STEL-1176 Data Sheet STEL-1176 80 MHz Decimal/BCD 0.1 Hz Resolution CMOSNumerically Controlled Oscillator R Powered by ICminer.com Electronic-Library Service CopyRight 2003 FEATURES FUNCTIONAL DESCRIPTION ■ HIGH CLOCK FREQUENCY The STEL-1176 Numerically Controlled Oscillator (NCO) uses digital techniques to provide a costeffective solution for the generation of low noise, high resolution signals. The NCO devices combines low power 1.5µ CMOS technology with a unique architectural design resulting in a power efficient, high-speed sinusoidal waveform generator. This performance is enhanced by its rapid frequency switching capability and parallel control interface. – 80 MHz MAXIMUM OVER COMMERCIAL OPERATING CONDITIONS ■ HIGH FREQUENCY RESOLUTION WITH DECIMAL FREQUENCY STEPS – PRECISELY 0.1 Hz @ 80 MHz ■ VERY HIGH SPEED FREQUENCY The STEL-1176 features high frequency resolution in a decimal format, with extremely low spurious signal levels and a high maximum operating frequency. The decimal frequency resolution allows frequencies to be generated in exact multiples of 0.1 Hz from a standard reference frequency, such as 10 MHz, and the divided clock output at 5 or 10 MHz is provided to facilitate this. The frequency control data format is 1-2-4-8 BCD, and the unique architecture allow the data to be loaded either as a 35-bit parallel word, for maximum speed, or as five bytes, for easy microprocessor interfacing. The STEL-1176 also features 3-bit phase modulation, allowing the output to be modulated with BPSK, QPSK or 8ary PSK data. HOPPING OR MODULATION – MAX. UPDATE SPEED 250 NANOSECS. ■ PRECISION PHASE MODULATION – 3 BITS FOR 8ARY PSK ■ HIGH RESOLUTION OUTPUT – 12 BITS ■ HIGH SPECTRAL PURITY – ALL SPURS < –72 dBc ■ PARALLEL OR BYTE-WIDE CONTROL INPUTS ■ LOW POWER DISSIPATION The output frequency can be calculated from the following equation: APPLICATIONS ■ PRECISION SYNTHESIZERS fo= ■ INSTRUMENTATION fc x ∆-Phase 8 x 108 where: fo is the frequency of the output signal and: fc is the clock frequency. ■ CARRIER GENERATION BLOCK DIAGRAM PHLD FRLD PHASE ADDR C SEL WRSTB ADDRESS SELEC T LOGIC -PHASE BUFFER REGISTERS DATA RESET 3 PHASE BUFFER REGISTER 3 35 35 -PHASE REGISTER 8 3/ 4 DEC ADE PHASE AC C UMULATOR 35 15 PHASE ALU 15 SINE LUT 12 OUT 35 TO ALL REGISTERS LDC LK C LKSEL ÷2/8/16 REFC LK C LOC K C IN STEL-1176 Powered by ICminer.com Electronic-Library Service CopyRight 2003 2 PIN CONFIGURATION Package: 84 pin PLCC Thermal coefficient, θja = 30°/W Package: 84 pin CLDCC Thermal coefficient, θja = 34°/W 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 Top View 0.145" max. 1 1 8 8 8 8 8 7 7 7 7 7 1 0 9 8 7 6 5 4 3 2 1 4 3 2 1 0 9 8 7 6 5 1 1 8 8 8 8 8 7 7 7 7 7 1 0 9 8 7 6 5 4 3 2 1 4 3 2 1 0 9 8 7 6 5 0.017" ± 0.004" (2) 1.190" ± 0.005" 0.05" nominal (1) 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 5 5 5 5 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 74 73 0.018" ± 0.004" (2) Top View 0.05" ± 0.005" (1) 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 5 5 5 5 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 0.200" max. 1.154" ± 0.004" 0.035" nominal 1.150" ± 0.012" Note: Tolerances on pin spacing are not cumulative. PIN CONNECTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 VSS RESET CIN CLKSEL ADDR0 ADDR1 ADDR2 WRSTB CSEL FRLD DATA0 VDD DATA1 DATA2 DATA3 DATA4 DATA5 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 DATA6 VSS VDD VSS VSS CLOCK VSS DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 VDD DATA15 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 DATA16 DATA17 DATA18 DATA19 DATA20 DATA21 DATA22 DATA23 VSS VSS DATA24 DATA25 DATA26 DATA27 DATA28 DATA29 DATA30 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 DATA31 DATA32 VDD DATA33 DATA34 I.C. VSS OUT0 OUT1 OUT2 OUT3 VSS VSS OUT4 OUT5 OUT6 OUT7 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 VSS OUT8 OUT9 OUT10 OUT11 VDD VDD LDCLK VSS REFCLK VSS PHLD PHASE0 PHASE1 PHASE2 VSS Note: I.C. denotes Internal Connection. These pins must be left unconnected. Do not use for vias. 3 Powered by ICminer.com Electronic-Library Service CopyRight 2003 STEL-1176 CIRCUIT DESCRIPTION The STEL-1176 features a dual mode input port which can be set up to allow either byte-wide or parallel loading of the BCD frequency control data. The input is double buffered, and the new frequency data is loaded on the first or second rising edge of the CLOCK (whichever occurs while LDCLK is low) after the falling edge of the FRLD signal. A 3-bit phase modulator is also incorporated, and the phase modulation (PM) data is loaded separately on its own bus. modulating function is at the output of the accumulator. The phase modulation may also be changed as rapidly as every clock cycle. Note that when a phase or frequency change occurs at the output the change is instantaneous, i.e., it occurs in one clock cycle, with complete phase coherence. A BCD technique is used to create an NCO with a frequency resolution which has a decimal relationship to the clock frequency. This is achieved by providing nearly nine decades of accumulation with a range of 0 to 799,999,999. Any value within this range may be loaded into the ∆-Phase register as a frequency control word. Within this range a total of 80 x 107 values exist, so that when the NCO is operating at a clock frequency of 80 MHz, the output frequency resolution will be precisely 0.1 Hz. The 80 MHz clock is divided by eight or sixteen internally, and the divided clock is provided as an output at 10 MHz or 5 MHz. This output can be used to phase lock the 80 MHz clock generator to a reference standard. ADDRESS SELECT LOGIC BLOCK This block controls the writing of data into the device via the DATA34-0 inputs and the PHASE2-0 inputs. The data is written into the device on the rising edge of the WRSTB input, and the mode (35-bit parallel or byte-wide) and register into which the data is written is selected by the ADDR2-0 inputs. The CSEL input can be used to selectively enable the writing of data from the bus. FUNCTION BLOCK DESCRIPTION ∆-PHASE BUFFER REGISTER BLOCK The ∆-Phase Buffer Register Block is used to temporarily store the ∆-Phase data written into the device. This allows the data to be written asynchronously as a 35-bit word or as five bytes per 35-bit ∆-Phase word. The data is transferred from these registers into the ∆-Phase Register after a falling edge on the FRLD input. The fifteen MSBs of the accumulator are used to address a unique lookup table. The lookup table generates a sinewave output with twelve bits of amplitude resolution. This results in a typical overall spurious performance of –72 dBc, or better. PHASE BUFFER REGISTER BLOCK The Phase Buffer Register Block is used to temporarily store the PM data written into the device. The data is transferred from this register into the Phase ALU after a falling edge on the PHLD input. The NCO generates a sampled sine wave where the sampling function is the clock. The practical upper limit of the NCO output frequency is about 40% of the clock frequency due to spurious components that are created by sampling. Those components are at frequencies greater than half the clock frequency, and become more difficult to remove by filtering. ∆-PHASE REGISTER BLOCK This block controls the updating of the ∆-Phase data used in the Accumulator. The frequency data from the ∆-Phase Buffer Register Block is loaded into this block after a falling edge on the FRLD input. The phase noise of the NCO output signal may be determined from the phase noise of the clock signal input and the ratio of the output frequency to the clock frequency. This ratio squared times the phase noise power of the clock specified in a given bandwidth is the phase noise power that may be expected in that same bandwidth relative to the output frequency. PHASE ACCUMULATOR BLOCK This block forms the core of the NCO function. It is a high-speed, pipelined, 35-bit parallel BCD accumulator, generating a new sum in every clock cycle. Unlike other NCOs, the arithmetic used in the STEL-1176 is BCD, making the resolution of the device decimal. The 35 bits make up 83/4 decades, so that the full-scale count of the accumulator is 799,999,999. This makes the frequency resolution 1 part in 800,000,000, or 0.1 Hz in 80 MHz. A carry input (the CIN input) allows the resolution of the accumulator The NCO achieves its high operating frequency by making extensive use of pipelining in its architecture. The pipeline delays within the NCO represent 37 clock cycles. The pipeline delay associated with the phase modulator is only 17 clock cycles, since the phase STEL-1176 Powered by ICminer.com Electronic-Library Service CopyRight 2003 4 DATA34 through DATA0 The 35-bit DATA34-0 bus is used to program the 35-bit ∆-Phase Register. DATA0 is the least significant bit of the bus. The data programmed into the ∆-Phase register in this way determines the output frequency of the NCO. The data will be loaded as a parallel 35bit word or as five bytes, depending on the state of the address bus, as shown in the address table. Each nibble (4 bits) of data starting at DATA3-0 represents one decade of frequency data in 1-2-4-8 BCD format. When the byte-wide mode is selected (addresses 000 to 100), the 35 data lines must be connected externally to form an 8-bit data bus as follows: to be expanded by means of an auxiliary NCO or phase accumulator. The overflow signal is discarded, since the required output is the modulo(8x108) sum only. This represents the modulo(2π) phase angle. PHASE ALU BLOCK The Phase ALU performs the addition of the PM data to the Phase Accumulator output. The PM data word is 3 bits wide, and this is added to the 3 most significant bits from the Phase Accumulator to form the 15-bit modulated phase used to address the lookup table. Connect DATA34-32 to DATA2-0, DATA31-24 to DATA23-16 to DATA15-8 to DATA7-0. SINE LOOKUP TABLE BLOCK This block is the sine memory. The 15 bits from the Phase Accumulator and ALU are used to address this memory to generate the 12-bit OUT11-0 outputs. PHASE2 through PHASE0 The 3-bit PHASE2-0 bus is used to program the 3-bit Phase Register. PHASE0 is the least significant bit of the bus. PHASE2 corresponds to an incremental phase shift of 180°, PHASE1 corresponds to an incremental phase shift of 90°, and PHASE0 corresponds to an incremental phase shift of 45°. CLOCK DIVIDER BLOCK The incoming system clock is divided by two and the half speed clock (LDCLK) is used in the ∆-Phase Register Block. The LDCLK is further divided by four or eight, depending on the state of the CLKSEL input, to provide the REFCLK output. This output may be used in a PLL circuit to lock the 80 MHz clock generator to a 10 MHz or 5 MHz reference standard. ADDR2 through ADDR0 The three address lines ADDR2-0 control the use of the DATA34-0 bus for writing frequency data to the ∆-Phase Buffer Register and the PHASE2-0 bus for writing phase data to the Phase Buffer Register, as shown in the table: INPUT SIGNALS RESET The RESET input is asynchronous and active low, and clears all the registers in the device. When RESET goes low, all registers are cleared within 13 nsecs, and normal operation will resume after this signal returns high. The data on the OUT11-0 bus will then be invalid for 10 clock cycles, and thereafter will remain at the value corresponding to zero phase (801H) until new frequency or phase data is loaded with the FRLD or PHLD inputs after the RESET returns high. ADDR2 ADDR1 ADDR0 Register Field 0 0 0 0 1 1 1 1 CLOCK All synchronous functions performed within the NCO are referenced to the rising edge of the CLOCK input. The CLOCK signal should nominally be a square wave at a maximum frequency of 80 MHz. A nonrepetitive CLOCK waveform is permissible as long as the minimum duration positive or negative pulse on the waveform is always greater than 5 nanoseconds. 0 1 0 1 0 1 0 1 ∆-Phase Bits 7-0 (LSB)1 ∆-Phase Bits 15-81 ∆-Phase Bits 23-161 ∆-Phase Bits 30-241 ∆-Phase Bits 34-321 Phase Bits 2-0 ∆-Phase Bits 34-02 ∆-Phase + Phase Bits3 It is not necessary to reload unchanged bytes, and the byte loading sequence may be random. Notes: 1. Byte-wide frequency loading mode. 2. Parallel frequency loading mode. 3. Loads the frequency data in the parallel mode and the phase data simultaneously. CSEL The Chip Select input is used to control the writing of data into the chip. It is active low. When this input is high all data writing via the DATA7-0 bus is inhibited. 5 Powered by ICminer.com Electronic-Library Service CopyRight 2003 0 0 1 1 0 0 1 1 STEL-1176 OUTPUT SIGNALS WRSTB The Write Strobe input is used to latch the data on the DATA34-0 and PHASE2-0 busses into the device. On the rising edge of the WRSTB input, the information on the busses is transferred to the buffer register selected by the ADDR2-0 bus. OUT11-0 The signal appearing on the OUT11-0 output bus is derived from the 15 most significant bits of the Phase Accumulator via the Phase ALU. The 12-bit sine function is presented in offset binary format. The value of the output for a given phase value follows the relationship when the phase modulation is zero: FRLD The Frequency Load input is used to control the transfer of the data from the ∆-Phase Buffer Registers to the ∆-Phase Register. The data at the output of the Buffer Registers must be valid from the falling edge of FRLD until after the next rising edge of LDCLK. The data is then transferred during the subsequent cycle. The frequency of the NCO output will change 37 clock cycles after the FRLD command due to pipelining delays if LDCLK was low at the time; otherwise it will change 38 clock cycles later. The maximum frequency update rate of the device is once every 9 clock cycles. OUT11-0=2047 x sin (360 x (phase+0.5)/8000)°+2048 The result is accurate to within 1 LSB. When the phase accumulator is zero, e.g., after a reset, the decimal value of the output is 2049 (801H). REFCLK The Reference Clock output signal is the CLOCK input divided by either eight or sixteen, depending on the state of the CLKSEL input. When the input clock frequency is set to 80 MHz to obtain precise 0.1 Hz resolution, the frequency of the REFCLK signal will then be either 10 or 5 MHz. It can be used in conjunction with a phase locked loop (PLL) to lock the 80 MHz clock generator to a reference standard frequency at one of these two frequencies. PHLD The Phase Load input is used to control the transfer of the data from the Phase Buffer Registers to the Phase ALU. The data at the output of the Buffer Register must be valid from the falling edge of PHLD until after the next rising edge of LDCLK. The data is then transferred during the subsequent cycle. The phase of the NCO output will change 17 clock cycles after the PHLD command due to pipelining delays if LDCLK was low at the time; otherwise it will change 18 clock cycles later. LDCLK The Load Clock output signal is the CLOCK input divided by two. This clock is used for loading the phase and frequency data from the buffer registers to the Phase ALU and ∆-Phase Register, respectively. This output can be used to determine the exact clock cycle during which these transfers will take place, as shown in the timing diagrams. The transfers will take place on the rising edge of the CLK following the falling edge of FRLD or PHLD when LDCLK is low. Since the propagation delay of this output from the rising edges of the CLOCK input is comparable to the clock period at 80 MHz, care should be taken when using this output to synchronize the phase and frequency changes. If this signal is not used, there is a 50% probability that the phase and frequency changes will occur one cycle of the CLOCK input later than specified. CIN The Carry Input is an arithmetic carry to the least significant bit of the Accumulator. Normal operation of the NCO requires that CIN be set at a logic 0. When CIN is set at a logic 1 the effective value of the ∆-Phase register is increased by one. This allows the resolution of the accumulator to be expanded for higher frequency resolution. CLKSEL The Clock Select input selects the frequency of the REFCLK output. When CLKSEL is set low the frequency of REFCLK will be the CLOCK frequency divided by eight, and when it is set high the frequency will be the CLOCK frequency divided by sixteen. STEL-1176 Powered by ICminer.com Electronic-Library Service CopyRight 2003 6 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Warning: Stresses greater than those shown below may cause permanent damage to the device. Exposure of the device to these conditions for extended periods may also affect device reliability. All voltages are referenced to VSS. Symbol Tstg Parameter Range Units –40 to +125 –65 to +150 Storage Temperature °C (Plastic package) °C (Ceramic package) VDDmax Supply voltage on VDD –0.3 to + 7 volts VI(max) Input voltage –0.3 to VDD + 0.3 volts Ii DC input current ± 10 mA RECOMMENDED OPERATING CONDITIONS Symbol VDD Ta Parameter Range Units Supply Voltage +5 ± 5% +5 ± 10% Volts (Commercial) Volts (Military) 0 to +50 –55 to +125 °C (Commercial) (70° Case) °C (Military) Operating Temperature (Ambient) D.C. CHARACTERISTICS (Operating Conditions: VDD= 5.0 V ±5%, VSS = 0 V, Ta= 0° to 50° C, Commercial VDD= 5.0 V ±10%, VSS = 0 V, Ta = –55° to 125° C, Military) Symbol Parameter Min. Typ. Max. Units Conditions mA Static, no clock IDD(Q) Supply Current, Quiescent 1.0 IDD Supply Current, Operational 3.0 mA/MHz VIH(min) High Level Input Voltage Standard Operating Conditions 2.0 volts Logic '1' Extended Operating Conditions 2.25 volts Logic '1' 0.8 volts Logic '0' 110 µA CIN and CSEL, VIN = VDD VIL(max) Low Level Input Voltage IIH(min) High Level Input Current IIH(min) High Level Input Current 10 µA All other inputs, VIN = VDD IIL(max) Low Level Input Current –10 µA CIN and CSEL, VIN = VSS IIL(max) Low Level Input Current –15 –45 –130 µA All other inputs, VIN = VSS VOH(min) High Level Output Voltage 2.4 4.5 volts IO = –4.0 mA VOL(max) Low Level Output Voltage IOS Output Short Circuit Current CIN COUT 10 0.2 0.4 volts IO = +4.0 mA 20 65 130 mA VOUT = VDD, VDD = max –10 –45 –130 mA VOUT = VSS, VDD = max pF pF All inputs All outputs Input Capacitance Output Capacitance 2 4 7 Powered by ICminer.com Electronic-Library Service CopyRight 2003 35 STEL-1176 NCO RESET SEQUENCE tRS RESET tSR 11 CLOCK EDGES CLOCK 1 2 3 4 5 6 7 8 10 11 9 LDCLK CLKSEL = 1 (÷ 8) REFCLK OUT CLKSEL = 0 (÷ 16) NOT VALID 11-0 801H NCO FREQUENCY CHANGE SEQUENCE CSEL ADDR 2-0 DON'T CARE DON'T CARE tSU WRSTB tHD DATA 7-0 tWR DON'T CARE DON'T CARE 37 CLOCK EDGES CLOCK tCC tCH tCL LDCLK tSU FRLD tW tCO OLD FREQUENCY OUT 11-0 STEL-1176 Powered by ICminer.com Electronic-Library Service CopyRight 2003 8 NEW FREQUENCY NCO PHASE CHANGE SEQUENCE CSEL ADDR 2-0 DON'T CARE DON'T CARE tSU WRSTB tHD DATA 7-0 DON'T CARE DON'T CARE 17 CLOCK EDGES CLOCK t CC t CH t CL LDCLK tSU PHLD tW t CO OLD PHASE NEW PHASE OUT 11-0 9 Powered by ICminer.com Electronic-Library Service CopyRight 2003 STEL-1176 ELECTRICAL CHARACTERISTICS VDD= 5.0 V ± 5%, VSS=0 V, Ta= 0° to 50° C, Commerical VDD= 5.0 V ± 10%, VSS=0 V, Ta=–55° to 125° C, Military) A.C. CHARACTERISTICS (Operating Conditions: Commercial Symbol Parameter Military Min. Typ. Max. Min. Typ. Max. Units Conditions tRS RESET pulse width 20 25 nsec. tSR RESET to CLOCK Setup 8 12 nsec. tSU DATA, ADDR or CSEL 6 8 nsec. 3 5 nsec. to WRSTB Setup, and FRLD or PHLD to CLOCK Setup tHD DATA, ADDR or CSEL to WRSTB Hold, and FRLD or PHLD to CLOCK Hold tCH CLOCK high 5 nsec. fCLK = 80 MHz tCL CLOCK low 5 nsec. fCLK = 80 MHz tCH CLOCK high 8 nsec. fCLK = 60 MHz tCL CLOCK low 8 nsec. fCLK = 60 MHz tW WRSTB, FRLD or PHLD 8 nsec. 5 pulse width tCO CLOCK to output delay 7 14 3 20 nsec. Load = 15 pF tCC CLOCK to LDCLK delay 7 20 3 28 nsec. Load = 15 pF tCR CLOCK to REFCLK delay 7 17 3 25 nsec. Load = 15 pF APPLICATIONS INFORMATION: LOCKING THE 80 MHz CLOCK GENERATOR FOR THE STEL-1176 TO A 10 MHz REFERENCE BCD FREQ. CONTROL 35 STEL-1176 NCO CLK 10MHz REF. PLL REFCLK 80 MHz OSCILLATOR STEL-1176 Powered by ICminer.com Electronic-Library Service CopyRight 2003 10 12 DAC 35 MHz LPF 0-35 MHz OUT APPLICATIONS INFORMATION: DATA BUS CONNECTIONS FOR DATA LOADING IN THE BYTE-WIDE MODE D34 D33 D32 D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 STEL-1176 SPECTRAL PURITY In many applications the NCO is used with a digital to analog converter (DAC) to generate an analog waveform which approximates an ideal sinewave. The spectral purity of this synthesized waveform is a function of many variables including the phase and amplitude quantization, the ratio of the clock frequency to output frequency, and the dynamic characteristics of the DAC. The sine signals generated by the STEL-1176 have 12 bits of amplitude resolution and 15 BCD bits of phase resolution which results in spurious levels which are theoretically at least 72 dB down. The highest output frequency the NCO can generate is half the clock frequency (fc/2), and the spurious components at frequencies greater than fc/2 can be removed by filtering. As the output frequency fo of the NCO 11 Powered by ICminer.com Electronic-Library Service CopyRight 2003 STEL-1176 approaches fc/2, the "image" spur at fc– fo (created by the sampling process) also approaches f c/2 from above. If the programmed output frequency is very close to fc/2 it will be virtually impossible to remove this image spur by filtering. For this reason, the maximum practical output frequency of the NCO should be limited to about 40% of the clock frequency. the second harmonic frequency will be higher than the Nyquist frequency, 50% of the clock frequency. When this happens, the image of the harmonic at the frequency fc– 2fo, which is not harmonically related to the output signal, will become intrusive since its frequency falls as the output frequency rises, eventually crossing the fundamental output when its frequency crosses through fc/3. It would be necessary to select a DAC with better dynamic linearity to improve the harmonic spur levels. (The dynamic linearity of a DAC is a function of both its static linearity and its dynamic characteristics, such as settling time and slew rates.) At higher output frequencies the waveform produced by the DAC will have large output changes from sample to sample. For this reason, the settling time of the DAC should be short in comparison to the clock period. As a general rule, the DAC used should have the lowest possible glitch energy as well as the shortest possible settling time. A spectral plot of the NCO output after conversion with a DAC (Sony CX20202A-1) is shown below. In this case, the clock frequency is 80 MHz and the output frequency is programmed to 12.3456789 MHz. This 10-bit DAC gives better performance than any of the currently available 12-bit DACs at clock frequencies higher than 10 or 20 MHz. The maximum nonharmonic spur level observed over the output frequency range shown in this case is –59 dBc. The spur levels are limited by the dynamic linearity of the DAC. It is important to remember that when the output frequency exceeds 25% of the clock frequency, TYPICAL SPECTRUM Center Frequency: 15.0 MHz Frequency Span: 30.0 MHz Reference Level: –10 dBm Resolution Bandwidth: 1 KHz Scale: Log, 10 dB/div Output frequency: 12.3456789 MHz Clock frequency: 80 MHz STEL-1176 Powered by ICminer.com Electronic-Library Service CopyRight 2003 12 Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intels Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel® products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. For Further Information Call or Write INTEL CORPORATION Cable Network Operation 350 E. Plumeria Drive, San Jose, CA 95134 Customer Service Telephone: (408) 545-9700 Technical Support Telephone: (408) 545-9799 FAX: (408) 545-9888 Copyright © Intel Corporation, December 15, 1999. All rights reserved Powered by ICminer.com Electronic-Library Service CopyRight 2003