Rev A PC404A Evaluation Module User’s Guide 1. Introduction The PC404A facilitates evaluation of the TAOS analog linear sensor arrays (TSL201, TSL202, TSL208, TSL1401, TSL1402, TSL1406, TSL1410, or TSL1301) by providing the necessary timing and clock signals to support the on-board imaging device. The designer is then free to investigate the properties and performance of the device without having to design and construct support circuitry. A single 5 volt regulated power supply (and light) are the only inputs required. An oscilloscope is required for observation and analysis of the output signals. 2. Functional Description The linear sensor array support circuitry of the PC404A consists of an oscillator, a counter/divider and logic to provide the imager with the required clock and integration pulse signals for operation. The oscillator is built around a TLC555 timer. The oscillator output is inverted and fed into divider U10 to provide lower frequency options. The clock frequency may PC404A Linear Array EVM DVdd 2MHz Clock 1 CLK DVdd DVdd R23 1 1 1 U9 470 U10 4 2 DIS 6 1 R24 Q 1 3 3 TR CV 5 11 74HC00 1 220 2MHz 1MHz 500KHz 3 13 12 14 15 CT=0 D Q CL Q 5 CLK 6 1 74HC74 DVdd C15 180p 8 10 9 7 6 5 3 2 CLK 9 Test Points TP10 1 74HC00 TP11 SO2 SI 11 1 CT=0 TP12 U11B 4 6 5 74HC00 1 SMD Bypass on Reverse Side DVdd 74HC4040 8 Pin/16 Pin Location TP13 CLK AO1 128uS 256uS 512uS 1mS 2mS 4mS 8mS 16mS 32mS 64mS Integration Time Control SO 1 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 U13 U11C 10 CLK PR 74HC4040 2 2 SI U12A 4 2 Clock Select CLK C14 .1 TLC555 2 1 10 2 THR 2 9 7 U11A R 7 2 2 2 U11D C16 C17 C18 C19 C20 C21 1 1 12 TP14 1 AO SI O TSL1401 GND 74HC00 8 Pin Jumper setting DVdd W1 1 2 3 Linear Array Device TP15 GND TSL1402 DVdd U14 TP16 DVdd 1 DVdd DVdd DVdd W2 8 Pin Jumper setting VCC 1 2 3 Jumper 1 1 C22 .1 2 1 C23 .1 2 1 C24 .1 2 1 C25 .1 2 1 2 SI CLK 3 AO1 4 5 SO2 6 7 DVdd C26 .1 1 13 TSL213 1 11 Vdd SI CLK AO1 GND SO 2 Vdd NC SO 1 GND NC SI 2 NC AO2 14 13 12 11 10 9 8 2 1 JP28 C27 10 1 TSL1402 2 DVdd 2 R25 330 1 Draftsman Tim Flanigan 2 2 Figure 1 - PC404A Schematic Diagram 1 2 Power 1 .1 .1 .1 .1 Jumper AO1 1 2 2 .1 2 .1 2 be selected from 2 MHz, 1 MHz and 500 kHz by moving the clock select jumper to the desired position (see Figure 1). U10, U11, and U12 generate the serial input (SI) pulse with the proper relationship to the clock (see Figure 2). The sensor integration time, defined by the time between SI clock pulses, may be selected from 128uS to 64mS by placing the jumper at the appropriate location. The analog output (AO) pin of the linear array is routed to the AO test terminal on the right side of the board, as are SI, clock (CLK), and serial out (SO) signals. The SO signal is generated by the linear array device (applies to TSL202, TSL208, TSL1402, TSL1406, and TSL1410 only). A supply terminal (DVdd) and 2 GND terminals are provided for applying +5 volts and common ground. Power may be applied through terminal block JP28 if desired. The analog output voltage is directly proportional to the light intensity and the integration time up to the devices saturation level (3.5V typ). The proportionality constant is the responsivity of the device given in (V*cm2/uW*sec). Responsivity is wavelength dependent. For the linear arrays the responsivity will peak at about 770nm. 0 1 2 128 129 CLK SI 1 2 128 AO Figure 2 - System Timing (AO output for TSL1401 shown) 3. Operation To operate the PC404A, apply 5VDC to the board using a regulated lab power supply. Connect an oscilloscope probe to the Ao terminal and the scope ground to one of the GND terminals. For best results, connect another probe to the SI terminal and use that signal to trigger the oscilloscope. Figure 3 - PC404A Silkscreen (top side) Table 1 - W1 and W2 Jumper Configuration DEVICE TSL1301 / 1401R / 201R TSL1402R / TSL202R TSL1406R / TSL1410R / TSL1412R TSL208 TSL210R TSL2014 JUMPER W1 Open 2-3 2-3 Open Open Open JUMPER W2 1-2 2-3 2-3 Open Open Open