TI TSL213

TSL213
64 × 1 INTEGRATED OPTO SENSOR
SOES009A – D4059, NOVEMBER 1992 – REVISED AUGUST 1993
•
•
Contains 64-Bit Static Shift Register
(TOP VIEW)
Contains Analog Buffer With Sample and
Hold for Analog Output Over Full Clock
Period
•
•
•
•
SI
CLK
AO
VDD
Single-Supply Operation
Operates With 500-kHz Shift Clock
1
8
2
7
3
6
4
5
VDD
GND
GND
NC
NC – No internal connection
8-Pin Clear Plastic DIP Package
Advanced LinCMOS Technology
description
The TSL213 integrated opto sensor consists of 64 charge-mode pixels arranged in a 64 × 1 linear array. Each
pixel measures 120 µm × 70 µm with 125-µm center-to-center spacing. Operation is simplified by internal logic
requiring only clock and start-integration-pulse signals.
The TSL213 is intended for use in a wide variety of applications including linear and rotary encoding, linear
positioning, edge and mark detection, and contact imaging.
The TSL213 is supplied in an 8-pin dual-in-line clear plastic package.
functional block diagram
VDD
8
1
2
3
64 Pixels
Sense
Node
Dark Pixel
Reference
Generator
Pixel Selector Switch
S1
Q1
SI
2
S3
Differential
Amplifier
Pixel
Buffer
Q2
Q3
64-Bit Shift Register
1
Sample
and
Hold
Output
Buffer
3 AO
RL
(external load)
S64
Nonoverlapping
Clock Generator
Reset
CLK
S2
Pixel
Buffer
Q64
Clock
Generator
Caution. These devices have limited built-in gate protection. The leads should be shorted together or the device placed in conductive
foam during storage or handling to prevent electrostatic damage to the MOS gates.
Advanced LinCMOS is a trademark of Texas Instruments Incorporated.
Copyright  1993, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
TSL213
64 × 1 INTEGRATED OPTO SENSOR
SOES009A – D4059, NOVEMBER 1992 – REVISED AUGUST 1993
Terminal Functions
PIN
DESCRIPTION
NAME
NO.
AO
3
Analog output
CLK
2
Clock. The clock controls charge transfer, pixel output, and reset.
GND
6, 7
Ground (substrate). All voltages are referenced to the substrate.
NC
5
No internal connection
SI
1
Serial input. The serial input defines the end of the integration period and initiates the pixel output sequence.
VDD
4, 8
Supply voltages. These supply power to the analog and digital circuits.
detailed description
sensor elements
The line of sensor elements, called pixels, consists of 64 discrete photosensing areas. Light energy striking a
pixel generates electron-hole pairs in the region under the pixel. The field generated by the bias on the pixel
causes the electrons to collect in the element while the holes are swept into the substrate. The amount of charge
accumulated in each element is directly proportional to the amount of incident light and the integration time.
device operation
Operation of the 64 × 1 array sensor consists of two time periods: an integration period during which charge is
accumulated in the pixels and an output period during which signals are transferred to the output. The integration
period is defined by the interval between serial-input (SI) pulses and includes the output period (see Figure 1).
The required length of the integration period depends upon the amount of incident light and the desired output
signal level.
sense node
On completion of the integration period, the charge contained in each pixel is transferred in turn to the sense
node under the control of the clock (CLK) and SI signals. The signal voltage generated at this node is directly
proportional to the amount of charge and inversely proportional to the capacitance of the sense node.
reset
An internal reset signal is generated by the nonoverlapping clock generator (NOCG) and occurs every clock
cycle. Reset establishes a known voltage on the sense node in preparation for the next charge transfer. This
voltage is used as a reference level for the differential signal amplifier.
shift register
The 64-bit shift register controls the transfer of charge from the pixels to the output stages and provides timing
signals for the NOCG. The SI signal provides the input to the shift register and is shifted under direct control
of the clock.
The output period is initiated by the presence of the SI input pulse coincident with a rising edge of CLK
(see Figures 1 and 2). The analog output voltage corresponds to the level of the first pixel after settling time (ts)
and remains constant for a minimum time, tv . A voltage corresponding to each succeeding pixel is available
at each rising edge of the clock. The output period ends on the rising edge of the 65th clock cycle, at which time
the output assumes the high-impedance state. The 65th clock cycle terminates the output of the last pixel and
clears the shift register in preparation for the next SI pulse. To achieve minimum integration time, the SI pulse
may be present on the 66th rising edge of the clock to immediately reinitiate the output phase. When the output
period has been initiated by an SI pulse, the clock must be allowed to complete 65 positive-going transitions
in order to reset the internal logic to a known state.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TSL213
64 × 1 INTEGRATED OPTO SENSOR
SOES009A – D4059, NOVEMBER 1992 – REVISED AUGUST 1993
sample and hold
The sample-and-hold signal generated by the NOCG is used to hold the analog output voltage of each pixel
constant until the next pixel is clocked out. The signal is sampled while CLK is high and held constant while CLK
is low.
nonoverlapping clock generators
The NOCG circuitry provides internal control signals for the sensor, including reset and pixel-charge sensing.
The signals are synchronous and are controlled by the outputs of the shift register.
initialization
Initialization of the sensor elements may be necessary on power up or during operation after any period of clock
or SI inactivity exceeding the integration time. The initialization phase consists of 12 to 15 consecutively
performed output cycles and clears the pixels of any charge that may have accumulated during the inactive
period.
output enable
The internally-generated output-enable signal enables the output stage of the sensor during the output period
(64 clock cycles). During the remainder of the integration period, the output stage is in the high-impedance state
that allows output interconnections of multiple devices without interference.
CLK
64 Cycles
Clock Continues or Remains Low After 65th Cycle
64 Cycles
tint
SI
AO
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
Analog
Output Period
Figure 1. Timing Waveforms
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
absolute maximum ratings, TA = 25°C (unless otherwise noted) (see Note 1)†
Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Digital input current range, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 20 mA to 20 mA
Operating case temperature range, TC (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 10°C to 85°C
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 25°C to 85°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Voltage values are with respect to the network GND.
2. Case temperature is the surface temperature of the plastic package measured directly over the integrated circuit.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
TSL213
64 × 1 INTEGRATED OPTO SENSOR
SOES009A – D4059, NOVEMBER 1992 – REVISED AUGUST 1993
recommended operating conditions
MIN
Supply voltage, VDD
Input voltage, VI
NOM
Low-level input voltage, VIL
UNIT
5.5
V
0
VDD
VDD
V
VDD × 0.7
0
High-level input voltage, VIH
MAX
4.5
V
VDD × 0.3
Wavelength of light source, λ
750
Clock input frequency, fclock
10
Pulse duration, CLK low, tw
1
500
kHz
µs
Sensor integration time, tint
5
Setup time, SI before CLK↑, tsu(SI)
50
Hold time, SI after CLK↑, th(SI)
50
V
nm
ms
ns
ns
External resistive load, AO, RL
Ω
330
Total number of TSL213 outputs connected together
10
Operating free-air temperature, TA
0
°C
70
electrical characteristics, VDD = 5 V, TA = 25°C, fclock = 180 kHz, λp = 565 nm, RL = 330 Ω,
CL = 330 pF, tint = 5 ms, Ee = 20 µW/cm2 (unless otherwise noted) (see Note 3)
PARAMETER
TEST CONDITIONS
MIN
TYP
3
3.4
Ee = 51 µW/cm2
Analog output voltage saturation level
Analog output voltage (white, average over 64 pixels)
Analog output voltage (dark, each pixel)
1.75
Output voltage (white) change with change in VDD
Ee = 0
VDD = 5 V ± 5%
Dispersion of analog output voltage
See Note 4
Linearity of analog output voltage
See Note 5
Pixel recovery time
See Note 6
Supply current
High-level input current
IDD Avg
VI = VDD
Low-level input current
VI = 0
MAX
V
2
0.25
UNIT
V
0.4
V
±2%
±10%
0.85
1.15
25
40
ms
4
9
mA
0.5
µA
0.5
µA
Input capacitance
5
pF
NOTES: 3. The input irradiance (Ee) is supplied by an LED array with λp = 565 nm.
4. Dispersion of analog output voltage is the maximum difference between the voltage from any single pixel and the average output
voltage from all pixels of the device under test.
5. Linearity of analog output voltage is calculated by averaging over 64 pixels and measuring the maximum deviation of the voltage at
2 ms and 3.5 ms from a line drawn between the voltage at 2.5 ms and the voltage at 5 ms.
6. Pixel recovery time is the time required for a pixel to go from the analog-output-voltage (white, average over 64 pixels) level to the
analog-output-voltage (dark, each pixel) level or vice versa after a step change in light input.
operating characteristics, VDD = 5 V, TA = 25°C, RL = 330 Ω, CL = 330 pF, tint = 5 ms, Ee = 20 µW/cm2,
fclock = 500 kHz (unless otherwise noted)
PARAMETER
ts
tv
TEST CONDITIONS
Settling time
See Figure 2 and Note 7
Valid time
NOTE 7: Clock duty cycle is assumed to be 50%.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MIN
TYP
MAX
1
1/2 fclock
UNIT
µs
µs
TSL213
64 × 1 INTEGRATED OPTO SENSOR
SOES009A – D4059, NOVEMBER 1992 – REVISED AUGUST 1993
PARAMETER MEASUREMENT INFORMATION
VDD
0.1 µF†
4
VDD
1
SI
SI
2
CLK
8
VDD
AO
3
AO
RL = 330 Ω
CLK
CL = 330 pF
TSL213
GND
6
GND
7
† Supply bypass capacitor with short leads should be placed as close to the device as possible.
TEST CIRCUIT
tw
1
2
64
65
5V
2.5 V
CLK
0V
tsu(SI)
5V
50%
SI
0V
th(SI)
ts
ts
AO
90%
90%
Pixel 64
Pixel 1
tv
OPERATIONAL WAVEFORMS
Figure 2. Test Circuit and Operational Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
TSL213
64 × 1 INTEGRATED OPTO SENSOR
SOES009A – D4059, NOVEMBER 1992 – REVISED AUGUST 1993
TYPICAL CHARACTERISTICS
INTEGRATION TIME
vs
IRRADIANCE FOR CONSTANT AVERAGE ANALOG
OUTPUT VOLTAGE
NORMALIZED RESPONSIVITY
vs
WAVELENGTH OF INCIDENT LIGHT
10
1
VDD = 5 V
λp = 565 nm
Analog Output Voltage (white,
average over 64 pixels) = 2 V
TA = 25°C
9
f int – Integration Time – ms
Normalized Responsivity
0.4
0.1
0.04
8
7
6
5
4
VDD = 5 V
TA = 25°C
tint = 3 ms
0.01
400
3
2
500
600
700
800
900
1000 1100
λ – Incident Wavelength – nm
0
5
10
15 20 25 30 35 40
Ee – Irradiance – µW/cm2
Figure 3
NORMALIZED OUTPUT VOLTAGE
vs
INTEGRATION TIME
300
1
VDD = 5 V
TA = 25°C
0.9
250
Output Voltage Normalized to 2.2 V
Analog Output Voltage (dark) – mV
50
Figure 4
ANALOG OUTPUT VOLTAGE (DARK)
vs
INTEGRATION TIME
200
150
100
VDD = 5 V
Ee = 0
TA = 25°C
50
1
2
Ee = 20 µW/cm2
0.8
0.7
Ee = 10 µW/cm2
0.6
0.5
0.4
0.3
Ee = 2 µW/cm2
0.2
0.1
0
4
7 10
20
40
70 100
0
2
3
tint – Integration Time – ms
Figure 5
6
45
4
5
6
7
8
tint – Integration Time – ms
Figure 6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
10
TSL213
64 × 1 INTEGRATED OPTO SENSOR
SOES009A – D4059, NOVEMBER 1992 – REVISED AUGUST 1993
mechanical data
This dual-in-line package consists of a circuit mounted on a lead frame and encapsulated with an electrically
nonconductive clear plastic compound.
Pin 1
Pin 2
Pin 3
Pin 4
Pin 5
Pin 6
Pin 7
Pin 8
10,92 (0.430)
9,40 (0.370)
Pixel 1 is centered
horizontally on Pin 1
SI
CLK
AO
VDD
NC
GND
GND
VDD
8
5
9,53 (0.325)
7,62 (0.300)
C
L (pixel)
C
L
0,32 (0.013)
6,60 (0.260)
6,10 (0.240)
1,91 (0.075)
1,02 (0.040)
0,76 (0.030) D NOM
1
4
0,51 (0.020) R NOM
4 Places
1,65 (0.065)
5,08 (0.200) 1,14 (0.045)
3,94 (0.155)
15° TYP
7° MAX TYP
1,6 (0.063)
1,5 (0.059)
Seating Plane
0,51 (0.020)
R MAX
4 Places
105°
90°
8 Places
0,30 (0.012)
0,20 (0.008)
7,62 (0.300)
T.P.
1,27 (0.050)
0,51 (0.020)
1,52 (0.060)
0,38 (0.015)
1,65 (0.065)
1,14 (0.045)
3,81 (0.150)
3,18 (0.125)
0,56 (0.022)
0,36 (0.014)
2,54 (0.100) T.P.
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor
product or service without notice, and advises its customers to obtain the latest version of relevant information
to verify, before placing orders, that the information being relied on is current.
TI warrants performance of its semiconductor products and related software to the specifications applicable at
the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are
utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each
device is not necessarily performed, except those mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death, personal injury, or
severe property or environmental damage (“Critical Applications”).
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED
TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI
products in such applications requires the written approval of an appropriate TI officer. Questions concerning
potential risk applications should be directed to TI through a local SC sales office.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards should be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein. Nor does TI warrant or represent that any license, either
express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property
right of TI covering or relating to any combination, machine, or process in which such semiconductor products
or services might be or are used.
Copyright  1995, Texas Instruments Incorporated