ETC TSL1410R

TSL1410R
1280 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS043 – AUGUST 2002
1280 × 1 Sensor-Element Organization
400 Dot-Per-Inch (DPI) Sensor Pitch
High Linearity and Uniformity
Wide Dynamic Range . . . 4000:1 (72 dB)
Output Referenced to Ground
Low Image Lag . . . 0.5% Typ
Operation to 8 MHz
Single 3-V to 5-V Supply
Rail-to-Rail Output Swing (AO)
No External Load Resistor Required
Replacement for TSL1410
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
Description
The TSL1410R linear sensor array consists of two
sections of 640 photodiodes, each with
associated charge amplifier circuitry, aligned to
form a contiguous 1280 × 1 pixel array. The device
incorporates a pixel data-hold function that
provides simultaneous-integration start and stop
times for all pixels. The pixels measure 63.5 µm by
55.5 µm with 63.5-µm center-to-center spacing
and 8-µm spacing between pixels. Operation is
simplified by internal logic that requires only a
serial-input (SI) pulse and a clock.
VPP
SI1
HOLD1
CLK1
GND
AO1
SO1
SI2
HOLD2
CLK2
SO2
AO2
VDD
The device is intended for use in a wide variety of applications including mark and code reading, OCR and
contact imaging, edge detection and positioning, and optical encoding.
Functional Block Diagram (each section)
13
Pixel 1 (641)
Pixel
2
(642)
Integrator
Reset
Pixel
3
(643)
Pixel
640
(1280)
Analog
Bus
_
Output
Buffer
VDD
6, 12
AO
+
Sample/
Output
5
Gain
Trim
Switch Control Logic
7, 11
3, 9
Hold
CLK
SI
Hold
Q1
4,10
Q2
GND
Q3
SO
Q640 (Q1280)
640-Bit Shift Register (2 each)
2,8
The LUMENOLOGY Company
Copyright 2002, TAOS Inc.
Texas Advanced Optoelectronic Solutions Inc.
800 Jupiter Road, Suite 205 Plano, TX 75074 (972)
673-0759
www.taosinc.com
1
TSL1410R
1280 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS043 – AUGUST 2002
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
AO1
6
O
Analog output, section 1.
AO2
12
O
Analog output, section 2.
CLK1
4
I
Clock, section 1. CLK1 controls charge transfer, pixel output, and reset.
CLK2
10
I
Clock, section 2. CLK2 controls charge transfer, pixel output, and reset.
GND
5
HOLD1
3
I
Hold signal. HOLD1 shifts pixel data to parallel buffer. HOLD1 is normally connected to SI1 and HOLD2 in
serial mode and to SI1 in parallel mode.
HOLD2
9
I
Hold signal. HOLD2 shifts pixel data to parallel buffer. HOLD2 is normally connected to SI2 in parallel mode.
SI1
2
I
Serial input (section 1). SI1 defines the start of the data-out sequence.
SI2
8
I
Serial input (section 2). SI2 defines the start of the data-out sequence.
SO1
7
O
Serial output (section 1). SO1 provides a signal to drive the SI2 input in serial mode.
SO2
11
O
Serial output (section 2). SO2 provides a signal to drive the SI input of another device for cascading or as an
end-of-data indication.
VDD
13
Supply voltage for both analog and digital circuitry.
VPP
1
Normally grounded.
Ground (substrate). All voltages are referenced to GND.
Detailed Description
The sensor consists of 1280 photodiodes, called pixels, arranged in a linear array. Light energy impinging on a pixel
generates photocurrent that is then integrated by the active integration circuitry associated with that pixel.
During the integration period, a sampling capacitor connects to the output of the integrator through an analog switch. The
amount of charge accumulated at each pixel is directly proportional to the light intensity on that pixel and the integration time.
The output and reset of the integrators are controlled by a 640-bit shift register and reset logic. An output cycle is initiated
by clocking in a logic 1 on SI. Another signal, called HOLD, is generated from the rising edge of SI1 when SI1 and HOLD1
are connected together. This causes all 640 sampling capacitors to be disconnected from their respective integrators and
starts an integrator reset period. As the SI pulse is clocked through the shift register, the charge stored on the sampling
capacitors is sequentially connected to a charge-coupled output amplifier that generates a voltage on analog output AO.
The integrator reset period ends 18 clock cycles after the SI pulse is clocked in. Then the next integration period begins.
On the 640th clock rising edge, the SI pulse is clocked out on the SO1 pin (section 1) and becomes the SI pulse for section
2 (when SO1 is connected to SI2). The rising edge of the 641st clock cycle terminates the SO1 pulse, and returns the analog
output AO of section 1 to high-impedance state. Similarly, SO2 is clocked out on the 1280th clock pulse. Note that a 1281st
clock pulse is needed to terminate the SO2 pulse and return AO of Section 2 to the high-impedance state. Sections 1 and
2 may be operated in parallel or in serial fashion.
AO is an op amp-type output that does not require an external pull-down resistor. This design allows a rail-to-rail
output voltage swing. With VDD = 5 V, the output is nominally 0 V for no light input, 2 V for normal white level, and 4.8 V
for saturation light level. When the device is not in the output phase, AO is in a high-impedance state.
The voltage developed at analog output (AO) is given by:
Vout = Vdrk + (Re) (Ee)(tint)
where:
Vout
Vdrk
Re
Ee
tint
is
is
is
is
is
the analog output voltage for white condition
the analog output voltage for dark condition
the device responsivity for a given wavelength of light given in V/(µJ/cm2)
the incident irradiance in µW/cm2
integration time in seconds
A 0.1 µF bypass capacitor should be connected between VDD and ground as close as possible to the device.
Copyright 2002, TAOS Inc.
The LUMENOLOGY Company
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TSL1410R
1280 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS043 – AUGUST 2002
Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3V
Input clamp current, IIK (VI < 0) or (VI > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA to 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25 mA to 25 mA
Voltage range applied to any output in the high impedance or power-off state, VO . . . –0.3 V to VDD + 0.3 V
Continuous output current, IO (VO = 0 to VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25 mA to 25 mA
Continuous current through VDD or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40 mA to 40 mA
Analog output current range, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25 mA to 25 mA
Maximum light exposure at 638 nm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mJ/cm2
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25°C to 85°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating Conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Recommended Operating Conditions
MIN
NOM
Supply voltage, VDD
3
5
Input voltage, VI
0
High-level input voltage, VIH
Low-level input voltage, VIL
VDD × 0.7
Wavelength of light source, λ
400
0
Clock frequency, fclock
5
MAX
UNIT
5.5
V
VDD
V
VDD
V
VDD × 0.3
V
1100
nm
8000
kHz
Sensor integration time, Serial, tint
0.162
100
ms
Sensor integration time, Parallel, tint
Setup time, serial input, tsu(SI)
0.082
100
ms
20
Hold time, serial input, th(SI) (see Note 1)
0
Operating free-air temperature, TA
0
Load capacitance, CL
Load resistance, RL
300
ns
ns
70
°C
330
pF
Ω
NOTE 1: SI must go low before the rising edge of the next clock pulse.
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Copyright 2002, TAOS Inc.
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TSL1410R
1280 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS043 – AUGUST 2002
Electrical Characteristics at fclock = 1 MHz, VDD = 5 V, TA = 25°C, λp = 640 nm, tint = 5 ms,
RL = 330 Ω, Ee = 12.5 µW/cm2 (unless otherwise noted) (see Note 2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1.6
2
2.4
UNIT
V
0
0.1
0.3
V
Vout
Analog output voltage (white, average over 1280 pixels)
See Note 3
Vdrk
Analog output voltage (dark, average over 1280 pixels)
Ee = 0
PRNU
Pixel response nonuniformity
See Note 4
Nonlinearity of analog output voltage
See Note 5
±0.4%
Output noise voltage
See Note 6
1
Re
Responsivity
See Note 7
78
112
4.8
Analog output saturation voltage
VDD = 5 V, RL = 330 Ω
4.5
Vsat
VDD = 3 V, RL = 330 Ω
2.5
2.8
SE
Saturation exposure
DSNU
Dark signal nonuniformity
All pixels, Ee = 0, See Note 9
IL
Image lag
See Note 10
IDD
Supply current
IIH
High-level input current
VI = VDD
IIL
Low-level input current
VI = 0
Ci
Input capacitance, SI
25
pF
Ci
Input capacitance, CLK
25
pF
±20%
VDD = 5 V, See Note 8
155
VDD = 3 V, See Note 8
90
0.05
mVrms
V/
(µJ/cm 2)
V
nJ/cm 2
0.15
V
0.5%
VDD = 5 V, Ee = 0
30
45
VDD = 3 V, Ee = 0
25
40
mA
10
µA
10
µA
NOTES: 2. All measurements made with a 0.1 µF capacitor connected between VDD and ground.
3. The array is uniformly illuminated with a diffused LED source having a peak wavelength of 640 nm.
4. PRNU is the maximum difference between the voltage from any single pixel and the average output voltage from all pixels of the
device under test when the array is uniformly illuminated at the white irradiance level. PRNU includes DSNU.
5. Nonlinearity is defined as the maximum deviation from a best-fit straight line over the dark-to-white irradiance levels, as a percent
of analog output voltage (white).
6. RMS noise is the standard deviation of a single-pixel output under constant illumination as observed over a 5-second period.
7. Re(min) = [Vout(min) – Vdrk(max)] ÷ (Ee × tint)
8. SE(min) = [Vsat(min) – Vdrk(min)] × 〈Ee × tint) ÷ [Vout(max) – Vdrk(min)]
9. DSNU is the difference between the maximum and minimum output voltage for all pixels in the absence of illumination.
10. Image lag is a residual signal left in a pixel from a previous exposure. It is defined as a percent of white-level signal remaining after
a pixel is exposed to a white condition followed by a dark condition:
IL V out (IL) V drk
100
V out (white) V drk
Timing Requirements (see Figure 1 and Figure 2)
MIN
tsu(SI)
Setup time, serial input (see Note 11)
th(SI)
Hold time, serial input (see Note 11 and Note 12)
tpd(SO)
Propagation delay time, SO
tw
Pulse duration, clock high or low
50
tr, tf
Input transition (rise and fall) time
0
NOM
MAX
20
UNIT
ns
0
ns
50
ns
ns
500
ns
NOTES: 11. Input pulses have the following characteristics: tr = 6 ns, tf = 6 ns.
12. SI must go low before the rising edge of the next clock pulse.
Copyright 2002, TAOS Inc.
The LUMENOLOGY Company
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TSL1410R
1280 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS043 – AUGUST 2002
Dynamic Characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figures 7 and 8)
PARAMETER
ts
Analog output settling time to ±1%
tpd(SO)
Propagation delay time, SO1, SO2
TEST CONDITIONS
RL = 330 Ω,
MIN
CL = 50 pF
TYP
MAX
UNIT
120
ns
50
ns
TYPICAL CHARACTERISTICS
CLK
SI1
Internal
Reset
Integration
18 Clock Cycles
tint
Not Integrating
Integrating
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ
1281 Clock Cycles
AO
Hi-Z
Hi-Z
Figure 1. Timing Waveforms (serial connection)
tw
1
2
640
641
5V
2.5 V
CLK
0V
tsu(SI)
5V
SI
50%
0V
th(SI)
tpd(SO)
tpd(SO)
SO
ts
AO
Pixel 1
Pixel 640
Figure 2. Operational Waveforms (Each Section)
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Copyright 2002, TAOS Inc.
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TSL1410R
1280 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS043 – AUGUST 2002
TYPICAL CHARACTERISTICS
NORMALIZED IDLE SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
PHOTODIODE SPECTRAL RESPONSIVITY
1
2
IDD — Normalized Idle Supply Current
TA = 25°C
Normalized Responsivity
0.8
0.6
0.4
0.2
0
300
1.5
1
0.5
0
400
500
600
700
800
900
1000 1100
0
10
λ – Wavelength – nm
40
50
Figure 3
Figure 4
WHITE OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
DARK OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
60
70
0.10
VDD = 5 V
tint = 0.5 ms to 15 ms
tint = 0.5 ms
tint = 1 ms
VDD = 5 V
0.09
Vout — Output Voltage
1.5
1
0.08
tint = 15 ms
tint = 5 ms
tint = 2.5 ms
0.07
0.5
0
0.06
0
10
20
30
40
60
50
TA – Free-Air Temperature – °C
70
0
10
20
30
40
60
50
TA – Free-Air Temperature – °C
Figure 5
Copyright 2002, TAOS Inc.
70
Figure 6
The LUMENOLOGY Company
6
30
TA – Free-Air Temperature – °C
2
Vout — Output Voltage — V
20
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TSL1410R
1280 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS043 – AUGUST 2002
TYPICAL CHARACTERISTICS
SETTLING TIME
vs.
LOAD
SETTLING TIME
vs.
LOAD
600
600
VDD = 3 V
Vout = 1 V
VDD = 5 V
Vout = 1 V
500
470 pF
Settling Time to 1% — ns
Settling Time to 1% — ns
500
400
220 pF
300
200
100 pF
100
470 pF
400
220 pF
300
200
100 pF
100
10 pF
10 pF
0
0
200
400
600
800
RL — Load Resistance – 1000
0
0
200
400
600
800
RL — Load Resistance – Figure 7
1000
Figure 8
APPLICATION INFORMATION
1
1
2
3
4
2
3
4
SI1/HOLD1/HOLD2
CLK1 and CLK2
5
6
CLK1 and CLK2
5
6
7
SO1
SI2
8
9
10
11
12
13
SI1/HOLD1
7
AO1
SO1
8
SI2/HOLD2
9
10
11
12
SO2
AO1/AO2
13
VDD
SERIAL
SO2
AO2
VDD
PARALLEL
Figure 9. Operational Connections
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Copyright 2002, TAOS Inc.
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TSL1410R
1280 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS043 – AUGUST 2002
MECHANICAL DATA
TOP VIEW
0.100 (2,54) x 12 = 1.2 (30,48))
(Tolerance Noncumulative)
0.270 (0,69)
0.121 (0,53)
13 Places
0.158 (4,01)
0.150 (3,81)
1.170 (29,72)
1.160 (29,46)
0.075 (0,191)
0.100 (2,54)
BSC
To Pixel 1
1
13
0.242 (6,15)
0.222 (5,64)
0.510 (12,95)
0.490 (12,45)
0.090 (2,28)
DIA (2 Places)
Centerline of Pixels is on the
Centerline of Mounting Holes
DETAIL A
3.535(89,79)
3.525 (89,54)
3.705 (94,11)
3.695 (93,85)
Cover Glass
(Index of Refraction = 1.52)
0.130 (3,30)
0.120 (3,05)
0.015 (0,38) Typical Free Area
ÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈ
0.027 (0,690)
Linear Array
0.048 (1,22)
0.038 (0,97)
ÌÌÌÌÌÌ
ÌÌÌÌÌÌ
Cover Glass
Bonded Chip
Bypass Cap
DETAIL A
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Pixel centers are in line with center line of mounting holes.
Figure 10. TSL1410R Mechanical Specifications
Copyright 2002, TAOS Inc.
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TSL1410R
1280 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS043 – AUGUST 2002
PRODUCTION DATA — information in this document is current at publication date. Products conform to
specifications in accordance with the terms of Texas Advanced Optoelectronic Solutions, Inc. standard
warranty. Production processing does not necessarily include testing of all parameters.
NOTICE
Texas Advanced Optoelectronic Solutions, Inc. (TAOS) reserves the right to make changes to the products contained in this
document to improve performance or for any other purpose, or to discontinue them without notice. Customers are advised
to contact TAOS to obtain the latest product information before placing orders or designing TAOS products into systems.
TAOS assumes no responsibility for the use of any products or circuits described in this document or customer product
design, conveys no license, either expressed or implied, under any patent or other right, and makes no representation that
the circuits are free of patent infringement. TAOS further makes no claim as to the suitability of its products for any particular
purpose, nor does TAOS assume any liability arising out of the use of any product or circuit, and specifically disclaims any
and all liability, including without limitation consequential or incidental damages.
TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS, INC. PRODUCTS ARE NOT DESIGNED OR INTENDED FOR
USE IN CRITICAL APPLICATIONS IN WHICH THE FAILURE OR MALFUNCTION OF THE TAOS PRODUCT MAY
RESULT IN PERSONAL INJURY OR DEATH. USE OF TAOS PRODUCTS IN LIFE SUPPORT SYSTEMS IS EXPRESSLY
UNAUTHORIZED AND ANY SUCH USE BY A CUSTOMER IS COMPLETELY AT THE CUSTOMER’S RISK.
LUMENOLOGY is a registered trademark, and TAOS, the TAOS logo, and Texas Advanced Optoelectronic Solutions are trademarks of
Texas Advanced Optoelectronic Solutions Incorporated.
The LUMENOLOGY Company
Copyright 2002, TAOS Inc.
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TSL1410R
1280 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS043 – AUGUST 2002
Copyright 2002, TAOS Inc.
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