INFINEON TDK5111F

Dat a Sh ee t , V 1. 1 , S ep t em be r 20 0 7
TDK5111F
315 M Hz ASK/ FS K Transm i tte r in 10 -p in
Package
Ver s i on 1 .1
W i re l e s s C o n t r o l
Co mpo ne nts
N e v e r
s t o p
t h i n k i n g .
Edition 2007-09-18
Published by Infineon Technologies AG,
Am Campeon 1-12
85579 Neubiberg, Germany
© Infineon Technologies AG 2007.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or the Infineon Technologies Companies and our Infineon Technologies
Representatives worldwide (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Dat a Sh ee t , V 1. 1 , S ep t em be r 20 0 7
TDK5111F
315 M Hz ASK/ FS K Transm i tte r in 10 -p in
Package
Ver s i on 1 .1
W i re l e s s C o n t r o l
Co mpo ne nts
N e v e r
s t o p
t h i n k i n g .
TDK5111F
Revision History:
2007-09-18
Previous Version:
V1.0 as of March 2005
V 1.1
Page
Subjects (major changes since last revision)
27
Increased ESD-values
28-30,32
Added Max.-and Min.-values (Current, Power)
32
Added output power and temperature drift of output power values
28, 30, 32
Added values of frequency range and for possible enhance of frequency
range
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
[email protected]
TDK5111F
Table of Contents
Page
1
1.1
1.2
1.3
Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
2.1
2.2
2.3
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.4.4.1
2.4.4.2
2.4.4.3
2.4.4.4
2.4.5
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Definition and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Functional Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PLL Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PLL Enable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Transmit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Recommended Timing Diagrams for ASK- and FSK-Modulation . . . . . 17
3
3.1
3.2
3.3
3.4
3.5
3.6
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50 Ohm-Output Testboard Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50 Ohm-Output Testboard Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bill of Material (50 Ohm-Output Evalboard) . . . . . . . . . . . . . . . . . . . . . . . .
Application Hints on the Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . .
Design Hints on the Clock Output (CLKOUT) . . . . . . . . . . . . . . . . . . . . . .
Application Hints on the Power-Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . .
19
19
20
21
22
24
25
4
4.1
4.1.1
4.2
4.3
4.3.1
4.3.2
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC/DC Characteristic at 3V, 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC/DC Characteristic at 2.1V ...4.0 V, -40°C ...+125°C . . . . . . . . . . . .
27
27
27
28
28
28
30
5
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Data Sheet
5
6
6
6
6
V 1.1, 2007-09-18
TDK5111F
Product Description
1
Product Description
1.1
Overview
The TDK 5111 F is a single chip ASK/FSK transmitter for operation in the frequency band
311 ... 317 MHz. The IC offers a high level of integration and needs only a few external
components. The device contains a fully integrated PLL synthesizer and a high efficiency
power amplifier to drive a loop antenna. A special circuit design and an unique power
amplifier design are used to save current consumption and therefore to save battery life.
Additional features are a power down mode and a divided clock output.
1.2
•
•
•
•
•
•
•
•
•
•
•
•
•
fully integrated frequency synthesizer
VCO without external components
ASK and FSK modulation
frequency range 311 ... 317 MHz
high efficiency power amplifier (typically 10 dBm)
low supply current
voltage supply range 2.1 ... 4 V
temperature range −40 ... +125°C
power down mode
crystal oscillator 9.84 MHz
FSK-switch
divided clock output for µC
low external component count
1.3
•
•
•
•
•
Features
Application
Tire pressure monitoring systems
Keyless entry systems
Remote control systems
Alarm systems
Communication systems
Table 1
Order information
Type
Ordering Code
Package
TDK5111F
SP000056181
PG-TSSOP-10
available on tape and reel
Data Sheet
6
V 1.1, 2007-09-18
TDK5111F
Functional Description
2
Functional Description
2.1
Pin Configuration
Figure 1
2.2
CLKOUT
1
10
PDWN
VS
2
9
PAOUT
GND
3
8
PAGND
FSKOUT
4
7
FSKDTA
COSC
5
6
ASKDTA
TDK 5111F
IC Pin Configuration
Pin Definition and Functions
Table 2
Pin Definition and Functions - Overview
Pin
No.
Symbol
Function
1
CLKOUT
Clock Driver Output (615.2 kHz)
2
VS
Voltage Supply
3
GND
Ground
4
FSKOUT
Frequency Shift Keying Switch Output
5
COSC
Crystal Oscillator Input (9.84 MHz)
6
ASKDTA
Amplitude Shift Keying Data Input
7
FSKDTA
Frequency Shift Keying Data Input
8
PAGND
Power Amplifier Ground
9
PAOUT
Power Amplifier Output (315 MHz)
10
PDWN
Power Down Mode Control
Data Sheet
7
V 1.1, 2007-09-18
TDK5111F
Functional Description
Table 3
Pin Definition and Function1
Pin
No.
Symbol
1
CLKOUT
Interface Schematic
Function
Clock output to supply an external
device.
An external pull-up resistor has to
be added in accordance to the
driving requirements of the
external device.
VS
1
300 Ω
The clock frequency is 615.2 kHz.
2
VS
This pin is the positive supply of
the transmitter electronics.
An RF bypass capacitor should be
connected directly to this pin and
returned to GND (pin 3) as short
as possible.
3
GND
General ground connection.
4
FSKOUT
This pin is connected to a switch to
GND (pin 3).
VS
VS
200 µA
120 kΩ
4
The switch is closed when the
signal at FSKDTA (pin 7) is in a
logic low state.
The switch is open when the signal
at FSKDTA (pin 7) is in a logic high
state.
200 kΩ
FSKOUT can switch an additional
capacitor to the reference crystal
network to pull the crystal
frequency by an amount resulting
in the desired FSK frequency shift
of the transmitter output
frequency.
Data Sheet
8
V 1.1, 2007-09-18
TDK5111F
Functional Description
Pin
No.
Symbol
5
COSC
Interface Schematic
Function
VS
VS
6 kΩ
5
This pin is connected to the
reference oscillator circuit.
The reference oscillator is working
as a negative impedance
converter. It presents a negative
resistance in series to an
inductance at the COSC pin.
100 µA
6
ASKDTA
VS
Digital amplitude modulation can
be imparted to the Power Amplifier
through this pin.
+1.2 V
60 kΩ
6
+1.1 V
90 kΩ
2.3 pF
A logic high (ASKDTA > 1.5 V or
open) enables the Power
Amplifier.
30 µA
A logic low (ASKDTA < 0.5 V)
disables the Power Amplifier.
Data Sheet
9
V 1.1, 2007-09-18
TDK5111F
Functional Description
Pin
No.
Symbol
7
FSKDTA
Interface Schematic
VS
Function
+1.2 V
60 kΩ
7
+1.1 V
Digital frequency modulation can
be imparted to the Xtal Oscillator
by this pin. The VCO-frequency
varies in accordance to the
frequency of the reference
oscillator.
90 kΩ
30 µA
A logic high (FSKDTA > 1.5V or
open) sets the FSK switch to a
high impedance state.
A logic low (FSKDTA < 0.5 V)
closes the FSK switch from
FSKOUT (pin 4) to GND (pin 3).
A capacitor can be switched to the
reference crystal network this way.
The Xtal Oscillator frequency will
be shifted giving the designed FSK
frequency deviation.
Data Sheet
10
V 1.1, 2007-09-18
TDK5111F
Functional Description
Pin
No.
Symbol
8
PAGND
Interface Schematic
Function
9
9
PAOUT
10
PDWN
8
Ground connection of the power
amplifier.
The RF ground return path of the
power amplifier output PAOUT
(pin 9) has to be concentrated to
this pin.
RF output pin of the transmitter.
A DC path to the positive supply
VS has to be supplied by the
antenna matching network.
Disable pin for the complete
transmitter circuit.
VS
40 µA ∗ (ASKDTA+FSKDTA)
A logic low (PDWN < 0.7 V) turns
off all transmitter functions.
5 kΩ
10
"ON"
A logic high (PDWN > 1.5 V) gives
access to all transmitter functions.
150 kΩ
PDWN input will be pulled up by
40 µA internally by either setting
FSKDTA or ASKDTA to a logic
high-state.
250 kΩ
1) Indicated voltages and currents apply for PLL Enable Mode and Transmit Mode.
In Power Down Mode, the values are zero or high-ohmic.
Data Sheet
11
V 1.1, 2007-09-18
Figure 2
Data Sheet
Crystal
9.84 MHz
FSK
Switch
5
4
XTAL
Osc
12
Ground
Clock
Output
LF
VCO
Power
Supply
2
Power
Supply
VS
3
:64
OR
10
Power
Down
Control
1
:16
PFD
6
ASK
Data
Input
:2
On
Power
AMP
Power
Amplifier
Output
Power
Amplifier
Ground
9
8
2.3
7
FSK
Data
Input
TDK5111F
Functional Description
Functional Block Diagram
Functional Block Diagram
V 1.1, 2007-09-18
TDK5111F
Functional Description
2.4
Functional Block Description
2.4.1
PLL Synthesizer
The Phase Locked Loop synthesizer consists of a Voltage Controlled Oscillator (VCO),
an asynchronous divider chain, a phase detector, a charge pump and a loop filter. It is
fully implemented on chip. The tuning circuit of the VCO consisting of spiral inductors
and varactor diodes is on chip, too. Therefore no additional external components are
necessary. The nominal center frequency of the VCO is 630MHz. The oscillator signal is
fed both, to the synthesizer divider chain and (via a 1:2 divider) to the power amplifier.
The overall division ratio of the asynchronous synthesizer divider chain is 64. The phase
detector is a Type IV PD with charge pump. The passive loop filter is realized on chip.
2.4.2
Crystal Oscillator
The crystal oscillator operates at 9.84 MHz.
The crystal frequency is divided by 16. The resulting 615.2 kHz are available at the clock
output CLKOUT (pin1) to drive the clock input of a micro controller.
To achieve FSK transmission, the oscillator frequency can be detuned by a fixed amount
by switching an external capacitor via FSKOUT (pin 4).
The condition of the switch is controlled by the signal at FSKDTA (pin 7).
Table 4
FSKDTA - FSK Switch
FSKDTA (pin7)
FSK Switch
Low1)
CLOSED
2)
3)
Open , High
OPEN
1) Low:
Voltage at pin < 0.5V
2) Open:
Pin open
3) High:
Voltage at pin > 1.5V
2.4.3
Power Amplifier
The VCO frequency is divided by 2 and fed to the Power Amplifier.
The Power Amplifier can be switched on and off by the signal at ASKDTA (pin 6).
Data Sheet
13
V 1.1, 2007-09-18
TDK5111F
Functional Description
Table 5
ASKDTA - Power Amplifier
ASKDTA (pin6)
Power Amplifier
1)
Low
OFF
Open2), High3)
ON
1) Low:
Voltage at pin < 0.5V
2) Open:
Pin open
3) High:
Voltage at pin > 1.5V
The Power Amplifier has an Open Collector output at PAOUT (pin 9) and requires an
external pull-up coil to provide bias. The coil is part of the tuning and matching LC
circuitry to get best performance with the external loop antenna. To achieve the best
power amplifier efficiency, the high frequency voltage swing at PAOUT (pin 9) should be
twice the supply voltage.
The power amplifier has its own ground pin PAGND (pin 8) in order to reduce the amount
of coupling to the other circuits.
2.4.4
Power Modes
The IC provides three power modes, the POWER DOWN MODE, the PLL ENABLE
MODE and the TRANSMIT MODE.
2.4.4.1
Power Down Mode
In the POWER DOWN MODE the complete chip is switched off.
The current consumption is typically 0.3 nA at 3 V 25°C.
This current doubles every 8°C. The values for higher temperatures are
typically 14 nA at 85°C and typically 600 nA at 125°C.
2.4.4.2
PLL Enable Mode
In the PLL ENABLE MODE the PLL is switched on but the power amplifier is turned off
to avoid undesired power radiation during the time the PLL needs to settle. The settling
time of the PLL is determined mainly by the turn on time of the crystal oscillator and is in
the range of 1 msec depending on the used crystal.
The current consumption is typically 4mA.
Data Sheet
14
V 1.1, 2007-09-18
TDK5111F
Functional Description
2.4.4.3
Transmit Mode
In the TRANSMIT MODE the PLL is switched on and the power amplifier is turned on too.
The current consumption of the IC is typically 14 mA when using a proper transforming
network at PAOUT, see Figure 8.
2.4.4.4
Power mode control
The bias circuitry is powered up via a voltage V > 1.5 V at the pin PDWN (pin10).
When the bias circuitry is powered up, the pins ASKDTA and FSKDTA are pulled up
internally.
Forcing the voltage at the pins low overrides the internally set state.
Alternatively, if the voltage at ASKDTA or FSKDTA is forced high externally, the PDWN
pin is pulled up internally via a current source. In this case, it is not necessary to connect
the PDWN pin, it is recommended to leave it open.
The principle schematic of the power mode control circuitry is shown in Figure 3
PDWN
ASKDTA
OR
FSKDTA
On
Bias
Source
Bias Voltage
120 kΩ
120 kΩ
On
PLL
315
MHz
FSK
PA
FSKOUT
PAOUT
IC
Figure 3
Data Sheet
Power mode control circuitry
15
V 1.1, 2007-09-18
TDK5111F
Functional Description
Table 6 provides a listing of how to get into the different power modes
Table 6
PDWN
1)
Power Modes
FSKDTA
ASKDTA
Low
Low, Open
Low, Open
Open2)
Low
Low
High3)
Low, Open, High
Low
Open
High
Low
High
Low, Open, High
Open, High
Open
High
Open, High
Open
Low, Open, High
High
1) Low:
MODE
POWER DOWN
PLL ENABLE
TRANSMIT
Voltage at pin < 0.7V (PDWN)
Voltage at pin < 0.5V (FSKDTA, ASKDTA)
2) Open:
Pin open
3) High:
Voltage at pin > 1.5V
Other combinations of the control pins PDWN, FSKDTA and ASKDTA are not
recommended.
Data Sheet
16
V 1.1, 2007-09-18
TDK5111F
Functional Description
2.4.5
Recommended Timing Diagrams for ASK- and FSK-Modulation
ASK Modulation using FSKDTA and ASKDTA, PDWN not connected
Modes:
Power Down
PLL Enable
Transmit
High
FSKDTA
Low
to
t
DATA
Open, High
ASKDTA
Low
to
t
min. 1 msec.
Figure 4
ASK Modulation
FSK Modulation using FSKDTA and ASKDTA, PDWN not connected.
Modes:
Power Down
PLL Enable
Transmit
DATA
High
FSKDTA
Low
to
t
to
t
High
ASKDTA
Low
min. 1 msec.
Figure 5
FSK Modulation
In case of FSK Modulation without using PDWN it should be considered, that a too small
value of C2 (referring to Figure 8 and the BOM) could possibly enlarge the start-up time
of the oscillator significantly.
Data Sheet
17
V 1.1, 2007-09-18
TDK5111F
Functional Description
Alternative ASK Modulation, FSKDTA not connected.
Modes:
Power Down
PLL Enable
Transmit
High
PDWN
Low
to
t
DATA
Open, High
ASKDTA
Low
to
t
min. 1 msec.
Figure 6
Alternative ASK Modulation
Alternative FSK Modulation
Modes:
Power Down
PLL Enable
Transmit
High
PDWN
Low
to
t
Open, High
ASKDTA
Low
to
t
DATA
Open, High
FSKDTA
Low
to
t
min. 1 msec.
Figure 7
Data Sheet
Alternative FSK Modulation
18
V 1.1, 2007-09-18
TDK5111F
Applications
3
Applications
3.1
50 Ohm-Output Testboard Schematic
Figure 8
Data Sheet
50 Ohm-output testboard schematic
19
V 1.1, 2007-09-18
TDK5111F
Applications
3.2
50 Ohm-Output Testboard Layout
Figure 9
Top Side of TDK5111 F-Testboard with 50 Ohm-Output
Figure 10
Bottom Side of TDK5111 F-Testboard with 50 Ohm-Output
Data Sheet
20
V 1.1, 2007-09-18
TDK5111F
Applications
3.3
Bill of Material (50 Ohm-Output Evalboard)
Reference
R1
R2
R3
R4
R5
R6
R7
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
L1
L2
X1
X2
X3
X4
X5
X6
X7
JP1
JP2
Q1
IC1
Data Sheet
Value
open
open
4k7
12k
open
15k
open
15p
6p8
open
open
100p
12p
100p
1n
6p8
47n
56n
100n
n.e.
n.e.
Pin
Pin
SMA-connector
SMA-connector
n.e.
solder bridge
solder bridge
9843.75 kHz, CL=12pF
TDK5111F
Specification
0603, +/-5%
0603, +/-5%
0603, +/-5%
0603, C0G, +/-0,1p
0603, C0G, +/-1%
0603, X7R, +/-10%
0603, C0G, +/-1%
0603, C0G, +/-1%
0603, C0G, +/-5%
0603, C0G, +/-0,1p
0603, X7R, +/-10%
EPCOS SIMID 0603-C, +/-2%
EPCOS SIMID 0603-C, +/-2%
single-pole connector, 2,54mm
single-pole connector, 2,54mm
in position "XTAL"
in position "FSK"
Tokyo Denpa TSS-3B 9843.75 kHz Spec.No. 1053-921
21
V 1.1, 2007-09-18
TDK5111F
Applications
3.4
Application Hints on the Crystal Oscillator
Application Hints on the crystal oscillator
The crystal oscillator achieves a turn on time in the range of 1 msec depending on the
used crystal. To achieve this, a NIC oscillator type is implemented in the TDK 5111 F.
The input impedance of this oscillator is a negative resistance in series to an inductance.
Therefore the load capacitance of the crystal CL (specified by the crystal supplier) is
transformed to the capacitance Cv.
-R
L
f, CL
Cv
IC
Figure 11
Application Hints
Formula 1:
Cv =
1
1
+ ω 2L
CL
CL:
crystal load capacitance for nominal frequency
ω:
angular frequency
L:
inductance of the crystal oscillator
Example for the ASK-Mode:
Referring to the application circuit, in ASK-Mode the capacitance C2 is replaced by a
short to ground. Assume a crystal frequency of 9.84 MHz and a crystal load capacitance
of CL = 12 pF. The inductance L at 9.84 MHz is about 4.6 µH. Therefore C1 is calculated
to 10 pF.
Cv =
Data Sheet
1
1
+ω 2L
CL
22
= C1
V 1.1, 2007-09-18
TDK5111F
Applications
Example for the FSK-Mode:
FSK modulation is achieved by switching the load capacitance of the crystal as shown
below.
FSKDTA
FSKOUT
Csw
-R
L
f, CL Cv1
Cv2
COSC
IC
Figure 12
FSK Mode
The frequency deviation of the crystal oscillator is multiplied with the divider factor N of
the Phase Locked Loop to the output of the power amplifier. In case of small frequency
deviations (up to +/- 400 ppm), the two desired load capacitances can be calculated with
the formula below.
CL ± =
2(C 0 + CL )
∆f
(1 +
)
N * f1
C1
∆f
2(C 0 + CL )
1±
(1 +
)
N * f1
C1
CL m C 0
CL:
crystal load capacitance for nominal frequency
C0:
shunt capacitance of the crystal
f:
frequency
ω:
ω = 2πf: angular frequency
N:
division ratio of the PLL
df:
peak frequency deviation
Because of the inductive part of the TDK 5111 F, these values must be corrected by
Formula 1 on the preceding page. The value of Cv± can be calculated.
Data Sheet
23
V 1.1, 2007-09-18
TDK5111F
Applications
Cv ± =
1
1
+ω 2L
CL ±
If the FSK switch is closed, Cv± is equal to Cv1 (C1 in the application diagram). If the
FSK switch is open, Cv2 (C2 in the application diagram) can be calculated.
Cv 2 = C 2 =
Csw:
Csw ∗ Cv1 − (Cv + ) ∗ (Cv1 + Csw )
(Cv + ) − Cv1
parallel capacitance of the FSK switch (3 pF incl. layout parasitics)
Remark: These calculations are only approximations. The necessary values depend
on the layout also and must be adapted for the specific application board.
3.5
Design Hints on the Clock Output (CLKOUT)
The CLKOUT pin is an open collector output. An external pull up resistor (RL) should be
connected between this pin and the positive supply voltage. The value of RL is
depending on the clock frequency and the load capacitance CLD (PCB board plus input
capacitance of the microcontroller). RL can be calculated to:
RL =
Table 7
1
fCLKOUT * 8 * CLD
Clock Output
fCLKOUT=615.2 kHz
Remark:
Data Sheet
CL[pF]
RL[kOhm]
5
39
10
18
20
10
To achieve a low current consumption and a low
spurious radiation, the largest possible RL should be chosen.
24
V 1.1, 2007-09-18
TDK5111F
Applications
Even harmonics of the signal at CLKOUT can interact with the crystal oscillator input
COSC preventing the start-up of oscillation. Care must be taken in layout by sufficient
separation of the signal lines to ensure sufficiently small coupling.
3.6
Application Hints on the Power-Amplifier
The power amplifier operates in a high efficient class C mode. This mode is
characterized by a pulsed operation of the power amplifier transistor at a current flow
angle of θ<<π. A frequency selective network at the amplifier output passes the
fundamental frequency component of the pulse spectrum of the collector current to the
load. The load and its resonance transformation to the collector of the power amplifier
can be generalized by the equivalent circuit of Figure 13. The tank circuit L//C//RL in
parallel to the output impedance of the transistor should be in resonance at the
operating frequency of the transmitter.
VS
L
Figure 13
C
RL
Equivalent power amplifier tank circuit
The optimum load at the collector of the power amplifier for “critical” operation under
idealized conditions at resonance is:
R LC =
V S2
2 * PO
The theoretical value of RLC for an RF output power of Po= 10dBm (10mW) is:
R
LC
=
32
= 450 Ω
2 * 0 . 01
“Critical” operation is characterized by the RF peak voltage swing at the collector of the
PA transistor to just reach the supply voltage VS.
The high degree of efficiency under “critical” operating conditions can be explained by
the low power losses at the transistor. During the conducting phase of the transistor, its
collector voltage is very small. This way the power loss of the transistor, equal to iC*uCE
is minimized. This is particularly true for small current flow angles of θ<<π.
Data Sheet
25
V 1.1, 2007-09-18
TDK5111F
Applications
In practice the RF-saturation voltage of the PA transistor and other parasitics reduce the
“critical” RLC.
The output power Po is reduced by operating in an “overcritical” mode characterised by
RL > RLC.
The power efficiency (and the bandwidth) increase when operating at a slightly higher
RL, as shown in Figure 14.
The collector efficiency E is defined as
E=
PO
VS I C
The diagram of Figure 14 was measured directly at the PA-output at VS = 3 V. Losses in
the matching circuitry decrease the output power by about 1.5 dB. As can be seen from
the diagram, 250 Ω is the optimum impedance for operation at 3 V. For an approximation
of ROPT and POUT at other supply voltages those two formulas can be used:
ROPT ~ VS
and
POUT ~ ROPT
18
16
14
12
10
Pout [mW]
10*Ec
8
6
4
2
0
0
100
200
300
400
500
RL [Ohm]
Figure 14
Output power Po (mW) and collector efficiency E vs. load resistor RL.
The DC collector current Ic of the power amplifier and the RF output power Po vary with
the load resistor RL. This is typical for overcritical operation of class C amplifiers. The
collector current will show a characteristic dip at the resonance frequency for this type of
“overcritical” operation. The depth of this dip will increase with higher values of RL.
Data Sheet
26
V 1.1, 2007-09-18
TDK5111F
Reference
4
Reference
4.1
Electrical Data
4.1.1
Absolute Maximum Ratings
Attention: The maximum ratings must not be exceeded under any circumstances,
not even momentarily and individually, as permanent damage to the IC
will result.
Table 8
Absolute Maximum Ratings, Tamb = -40 °C … +125 °C
Parameter
Symbol
Limit Values
Unit
Remarks
min.
max.
Junction Temperature
TJ
−40
+150
°C
Storage Temperature
Ts
−40
+125
°C
Thermal Resistance
RthJA
220
K/W
Supply voltage
VS
−0.3
+4.0
V
Voltage at any pin
excluding pin 9
Vpins
-0.3
VS + 0.3
V
Voltage at pin 9
Vpin9
-0.3
2 * VS
V
No ESD-Diode to VS
ESD integrity, all pins
VESD
-1
+1
kV
JEDEC Standard
JESD22-A114-B
ESD integrity, all pins
excluding pin 9
VESD
-2.5
+2.5
kV
JEDEC Standard
JESD22-A114-B
Ambient Temperature under bias: TA = −40°C to +125°C
Note: All voltages referred to ground (pins) unless stated otherwise.
Pins 3 and 8 are grounded.
Data Sheet
27
V 1.1, 2007-09-18
TDK5111F
Reference
4.2
Operating Ratings
Within the operational range the IC operates as described in the circuit description.
Table 9
Operating Ratings
Parameter
Symbol
Limit Values
min.
max.
Unit
Supply voltage
VS
2.1
4.0
V
Ambient temperature
TA
-40
125
°C
4.3
Test Conditions
AC/DC Characteristics
AC/DC characteristics involve the spread of values guaranteed within the specified
supply voltage and ambient temperature. Typical charcateristics are the median of the
production.
4.3.1
AC/DC Characteristic at 3V, 25°C
Table 10
Supply Voltage VS=3V, Ambient temperature Tamb=25°C
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit Test
Conditions
Current consumption
Power Down mode
IS PDWN
0.3
100
nA
PLL Enable mode
IS PLL_EN
4
5.5
mA
Transmit mode
315 MHz
IS TRANSM
14
17.5
mA
315
325
MHz fOUT = 32 * fCOSC
V (Pins 10, 6
and 7)
< 0.2 V
Output frequency
Output frequency
fOUT
305
Clock Driver Output (Pin 1)
Output current (High)
ICLKOUT
5
µA
VCLKOUT = VS
Saturation Voltage
(Low)1)
VSATL
0.56
V
ICLKOUT = 1 mA
Data Sheet
28
V 1.1, 2007-09-18
TDK5111F
Reference
Table 10
Supply Voltage VS=3V, Ambient temperature Tamb=25°C (cont’d)
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit Test
Conditions
FSK Switch Output (Pin 4)
On resistance
RFSKOUT
250
Ω
VFSKDTA = 0 V
On capacitance
CFSKOUT
6
pF
VFSKDTA = 0 V
Off resistance
RFSKOUT 10
kΩ
VFSKDTA = VS
Off capacitance
CFSKOUT
1.5
pF
VFSKDTA = VS
5
pF
100
Ω
f = 9.84 MHz
µH
f = 9.84 MHz
Crystal Oscillator Input (Pin 5)
Capacitive load
CCOSCmax
Serial Resistance of
the crystal
Input inductance of the
COSC pin
4.6
ASK Modulation Data Input (Pin 6)
ASK Transmit disabled VASKDTA 0
0.5
ASK Transmit enabled VASKDTA 1.5
VS
V
Input bias current
ASKDTA
IASKDTA
30
µA
VASKDTA = VS
Input bias current
ASKDTA
IASKDTA
µA
VASKDTA = 0 V
ASK data rate
fASKDTA
-20
V
20
kHz
VFSKDTA 0
0.5
V
FSK Switch off
VFSKDTA 1.5
VS
V
Input bias current
FSKDTA
IFSKDTA
30
µA
VFSKDTA = VS
Input bias current
FSKDTA
IFSKDTA
µA
VFSKDTA = 0 V
FSK data rate
fFSKDTA
FSK Modulation Data Input (Pin 7)
FSK Switch on
-20
20
kHz
13.2
dBm
Power Amplifier Output (Pin 9)
Output Power2) at
315 MHz transformed
to 50 Ohm
Data Sheet
POUT315
7.2
10.2
29
V 1.1, 2007-09-18
TDK5111F
Reference
Table 10
Supply Voltage VS=3V, Ambient temperature Tamb=25°C (cont’d)
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit Test
Conditions
Power Down Mode Control (Pin 10)
Power Down mode
V PDWN
0
0.7
V
VASKDTA < 0.2 V
VFSKDTA < 0.2 V
PLL Enable mode
V PDWN
1.5
VS
V
VASKDTA < 0.5 V
Transmit mode
V PDWN
1.5
VS
V
VASKDTA > 1.5 V
Input bias current
PDWN
IPDWN
30
µA
VPDWN = VS
1) Derating linearly to a saturation voltage of max. 140 mV at ICLKOUT = 0 mA
2) Power amplifier in overcritical C-operation
Matching circuitry as used in the 50 Ohm-Output Testboard at the specified frequency.
Tolerances of the passive elements not taken into account.
4.3.2
AC/DC Characteristic at 2.1V ...4.0 V, -40°C ...+125°C
Table 11
Supply Voltage VS=2.1V ... 4.0V, Tamb=-40°C ... +125°C
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit Test
Conditions
4
µA
Current consumption
Power Down mode
IS PDWN
V (Pins 10, 6
and 7) < 0.2 V
PLL Enable mode
IS PLL_EN
4
6
mA
Transmit mode
IS TRANSM
10.6
15.5
mA
@ 2.1 V
14
18
mA
@3V
16.2
21
mA
@4V
315
317
MHz fOUT = 32 * fCOSC
Output frequency
Output frequency1)
fOUT
311
Clock Driver Output (Pin 1)
Output current (High)
ICLKOUT
5
µA
VCLKOUT = VS
Saturation Voltage
(Low)2)
VSATL
0.5
V
ICLKOUT = 0.6
mA
Data Sheet
30
V 1.1, 2007-09-18
TDK5111F
Reference
Table 11
Supply Voltage VS=2.1V ... 4.0V, Tamb=-40°C ... +125°C (cont’d)
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit Test
Conditions
FSK Switch Output (Pin 4)
On resistance
RFSKOUT
280
Ω
VFSKDTA = 0 V
On capacitance
CFSKOUT
6
pF
VFSKDTA = 0 V
Off resistance
RFSKOUT 10
kΩ
VFSKDTA = VS
Off capacitance
CFSKOUT
1.5
pF
VFSKDTA = VS
5
pF
100
Ω
f = 9.84 MHz
µH
f = 9.84 MHz
Crystal Oscillator Input (Pin 5)
Capacitive Load
CCOSCmax
Serial Resistance of
the crystal
Input inductance of the
COSC pin
4.6
ASK Modulation Data Input (Pin 6)
ASK Transmit disabled VASKDTA 0
0.5
ASK Transmit enabled VASKDTA 1.5
VS
V
Input bias current
ASKDTA
IASKDTA
33
µA
VASKDTA = VS
Input bias current
ASKDTA
IASKDTA
µA
VASKDTA = 0 V
ASK data rate
fASKDTA
-20
V
20
kHz
VFSKDTA 0
0.5
V
FSK Switch off
VFSKDTA 1.5
VS
V
Input bias current
FSKDTA
IFSKDTA
33
µA
VFSKDTA = VS
Input bias current
FSKDTA
IFSKDTA
µA
VFSKDTA = 0 V
FSK data rate
fFSKDTA
FSK Modulation Data Input (Pin 7)
FSK Switch on
Data Sheet
-20
20
31
kHz
V 1.1, 2007-09-18
TDK5111F
Reference
Table 11
Supply Voltage VS=2.1V ... 4.0V, Tamb=-40°C ... +125°C (cont’d)
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit Test
Conditions
Power Amplifier Output (Pin 9)
Output Power 3) at
315 MHz
transformed to
50 Ohm.
POUT, 315 4.5
7
10
dBm VS = 2.1 V
POUT, 315 6.5
10.2
13.5
dBm VS = 3.0 V
POUT, 315 7.5
12.5
17
dBm VS = 4.0 V
Power Down Mode Control (Pin 10)
Power Down mode
V PDWN
0
0.5
V
VASKDTA < 0.2 V
VFSKDTA < 0.2 V
PLL Enable mode
V PDWN
1.5
VS
V
VASKDTA < 0.5 V
Transmit mode
V PDWN
1.5
VS
V
VASKDTA > 1.5 V
Input bias current
PDWN
IPDWN
38
µA
VPDWN = VS
1) a) When the minimum TA is increased by 10°C, the minimum fOUT decreases by 1 MHz.
b) When the maximum TA is decreased by 10°C, the maximum fOUT increases by 1 MHz.
c) When the minimum VS is increased by 60 mV, the maximum fOUT increases by 1 MHz.
Restriction of c): The maximum fOUT must not be increased by more than 19 MHz
by increasing VS.
All three measures can be taken independently and additive.
2) Derating linearly to a saturation voltage of max. 140 mV at ICLKOUT = 0 mA
3) Matching circuitry as used in the 50 Ohm-Output Testboard.
Tolerances of the passive elements not taken into account.
Range @ 2.1 V, +25°C: 7 dBm +/- 2 dBm
Typ. temperature dependency at 2.1 V: +0.05 dBm@-40°C and -0.3 dBm@+125°C, reference +25°C
Range @ 3.0 V, +25°C: 10.2 dBm +/- 3 dBm
Typ. temperature dependency at 3.0 V: +0.1 dBm@-40°C and -0.5 dBm@+125°C, reference +25°C
Range @ 4.0 V, +25°C: 12.5 dBm +/- 4.5 dBm
Typ. temperature dependency at 4.0 V: + 0 dBm@-40°C and -0.5 dBm@+125°C, reference +25°C
Data Sheet
32
V 1.1, 2007-09-18
TDK5111F
Package Outlines
0.5
0.1 A
A
0.22 ±0.05
0.08
M
C
0.42 +0.15
-0.1
ABC
4.9
3 ±0.1
6 max.
+0.08
0.125 -0.05
3 ±0.1
H
0.09
0.85 ±0.1
1.1 max.
Package Outlines
0.15 max.
5
0.25
M
ABC
B
Index Marking
Figure 15
PG-TSSOP-10
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
Dimensions in mm
SMD = Surface Mounted Device
Data Sheet
33
V 1.1, 2007-09-18
TDK5111F
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Data Sheet
Page
Order information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Definition and Functions - Overview . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Definition and Function1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
FSKDTA - FSK Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
ASKDTA - Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Absolute Maximum Ratings, Tamb = -40 °C … +125 °C . . . . . . . . . . . . 27
Operating Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Supply Voltage VS=3V, Ambient temperature Tamb=25°C . . . . . . . . . . 28
Supply Voltage VS=2.1V ... 4.0V, Tamb=-40°C ... +125°C. . . . . . . . . . . 30
34
V 1.1, 2007-09-18
TDK5111F
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Data Sheet
Page
IC Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Power mode control circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
ASK Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
FSK Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Alternative ASK Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Alternative FSK Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
50 Ohm-output testboard schematic . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Top Side of TDK5111 F-Testboard with 50 Ohm-Output. . . . . . . . . . . 20
Bottom Side of TDK5111 F-Testboard with 50 Ohm-Output . . . . . . . . 20
Application Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
FSK Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Equivalent power amplifier tank circuit. . . . . . . . . . . . . . . . . . . . . . . . . 25
Output power Po (mW) and collector efficiency E vs. load resistor RL. 26
PG-TSSOP-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
35
V 1.1, 2007-09-18
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG