INTEGRATED CIRCUITS DATA SHEET TDA8766 10-bit high-speed 2.7 to 5.25 V analog-to-digital converter Product specification Supersedes data of 1995 Mar 22 File under Integrated Circuits, IC02 1996 Mar 20 Philips Semiconductors Product specification 10-bit high-speed 2.7 to 5.25 V analog-to-digital converter TDA8766 FEATURES APPLICATIONS • 10-bit resolution High-speed analog-to-digital conversion for: • 2.7 to 5.25 V operation • Video data digitizing • Sampling rate up to 20 MHz • Camera • DC sampling allowed • Camcorder • High signal-to-noise ratio over a large analog input frequency range (9.3 effective bits at 1.0 MHz full-scale input at fclk = 20 MHz) • Radio communication. GENERAL DESCRIPTION • In range (IR) CMOS output The TDA8766 is a 10-bit high-speed analog-to-digital converter (ADC) for professional video and other applications. It converts with 2.7 to 5.25 V operation the analog input signal into 10-bit binary-coded digital words at a maximum sampling rate of 20 MHz. All digital inputs and outputs are CMOS compatible. A standby mode allows reduction of the device power consumption down to 4 mW. • CMOS/TTL compatible digital inputs and outputs • External reference voltage regulator • Power dissipation only 53 mW (typical) • Low analog input capacitance, no buffer amplifier required • Standby mode • No sample-and-hold circuit required. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDDA analog supply voltage 2.7 3.3 5.25 V VDDD1 digital supply voltage 1 2.7 3.3 5.25 V VDDD2 digital supply voltage 2 2.7 3.3 5.25 V VDDO output stages supply voltage 2.5 3.3 5.25 V IDDA analog supply current − 7.5 10 mA IDDD digital supply current − 7.5 10 mA IDDO output stages supply current fclk = 20 MHz; CL = 20 pF; ramp input − 1 2 mA INL integral non-linearity fclk = 20 MHz; ramp input − ±1 ±2 LSB DNL differential non-linearity fclk = 20 MHz; ramp input − ±0.25 ±0.7 LSB fclk(max) maximum clock frequency 20 − − MHz Ptot total power dissipation − 53 73 mW VDDA = VDDD = VDDO = 3.3 V ORDERING INFORMATION TYPE NUMBER TDA8766G 1996 Mar 20 PACKAGE NAME DESCRIPTION VERSION LQFP32 plastic low profile quad flat package; 32 leads; body 5 × 5 × 1.4 mm SOT401-1 2 Philips Semiconductors Product specification 10-bit high-speed 2.7 to 5.25 V analog-to-digital converter TDA8766 BLOCK DIAGRAM handbook, full pagewidth V DDA CLK VDDD2 OE 7 5 18 16 6 CLOCK DRIVER STDBY TDA8766 V RT 15 1 D9 31 D8 MSB 30 D7 RLAD analog voltage input VI 29 D6 28 D5 14 ANALOG -TO - DIGITAL CONVERTER CMOS OUTPUTS LATCHES 27 D4 data outputs 26 D3 V RM 11 25 D2 23 D1 22 D0 20 VRB 10 CMOS OUTPUT IN RANGE LATCH 2 4 9 VSSA analog ground 19 VSSD2 21 VSSO digital ground 2 output ground Fig.1 Block diagram. 1996 Mar 20 3 3 VSSD1 digital ground 1 MLC853 LSB VDDO IR output VDDD1 Philips Semiconductors Product specification 10-bit high-speed 2.7 to 5.25 V analog-to-digital converter TDA8766 PINNING SYMBOL PIN DESCRIPTION SYMBOL PIN DESCRIPTION D9 1 data output; bit 9 (MSB) VDDD2 18 digital supply voltage 2 (2.7 to 5.25 V) IR 2 in range data output VSSD2 19 digital ground 2 VSSD1 3 digital ground 1 VDDO 20 VDDD1 4 digital supply voltage 1 (2.7 to 5.25 V) positive supply voltage for output stage (2.5 to 5.25 V) CLK 5 clock input VSSO 21 digital output ground 22 data output; bit 0 (LSB) STDBY 6 standby mode input D0 VDDA 7 analog supply voltage (2.7 to 5.25 V) D1 23 data output; bit 1 n.c. 8 not connected n.c. 24 not connected VSSA 9 analog ground D2 25 data output; bit 2 26 data output; bit 3 VRB 10 reference voltage BOTTOM input D3 VRM 11 reference voltage MIDDLE D4 27 data output; bit 4 n.c. 12 not connected D5 28 data output; bit 5 29 data output; bit 6 30 data output; bit 7 VRT 15 reference voltage TOP input D8 31 data output; bit 8 n.c. 32 not connected OE 16 output enable input n.c. 17 not connected 32 n.c. handbook, full pagewidth index corner D9 1 24 n.c. IR 2 23 D1 VSSD1 3 22 D0 VDDD1 4 CLK 5 20 VDDO STDBY 6 19 VSSD2 VDDA 7 18 VDDD2 n.c. 8 17 n.c. 21 VSSO 4 OE 16 VRT 15 VI 14 n.c. 13 n.c. 12 VRM 11 VRB 10 VSSA 9 TDA8766 Fig.2 Pin configuration. 1996 Mar 20 25 D2 D7 26 D3 analog input voltage 27 D4 14 28 D5 VI 29 D6 not connected 30 D7 13 31 D8 n.c. D6 MLC854 Philips Semiconductors Product specification 10-bit high-speed 2.7 to 5.25 V analog-to-digital converter TDA8766 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDDA analog supply voltage note 1 −0.3 +7.0 V VDDD1, VDDD2 digital supply voltages note 1 −0.3 +7.0 V VDDO output stages supply voltage note 1 −0.3 +7.0 V ∆VDD supply voltage difference VDDA − VDDD −1.0 +4.0 V VDDD − VDDO −1.0 +4.0 V −1.0 +4.0 V VI input voltage VDDA − VDDO referenced to VSSA −0.3 +7.0 V Vclk(p-p) AC input voltage for switching (peak-to-peak value) referenced to VSSD − VDDD V IO output current − 10 mA Tstg storage temperature −55 +150 °C Tamb operating ambient temperature −20 +75 °C Tj junction temperature − +150 °C Note 1. The supply voltages VDDA, VDDD and VDDO may have any value between −0.3 V and +7.0 V provided that the supply voltage differences ∆VDD are respected. HANDLING Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. THERMAL CHARACTERISTICS SYMBOL Rth j-a 1996 Mar 20 PARAMETER thermal resistance from junction to ambient in free air 5 VALUE UNIT 90 K/W Philips Semiconductors Product specification 10-bit high-speed 2.7 to 5.25 V analog-to-digital converter TDA8766 CHARACTERISTICS VDDA = V7 to V9 = 3.3 V; VDDD = V4 to V3 = V18 to V19 = 3.3 V; VDDO = V20 to V21 = 3.3 V; VSSA, VSSD and VSSO short-circuited together; Vi(p-p) = 1.83 V; CL = 20 pF; Tamb = 0 to +70 °C; typical values measured at Tamb = 25 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply VDDA analog supply voltage 2.7 3.3 5.25 V VDDD1 digital supply voltage 1 2.7 3.3 5.25 V VDDD2 digital supply voltage 2 2.7 3.3 5.25 V VDDO output stages supply voltage 2.5 3.3 5.25 V ∆VDD voltage difference VDDA − VDDD −0.2 − +0.2 V VDDA − VDDO −0.2 − +3.0 V VDDD − VDDO −0.2 − +3.0 V IDDA analog supply current − 7.5 10 mA IDDD digital supply current − 7.5 10 mA IDDO output stages supply current − 1 2 mA fclk = 20 MHz; ramp input; CL = 20 pF Inputs CLOCK INPUT CLK (REFERENCED TO VSSD); see note 1 VIL LOW level input voltage 0 − 0.3VDDD V VIH HIGH level input voltage 0.7VDDD − VDDD V VDDD ≤ 3.6 V 0.6VDDD − VDDD V IIL LOW level input current Vclk = 0.3VDDD −1 0 +1 µA IIH HIGH level input current Vclk = 0.7VDDD − − 5 µA ZI input impedance fclk = 20 MHz − 4 − kΩ CI input capacitance fclk = 20 MHz − 3 − pF 0 − 0.3VDDD V INPUTS OE AND STDBY (REFERENCED TO VSSD); see Table 3 VIL LOW level input voltage VIH HIGH level input voltage 0.7VDDD − VDDD V VDDD ≤ 3.6 V 0.6VDDD − VDDD V IIL LOW level input current VIL = 0.3VDDD −1 − − µA IIH HIGH level input current VIH = 0.7VDDD − − +1 µA VI (ANALOG INPUT VOLTAGE REFERENCED TO VSSA) IIL LOW level input current VI = VRB − 0 − µA IIH HIGH level input current VI = VRT − 35 − µA ZI input impedance fi = 1 MHz − 5 − kΩ CI input capacitance fi = 1 MHz − 8 − pF 1996 Mar 20 6 Philips Semiconductors Product specification 10-bit high-speed 2.7 to 5.25 V analog-to-digital converter SYMBOL TDA8766 PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Reference voltages for the resistor ladder; see Table 1 1.1 1.2 − V 2.7 3.3 VDDA V differential reference voltage VRT − VRB 1.5 2.1 2.7 V Iref reference current − 7.2 − mA RLAD resistor ladder − 290 − Ω TCRLAD temperature coefficient of the resistor ladder − 1860 − ppm − 539 − mΩ/K VosB offset voltage BOTTOM note 2 − 135 − mV VosT offset voltage TOP note 2 − 135 − mV Vi(p-p) analog input voltage (peak-to-peak value) note 3 1.4 1.83 2.4 V − VRB reference voltage BOTTOM VRT reference voltage TOP Vdiff VTOP ≤ VDDA Outputs DIGITAL OUTPUTS D9 TO D0 AND IR (REFERENCED TO VSSD) VOL LOW level output voltage IO = 1 mA 0 0.5 V VOH HIGH level output voltage IO = −1 mA VDDO − 0.5 − VDDO V IOZ output current in 3-state mode 0.5 V < VO < VDDO −20 − +20 µA Switching characteristics CLOCK INPUT CLK; see Fig.4; note 1 fclk(max) maximum clock frequency 20 − − MHz tCPH clock pulse width HIGH 15 − − ns tCPL clock pulse width LOW 15 − − ns Analog signal processing LINEARITY INL integral non-linearity fclk = 20 MHz; ramp input; (see Fig.6) − ±1 ±2 LSB DNL differential non-linearity fclk = 20 MHz; ramp input; (see Fig.7) − ±0.25 ±0.7 LSB INPUT SET RESPONSE (fclk = 20 MHz; see Fig.8; note 4) tSTLH analog input settling time LOW-to-HIGH full-scale square wave − 4 6 ns tSTHL analog input settling time HIGH-to-LOW full-scale square wave − 4 6 ns fi = 1 MHz − −63 − dB without harmonics; fclk = 20 MHz; fi = 1 MHz − 60 − dB HARMONICS; (fclk = 20 MHZ; see Fig.9; note 5) THD total harmonic distortion SIGNAL-TO-NOISE RATIO; see Fig.9; note 5 S/N 1996 Mar 20 signal-to-noise ratio (full scale) 7 Philips Semiconductors Product specification 10-bit high-speed 2.7 to 5.25 V analog-to-digital converter SYMBOL TDA8766 PARAMETER CONDITIONS MIN. TYP. MAX. UNIT EFFECTIVE BITS; see Fig.9; note 5 EB effective bits fclk = 20 MHz fi = 300 kHz − 9.5 − bits fi = 1 MHz − 9.3 − bits fi = 3.58 MHz − 8.0 − bits Timing (fclk = 20 MHz; CL = 20 pF); see Fig.4; note 6 tds sampling delay time − − 5 ns th output hold time 5 − − ns td output delay time VDDO = 4.75 V 8 12 15 ns VDDO = 3.15 V 8 17 20 ns VDDO = 2.7 V 8 21 24 ns 3-state output delay times; see Fig.5 tdZH enable HIGH − 14 18 ns tdZL enable LOW − 16 20 ns tdHZ disable HIGH − 16 20 ns tdLZ disable LOW − 14 18 ns Standby mode output delay times tdSTBLH standby (LOW-to-HIGH transition) − − 200 ns tdSTBHL start-up (HIGH-to-LOW transition) − − 500 ns Notes 1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less than 1 ns. 2. Analog input voltages producing code 0 up to and including 1023: a) VosB (voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00 and the reference voltage BOTTOM (VRB) at Tamb = 25 °C. b) VosT (voltage offset TOP) is the difference between VRT (reference voltage TOP) and the analog input which produces data outputs equal to 1023 at Tamb = 25 °C. 3. In order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities of the converter reference resistor ladder (corresponding to output codes 0 and 1023 respectively) are connected to pins VRB and VRT via offset resistors ROB and ROT as shown in Fig.3. V RT – V RB a) The current flowing into the resistor ladder is IL = ------------------------------------------ and the full-scale input range at the converter, R OB + R L + R OT RL to cover code 0 to code 1023, is V I = R L × I L = ------------------------------------------ × ( V RT – V RB ) = 0.871 × ( V RT – V RB ) R OB + R L + R OT b) Since RL, ROB and ROT have similar behaviour with respect to process and temperature variation, the ratio RL ----------------------------------------- will be kept reasonably constant from part to part. Consequently variation of the output codes R OB + R L + R OT at a given input voltage depends mainly on the difference VRT − VRB and its variation with temperature and supply voltage. When several ADCs are connected in parallel and fed with the same reference source, the matching between each of them is then optimized. 1996 Mar 20 8 Philips Semiconductors Product specification 10-bit high-speed 2.7 to 5.25 V analog-to-digital converter TDA8766 4. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale input (square-wave signal) in order to sample the signal and obtain correct output data. 5. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8K acquisition points per equivalent fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency (NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB × 6.02 + 1.76 dB. 6. Output data acquisition: the output data is available after the maximum delay time of td. handbook, halfpage VRT ROT code 1023 RL VRM RLAD IL code 0 ROB VRB MGD281 Fig.3 Explanation of note 3. 1996 Mar 20 9 Philips Semiconductors Product specification 10-bit high-speed 2.7 to 5.25 V analog-to-digital converter Table 1 TDA8766 Output coding and input voltage (typical values; referenced to VSSA) BINARY OUTPUT BITS VI(p-p) (V) IR Underflow <1.335 0 STEP D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 1.335 1 0 0 0 0 0 0 0 0 0 0 1 . 1 0 0 0 0 0 0 0 0 0 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 1022 . 1 1 1 1 1 1 1 1 1 1 0 1023 3.165 1 1 1 1 1 1 1 1 1 1 1 Overflow >3.165 0 1 1 1 1 1 1 1 1 1 1 Table 2 Mode selection OE Table 3 D9 TO D0 IR 1 high impedance high impedance 0 active; binary active Standby selection STDBY IDDA + IDDD (typ.) D9 TO D0 1 last logic state 1.2 mA 0 active 15 mA t CPL handbook, full pagewidth t CPH 50% CLK sample N sample N + 1 sample N + 2 Vl t ds DATA D0 to D9 th VDDO DATA N-2 DATA N-1 DATA N DATA N+1 50% 0V td Fig.4 Timing diagram. 1996 Mar 20 10 MGD346 Philips Semiconductors Product specification 10-bit high-speed 2.7 to 5.25 V analog-to-digital converter handbook, full pagewidth TDA8766 V DDD 50 % OE t dHZ t dZH HIGH 90 % output data 50 % t dLZ LOW t dZL HIGH output data 50 % LOW 10 % V DDD 3.3 kΩ S1 TDA8766 20 pF TEST S1 t dLZ t dZL VDDD VDDD t dHZ GND t dZH GND OE MLC855 fOE = 100 kHz. Fig.5 Timing diagram and test conditions of 3-state output delay time. 1996 Mar 20 11 Philips Semiconductors Product specification 10-bit high-speed 2.7 to 5.25 V analog-to-digital converter TDA8766 MLD115 0.6 handbook, full pagewidth A (LSB) 0.4 0.2 0 −0.2 −0.4 −0.6 0 200 400 600 800 1000 f (codes) 1100 1023 Fig.6 Typical integral non-linearity (INL) performance. MLD116 0.25 handbook, full pagewidth A (LSB) 0.15 0.05 −0.05 −0.15 −0.25 0 200 400 600 800 1000 f (codes) Fig.7 Typical differential non-linearity (DNL) performance. 1996 Mar 20 12 1023 1100 Philips Semiconductors Product specification 10-bit high-speed 2.7 to 5.25 V analog-to-digital converter TDA8766 t STHL t STLH handbook, full pagewidth code 1023 VI 50 % 50 % code 0 5 ns 5 ns CLK 50 % 50 % 2 ns MBD875 2 ns Fig.8 Analog input settling-time diagram. MLD117 0 handbook, full pagewidth A (dB) 20 40 60 80 100 120 0 1.25 2.5 3.76 5.01 6.26 7.51 8.76 10 f (MHz) Effective bits: 9.59; THD = −76.60 dB. Harmonic levels (dB): 2nd = −81.85; 3rd = −87.56; 4th = −88.81; 5th = −88.96; 6th = −79.58. Fig.9 Typical Fast Fourier Transform (fclk = 20 MHz; fi = 1 MHz). 1996 Mar 20 13 Philips Semiconductors Product specification 10-bit high-speed 2.7 to 5.25 V analog-to-digital converter TDA8766 INTERNAL PIN CONFIGURATIONS handbook, halfpage handbook, halfpage V DDO V DDA D9 to D0 IR VI V SSO VSSA MLC856 MLC857 Fig.10 CMOS data and In Range (IR) outputs. Fig.11 Analog inputs. handbook, halfpage handbook, halfpage VDDA V DDO VRT VRM OE (STDBY) VRB VSSA V SSO MLC859 MLC858 Fig.12 OE (STDBY) input. 1996 Mar 20 R LAD Fig.13 VRB, VRM and VRT. 14 Philips Semiconductors Product specification 10-bit high-speed 2.7 to 5.25 V analog-to-digital converter TDA8766 V DDD handbook, halfpage 1/2V CLK DDD VSSD MLC860 Fig.14 CLK input. 1996 Mar 20 15 Philips Semiconductors Product specification 10-bit high-speed 2.7 to 5.25 V analog-to-digital converter TDA8766 APPLICATION INFORMATION Additional application information will be supplied upon request (please quote number “AN96012”). handbook, full pagewidth (2) n.c. 32 D9 IR V SSD1 VDDD1 CLK STDBY VDDA D8 31 D7 30 D6 29 D5 D4 28 27 D3 26 D2 25 (2) 1 24 2 23 3 22 4 21 TDA8766 5 20 6 19 7 18 8 17 (2) n.c. n.c. D1 D0 VSSO VDDO VSSD2 VDDD2 (2) 9 10 VSSA 100 nF 11 12 13 VRB(1) VRM (1) n.c.(2) (3) VSSA 14 (2) n.c. 15 VI (4) VRT n.c. 16 (1) OE MLC861 100 nF VSSA 100 nF VSSA The analog and digital supplies should be separated and decoupled. The external voltage reference generator must be built such that a good supply voltage ripple rejection is achieved with respect to the LSB value. Eventually, the reference ladder voltages can be derived from a well regulated VDDA supply through a resistor bridge and a decoupled capacitor. (1) VRB, VRM and VRT are decoupled to VSSA. (2) Pins 8, 12, 13, 17, 24 and 32 should be connected to the closest ground pin in order to prevent noise influence. (3) When VRM is not used, pin 11 can be left open, avoiding the decoupling capacitor. In any case, pin 11 must not be grounded. (4) When analog input signal is AC coupled, an input bias or a clamping level must be applied to VI input (pin 14). Fig.15 Application diagram. 1996 Mar 20 16 Philips Semiconductors Product specification 10-bit high-speed 2.7 to 5.25 V analog-to-digital converter TDA8766 PACKAGE OUTLINE SOT401-1 LQFP32: plastic low profile quad flat package; 32 leads; body 5 x 5 x 1.4 mm c y X A 17 24 ZE 16 25 e A A2 E HE (A 3) A1 w M pin 1 index θ bp 32 Lp 9 L 1 8 detail X ZD e v M A w M bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 1.60 0.15 0.05 1.5 1.3 0.25 0.27 0.17 0.18 0.12 5.1 4.9 5.1 4.9 0.5 7.15 6.85 7.15 6.85 1.0 0.75 0.45 0.2 0.12 0.1 Z D (1) Z E (1) θ 0.95 0.55 7 0o 0.95 0.55 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 95-12-19 97-08-04 SOT401-1 1996 Mar 20 EUROPEAN PROJECTION 17 Philips Semiconductors Product specification 10-bit high-speed 2.7 to 5.25 V analog-to-digital converter TDA8766 If wave soldering cannot be avoided, the following conditions must be observed: SOLDERING Introduction • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. • The footprint must be at an angle of 45° to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering LQFP packages LQFP48 (SOT313-2), LQFP64 (SOT314-2) or LQFP80 (SOT315-1). This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Reflow soldering Reflow soldering techniques are suitable for all LQFP packages. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. Wave soldering Wave soldering is not recommended for LQFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. 1996 Mar 20 18 Philips Semiconductors Product specification 10-bit high-speed 2.7 to 5.25 V analog-to-digital converter TDA8766 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1996 Mar 20 19 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. (02) 805 4455, Fax. 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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 537021/1100/02/pp20 Document order number: Date of release: 1996 Mar 20 9397 750 00746