INTEGRATED CIRCUITS DATA SHEET TDA8758 YC 8-bit low-power analog-to-digital video interface Product specification Supersedes data of 1995 Mar 22 File under Integrated Circuits, IC02 1996 Feb 01 Philips Semiconductors Product specification YC 8-bit low-power analog-to-digital video interface TDA8758 FEATURES APPLICATIONS • Two 8-bit ADCs: • Video signal decoding – one Luminance or CVBS channel • Digital picture processing – one Chrominance channel • Frame grabbing • Multimedia with the Philips Desktop Video chip set (and especially SAA7196 multistandard decoder and scaler). • Sampling rate up to 32 MHz • Binary or two's complement 3-state TTL outputs for each channel • Internal reference voltage regulator GENERAL DESCRIPTION • TTL-compatible digital inputs and outputs The TDA8758 is an 8-bit video high-speed low-power analog-to-digital conversion (ADC) interface for YC and CVBS signal processing. It converts 1-of-3 CVBS input signals or 1-of-2 YC input signals into binary or two’s complement words at a sampling rate of 32 MHz. All analog signal inputs are digitally clamped and an ADC interface is provided on the Y/CVBS channel. A fast precharge on clamp and AGC is provided for start-up. All digital inputs and outputs are TTL compatible. • Power dissipation of 530 mW (typical) • Input selector circuit (five selectable video inputs for CVBS or YC processing) • Peak white enable input • Clamp and Automatic Gain Control (AGC) functions for Y/CVBS channel (clamping on code 64 and Peak White level control at code 255) • Clamp function for C channel (code 128) • No sample-and-hold circuit required. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VCCA analog supply voltage 4.75 5.0 5.25 V VCCD digital supply voltage 4.75 5.0 5.25 V VCCO output stages supply voltage 4.75 5.0 5.25 V ICCA analog supply current − 59 70 mA ICCD digital supply current − 28 40 mA ICCO output supply current − 19 28 mA ILE DC integral linearity error − ±0.75 ±1.5 LSB DLE DC differential linearity error EB effective bits (from video input to digital outputs) fclk(max) maximum clock frequency B maximum −3 dB bandwidth (input preamplifier) αct Ptot CL = 15 pF − ±0.4 ±1.0 LSB − 7.1 − bits 30 32 − MHz − 15 − MHz crosstalk between Y and C channels and each video input − −63 −55 dB total power dissipation − 530 724 mW fclk = 32 MHz; fi = 4.43 MHz full-scale; 0 dB gain ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA8758G LQFP48 1996 Feb 01 DESCRIPTION plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm 2 VERSION SOT313-2 Philips Semiconductors Product specification YC 8-bit low-power analog-to-digital video interface TDA8758 BLOCK DIAGRAM V CCA handbook, full pagewidth VCCD SEL2 VCCA 5 CHROM2 CHROM1 VCCO2 V CCO1 10 21 2 DEC2 REG1 REG2 SDN DEC3 DEC1 ANOUTC CCLPC 41 32 48 45 8 44 CLAMP LEVEL 128 17 1 ADC 46 15 TTL 33 to 40 4 COMPARATOR CVBS3 6 42 TIMING GENERATOR Y2/CVBS2 Y1/CVBS1 9 AGC & CLAMP 64 11 12 SEL1 14 PWE 19 GATE A ADC 20 7 13 16 TTL 43 18 8 3 Y7 to Y0 3 DGND OGND2 ANOUTY OGND1 AGND Fig.1 Block diagram. OFY 23 to 30 CAGC C CLPY GATE B 1996 Feb 01 31 CLK 22 COMPARATORS C7 to C0 OFC 47 TDA8758 INPUT SELECTOR 8 MGB469 - 1 Philips Semiconductors Product specification YC 8-bit low-power analog-to-digital video interface TDA8758 PINNING SYMBOL PIN DESCRIPTION DEC1 1 decoupling input 1 CHROM2 2 chrominance analog voltage input 2 AGND 3 analog ground CHROM1 4 chrominance analog voltage input 1 SEL2 5 selection control input 2 CVBS3 6 luminance analog voltage input 3 CCLPY 7 Y channel clamping capacitor SDN 8 stabilizer decoupling node Y2/CVBS2 9 luminance analog voltage input 2 VCCA 10 analog supply voltage (+5 V) Y1/CVBS1 11 luminance analog voltage input 1 SEL1 12 selection control input 1 CAGC 13 AGC capacitor PWE 14 peak white enable input (active LOW) DEC3 15 decoupling input 3 ANOUTY 16 analog output for Y channel REG2 17 decoupling input 2 (internal stabilization loop decoupling) DGND 18 digital ground GATE A 19 AGC control input GATE B 20 clamp control input VCCD 21 digital supply voltage (+5 V) OFY 22 Y channel output format/chip enable (3-state input) Y7 23 Y channel data output; bit 7 (MSB) Y6 24 Y channel data output; bit 6 Y5 25 Y channel data output; bit 5 Y4 26 Y channel data output; bit 4 Y3 27 Y channel data output; bit 3 Y2 28 Y channel data output; bit 2 Y1 29 Y channel data output; bit 1 Y0 30 Y channel data output; bit 0 (LSB) OGND2 31 output ground 2 VCCO2 32 output supply voltage 2 (+5 V) C7 33 C channel data output; bit 7 (MSB) C6 34 C channel data output; bit 6 C5 35 C channel data output; bit 5 C4 36 C channel data output; bit 4 C3 37 C channel data output; bit 3 C2 38 C channel data output; bit 2 C1 39 C channel data output; bit 1 C0 40 C channel data output; bit 0 (LSB) 1996 Feb 01 4 Philips Semiconductors Product specification YC 8-bit low-power analog-to-digital video interface SYMBOL TDA8758 PIN DESCRIPTION 45 analog output for C channel DEC2 46 decoupling input 2 OFC 47 C channel output format/chip enable (3-state input) CCLPC 48 C channel clamping capacitor pin 1 index corner 44 REG1 handbook, full pagewidth DEC1 1 36 C4 CHROM2 2 35 C5 AGND 3 34 C6 CHROM1 4 33 C7 SEL2 5 32 VCCO2 CVBS3 6 C CLPY 7 30 Y0 SDN 8 29 Y1 Y2/CVBS2 31 OGND2 TDA8758 5 Y6 24 Y7 23 OFY 22 VCCD 21 GATE B 20 GATE A 19 REG2 17 25 Y5 DGND 18 SEL1 12 ANOUTY 16 26 Y4 DEC3 15 27 Y3 Y1/CVBS1 11 PWE 14 28 Y2 C AGC 13 9 V CCA 10 Fig.2 Pin configuration. 1996 Feb 01 37 C3 ANOUTC 38 C2 decoupling input 1 (internal stabilization loop decoupling) 39 C1 44 40 C0 REG1 41 VCCO1 output ground 1 42 CLK clock input 43 43 OGND1 42 OGND1 45 ANOUTC CLK 46 DEC2 output supply voltage 1 (+5 V) 47 OFC 41 48 CCLPC VCCO1 MGB470 Philips Semiconductors Product specification YC 8-bit low-power analog-to-digital video interface TDA8758 FUNCTIONAL DESCRIPTION Synchronization pulses The TDA8758 provides a simple interface between CVBS or Y/C analog signals and a digital colour decoder. GATE A and GATE B pulses are synchronization pulses occurring during the sync period and rear porch respectively. They should be distinct. Video inputs selection On the Y channel, the digital output of the ADC is compared to internal digital reference levels. The resultant outputs control the charge or discharge current of a capacitor connected to the CAGC pin. The voltage across this capacitor controls the gain of the video amplifier. This is the control loop. The input selector allows a choice from different video sources, and has one of the following configurations: A: Two Y/C and one CVBS signals B: One Y/C and two CVBS signals C: Three CVBS signals (only the Y channel is used). The sync level comparator is active during a positive-going pulse at the GATE A input. This means that sync pulse of the composite video signal is used as an amplitude reference. The bottom of the sync pulse is adjusted to obtain a digital output of logic 1 at the converter Y output. As the black level is digital level 64, the sync pulse will have a digital amplitude of 64 LSBs. The wiring of the five video inputs (pins 2, 4, 6, 9 and 11) and the control of the two selection inputs (pins 5 and 12) will depend on the available video sources. • In configuration A, connect as follows: – Y1 to pin 11 – C1 to pin 4 The Peak White control loop is active when the selection pin PWE is LOW. Then, if the Y video signal exceeds the digital code of 255, it will be limited to avoid any over-range of the converter. – Y2 to pin 9 – C2 to pin 2 – CVBS3 to pin 6. The clamp level control is accomplished by using the same techniques as used for the gain control. On both Y and C channels, the black level digital comparators are active during a positive-going pulse at the GATE B input. On the Y channel, the clamping capacitor connected to the CCLPY pin will be charged or discharged to adjust the digital output to code 64. On the C channel, the clamping capacitor connected to the CCLPC pin will be charged or discharged to adjust the digital output to code 128. Keep SEL2 (pin 5) LOW and select Y1/C1 or Y2/C2 by switching SEL1 (pin 12). CVBS3 is selected with SEL1 and SEL2 HIGH. • In configuration B, replace Y1 (or Y2) by a CVBS input (no more C1 or C2). The selection mode is the same. • In configuration C, connect as follows: – CVBS1 to pin 11 – CVBS2 to pin 9 – CVBS3 to pin 6. Use both SEL1 and SEL2 to select inputs. Remark: the video inputs selection is a static selection. 1996 Feb 01 6 Philips Semiconductors Product specification YC 8-bit low-power analog-to-digital video interface TDA8758 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCCA analog supply voltage −0.3 +7.0 V VCCD digital supply voltage −0.3 +7.0 V VCCO output supply voltage −0.3 +7.0 V ∆VCC supply voltage difference between VCCA and VCCD −1.0 +1.0 V supply voltage difference between VCCO and VCCD −1.0 +1.0 V supply voltage difference between VCCA and VCCO −1.0 +1.0 V VI input voltage referenced to AGND − 5.0 V Vclk(p-p) AC input voltage for switching (peak-to-peak value) referenced to DGND − VCCO V IO output current − +6 mA Tstg storage temperature −55 +150 °C Tamb operating ambient temperature 0 +70 °C Tj junction temperature − +150 °C THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER VALUE UNIT 72 K/W thermal resistance from junction to ambient in free air CHARACTERISTICS VCCA = V10 to V3 = 4.75 to 5.25 V; VCCD = V21 to V18 = 4.75 to 5.25 V; VCCO1 = V41 to V43 = 4.75 to 5.25 V; VCC02 = V32 to V31 = 4.75 to 5.25 V; AGND and DGND shorted together; VCCA to VCCD = −0.25 to +0.25 V; VCCO to VCCD = −0.25 to +0.25 V; VCCA to VCCO = −0.25 to +0.25 V; Tamb = 0 to +70 °C; typical values measured at VCCA = VCCD = VCCO = 5 V and Tamb = 25 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VCCA analog supply voltage 4.75 5.0 5.25 V VCCD digital supply voltage 4.75 5.0 5.25 V VCCO output stages supply voltage 4.75 5.0 5.25 V ICCA analog supply current − 59 70 mA ICCD digital supply current − 28 40 mA ICCOtot total output supply current − 19 28 mA Y channel 0.7 − 1.4 V C channel − 1.0 − V CL = 15 pF Video amplifier inputs Y1/CVBS1, Y2/CVBS2, CVBS3, CHROM1 AND CHROM2 INPUTS VI(p-p) input voltage (peak-to-peak value) AGC load with external capacitor; note 1 |Zi| input impedance fi = 6 MHz − 25 − kΩ CI input capacitance fi = 6 MHz − 2 − pF 1996 Feb 01 7 Philips Semiconductors Product specification YC 8-bit low-power analog-to-digital video interface SYMBOL PARAMETER TDA8758 CONDITIONS MIN. TYP. MAX. UNIT SEL1 AND SEL2 TTL INPUTS; see Table 1 VIL LOW level input voltage 0 − 0.8 V VIH HIGH level input voltage 2.0 − VCCD V IIL LOW level input current VI = 0.4 V −400 − − µA IIH HIGH level input current VI = 2.7 V − − 20 µA GATE A AND GATE B TTL INPUTS; see Figs 5 and 6 VIL LOW level input voltage 0 − 0.8 V VIH HIGH level input voltage 2.0 − VCCD V IIL LOW level input current VI = 0.4 V −400 − − µA IIH HIGH level input current VI = 2.7 V − − 20 µA 3.3 − V 3.75 − V AGC INPUT (PIN 13); see Fig.8 V13(min) AGC voltage for minimum gain at −3 dB − V13(max) AGC voltage for maximum gain at +3 dB − I12 AGC output current see Table 2 C-CHANNEL CLAMP INPUT (PIN 48) V48 CLAMP voltage for code 128 output I48 CLAMP output current − 3.45 − V see Table 3 Y-CHANNEL CLAMP INPUT (PIN 7) V7 CLAMP voltage for code 64 output I7 CLAMP output current − 3.70 − V see Table 3 Video amplifier dynamic characteristics αct crosstalk between video inputs (pins 2, 4, 6, 9 and 11) B − −63 −55 dB −3 dB bandwidth − 15 − MHz ∆G gain range −3 − +3 dB Gstab gain stability as a function of: − − 0.5 % − − 6 % supply voltage VCCA = 4.75 to 5.25 V fi = 4.43 MHz supply voltage and temperature Analog-to-digital converter inputs CLK INPUT (PIN 42) VIL LOW level input voltage 0 − 0.8 V VIH HIGH level input voltage 2.0 − VCCD V IIL LOW level input current Vclk = 0.4 V −400 − − µA IIH HIGH level input current Vclk = 2.7 V − − 20 µA CI input capacitance fclk = 32 MHz − 2 − pF 1996 Feb 01 8 Philips Semiconductors Product specification YC 8-bit low-power analog-to-digital video interface SYMBOL PARAMETER TDA8758 CONDITIONS MIN. TYP. MAX. UNIT OFY AND OFC INPUTS; 3-STATE; see Table 4 VIL LOW level input voltage 0 − 0.2 V VIH HIGH level input voltage 2.6 − VCCD V VI input voltage in high impedance state − 1.15 − V IIL LOW level input current −370 −300 − µA IIH HIGH level input current − 500 700 µA Analog-to-digital converter outputs ANOUTY AND ANOUTC OUTPUTS (PINS 16 AND 45); see Table 5 VANOUT output voltage digital output = 00 − 2.6 − V VANOUT output voltage digital output = 255 − 3.6 − V VANOUT(p-p) output voltage amplitude (peak-to-peak value) − 1.0 − V DIGITAL OUTPUTS Y0 TO Y7, C0 TO C7 VOL LOW level output voltage IOL = 2 mA 0 − 0.6 V VOH HIGH level output voltage IOL = −0.4 mA 2.4 − VCCD V Switching characteristics; see Fig.9 fclk(max) CLK input maximum frequency 30 32 − MHz tCPH clock pulse width HIGH 12 − − ns tCPL clock pulse with LOW 12 − − ns note 2 Analog signal processing from video input to digital output on both channels; 0 dB gain (fclk = 32 MHz) INL DC integral non-linearity − ±0.75 ±1.5 LSB DNL DC differential non-linearity − ±0.4 ±1.0 LSB AINL AC integral non linearity fi = 4.43 MHz − ±1.5 − LSB ADNL AC differential non-linearity fi = 4.43 MHz − ±0.5 − LSB THD total harmonic distortion note 3 − −52 − dB EB effective bits fi = 4.43 MHz; note 4 − 7.1 − bits Gdiff differential gain V16,45 = 1.0 V (p-p); see Fig.4; PAL modulated ramp; note 5 − 1.5 3.0 % ϕdiff differential phase see Fig.5; PAL modulated ramp; note 5 − 0.6 1.5 deg SVRR2 supply voltage ripple rejection note 6 − − 5 %/V 1996 Feb 01 9 Philips Semiconductors Product specification YC 8-bit low-power analog-to-digital video interface SYMBOL PARAMETER TDA8758 CONDITIONS MIN. TYP. MAX. UNIT Timing (fclk = 32 MHz); see Fig.9 DIGITAL OUTPUTS (CL = 15 pF) tds sampling delay time − 2 − ns th output hold time 10 − − ns td output delay time − 15 18 ns tW clamp pulse width 2 3 − µs see Figs 6 and 7 3-state output delay times; see Fig.10 tdZH enable HIGH − 12 14 ns tdZL enable LOW − 10 12 ns tdHZ disable HIGH − 58 62 ns tdLZ disable LOW − 70 74 ns Notes 1. 0 dB is obtained at the AGC amplifier when applying VI(p-p) = 1.0 V on Y channel. 2. It is recommended that the rise and fall times of the clock are ≥1 ns. In addition, a ‘good layout’ for the digital and analog grounds is recommended. 3. THD (total harmonic distortion) is obtained with the addition of the first five harmonics: F THD = 20 log --------------------------------------------------------------------------------------------------------------2 2 2 2 2 (2nd) + (3rd) + (4th) + (5th) + (6th) a) F being the fundamental harmonic referenced at 0 dB for a full-scale sine wave input. 4. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8 K acquisition points per equivalent fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency (NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB × 6.02 + 1.76 dB. 5. Measurement carried out using video analyser VM700A, where video analog signal is reconstructed through a digital-to-analog converter. 6. The supply voltage ripple rejection is the relative variation of the analog signal (full-scale signal at input) for 0.5 V of supply variation: ∆ ( V I ( 00 ) – V I ( FF ) ) × ( V I ( 00 ) – V I ( FF ) ) SVRR2 = ---------------------------------------------------------------------------------------------------∆V CCA 1996 Feb 01 10 Philips Semiconductors Product specification YC 8-bit low-power analog-to-digital video interface TDA8758 SEL2 handbook, full pagewidth 5 2 CHROM2 SEL2 C CHANNEL 4 CHROM1 9 Y2/CVBS2 Y CHANNEL 9 Y2/CVBS2 11 Y1/CVBS1 6 CVBS3 Y CHANNEL C CHANNEL 4 CHROM1 6 CVBS3 5 2 CHROM2 11 Y1/CVBS1 12 SEL1 12 SEL1 (a) SEL2 C CHANNEL 4 CHROM1 6 CVBS3 Y CHANNEL 9 Y2/CVBS2 Y1/CVBS1 5 2 CHROM2 (b) 11 12 SEL1 MGB471 (c) Fig.3 Video inputs selector. Table 1 Video input selection SEL1 SEL2 Y-CHANNEL C-CHANNEL FIGURE 3 0 X(1) Y1/CVBS1 CHROM1 (a) 1 0 Y2/CVBS2 CHROM2 (b) 1 1 CVBS3 CHROM2 (c) Note 1. X = don't care. 1996 Feb 01 11 Philips Semiconductors Product specification YC 8-bit low-power analog-to-digital video interface Table 2 AGC output current PWE GATE A 0 0 0 Table 4 OFY and OFC input coding DIGITAL OUTPUT 1 TDA8758 OFY (or OFC) IAGC Y0 to Y7 (or C0 TO C7) 0 active, twos complement output < 255 0 µA 1 high impedance output > 255 +540 µA circuit(1) active, binary output < 0 +8 µA 0 < output < 255 −8 µA output > 255 +540 µA 1 0 X(1) 0 µA 1 1 output < 0 +8 µA 0 < output < 255 −8 µA open Note 1. Use C ≥ 10 pF to DGND. Note 1. X = don't care. Table 3 CLAMP output current CLAMP GATE B C 1 X(1) 0 Y 1 DIGITAL OUTPUT ICLAMP output < 128 +54 µA output > 128 −54 µA X(1) 0 µA output < 64 +54 µA 64 < output −54 µA Note 1. X = don't care. Table 5 Output coding and ANOUTY (or ANOUTC) voltage (typical values) BINARY OUTPUTS STEP VI TWOS COMPLIMENT D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Underflow − 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 2.6 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 − 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 . − . . . . . . . . . . . . . . . . . − . . . . . . . . . . . . . . . . 254 − 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 255 3.6 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 Overflow − 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1996 Feb 01 12 Philips Semiconductors Product specification YC 8-bit low-power analog-to-digital video interface TDA8758 MBE455 handbook, full pagewidth 1.0 DIFFERENTIAL GAIN (%) (2) (1) 0.0 (4) (5) (3) 1.0 (6) 2.0 3.0 1st 2nd 3rd 4th 5th 6th step number (1) = 0.00; (2) = 0.09; (3) = −0.63; (4) = −0.45; (5) = −0.45; (6) = −1.23. Differential gain = max. (2) − min. (6) = 1.32%. Fig.4 Typical differential gain result on VM700A. MBE456 handbook, full pagewidth 2.0 DIFFERENTIAL PHASE (deg) 1.0 (1) (2) (5) 0 (6) (4) (3) 1.0 2.0 1st 2nd 3rd 4th 5th 6th step number (1) = 0.00; (2) = 0.03; (3) = −0.53; (4) = −0.32; (5) = 0.01; (6) = −0.08. Differential phase = max. (2) − min. (3) = 0.56 deg. Fig.5 Typical differential phase result on VM700A. 1996 Feb 01 13 Philips Semiconductors Product specification YC 8-bit low-power analog-to-digital video interface TDA8758 handbook, full pagewidthdigital output level 255 safety margin peak-level gain control 213 standard picture level black-level clamping 64 sync-level control 0 tW time GATE A MGB472 tW GATE B Fig.6 Control mode Y channel. andbook, full pagewidth digital output level 255 black-level clamping 128 0 tW time GATE B MGB473 Fig.7 Control mode C-channel. 1996 Feb 01 14 Philips Semiconductors Product specification YC 8-bit low-power analog-to-digital video interface TDA8758 MBE463 8 handbook, AGC full pagewidth GAIN (dB) 6 4 2 0 2 4 6 8 3.0 3.2 3.1 3.3 3.4 3.6 3.5 3.8 3.7 3.9 4.0 C AGC voltage (V) Dotted line: Typical curve (Tamb = 25 °C; VCC = 5 V). Full line: Maximum envelope (Tamb = 0 to 70 °C; VCC = 4.75 to 5.25 V). Fig.8 AGC behaviour as a function temperature and supply voltage for ANOUTY output; fi = 4.43 MHz, Vi = 0 dB. t CPL handbook, full pagewidth t CPH 1.4 V CLK sample N sample N + 1 sample N + 2 Vl t ds DATA C0 to C7 Y0 to Y7 th 2.4 V DATA N-2 DATA N-1 DATA N 1.4 V 0.4 V td Fig.9 Timing diagram. 1996 Feb 01 DATA N+1 15 MBE454 Philips Semiconductors Product specification YC 8-bit low-power analog-to-digital video interface handbook, full pagewidth TDA8758 V CCD 50 % OFC OFY 1.15 V t dHZ t dZH HIGH 90 % output data 50 % HIGH Z t dLZ t dZL HIGH Z output data 50 % LOW 10 % V CCD 3.3 kΩ S1 TDA8758 15 pF TEST S1 t dLZ t dZL VCCD VCCD t dHZ GND t dZH GND OFC OFY MBE453 fOFC = fOFY = 100 kHz. Fig.10 Timing diagram and test conditions of 3-state output delay time. 1996 Feb 01 16 Philips Semiconductors Product specification YC 8-bit low-power analog-to-digital video interface TDA8758 APPLICATION INFORMATION VCCA AGND handbook, full pagewidth ANOUTC (1) OFC 3.3 nF 1 nF 18 nF CCLPC AGND 1 µF DEC1 CHROM2 75 Ω AGND 75 Ω 4.7 µF CHROM1 SEL2 4.7 µF 75 Ω 18 nF 22 nF AGND 75 Ω 4.7 µF CVBS3 C CLPY SDN Y2/CVBS2 VCCA 75 Ω 4.7 µF Y1/CVBS1 SEL1 48 47 46 45 CLK C1 C2 C3 44 43 42 41 40 39 38 37 1 36 C4 2 35 C5 3 34 C6 4 33 C7 5 32 VCCO2 ( 5 V) 31 OGND2 6 TDA8758 7 30 Y0 8 29 Y1 9 28 Y2 10 27 Y3 11 26 Y4 25 Y5 12 13 CAGC 14 470 nF PWE 15 16 17 18 DEC3 REG2 1 nF 3.3 nF ANOUTY AGND (1) 19 20 GATE A DGND VCCA Fig.11 Application diagram. 17 21 22 VCCD ( 5 V) GATE B (1) It is recommended that pin 16 and pin 45 are not loaded in order to avoid any distortion. 1996 Feb 01 C0 REG1 DEC2 22 nF V CCO1 ( 5 V) OGND1 OFY 23 24 Y7 Y6 MGB476 Philips Semiconductors Product specification YC 8-bit low-power analog-to-digital video interface TDA8758 9 andbook, full pagewidth 4.7 µF CHROMA IN C27 4 2 LUMA IN CVBS1 IN 4.7 µF 4.7 µF C26 11 C11 9 4.7 µF CVBS2 IN C25 IN0 6 12 5 IN1 GPSWO HSY HCL C12 0.1 µF 0.1 µF C13 0.022 µF 19 20 7 48 0.022 µF 0.022 µF 14 C14 8 C15 1 0.022 µF C16 46 C17 15 INADCY VCCA 16 45 INADCC 0.47 µF C18 13 0.047 µF C19 0.047 µF 44 C20 17 22 VCC VCC 1 47 JP15 2 3 3 CHR7 CHROMA1 CHR6 CHROMA2 CHR5 CHR4 Y1/CVBS1 CHR3 CHR2 Y2/CVBS2 CHR1 CVBS3 CHR0 PAD100 TEST PT J10 CHR7 34 CHR6 35 CHR5 36 CHR4 37 CHR3 38 CHR2 39 CHR1 40 CHR0 23 CVBS7 24 CVBS6 25 26 CVBS5 CVBS4 27 CVBS3 28 CVBS2 29 CVBS1 30 CVBS0 SAA7151B Y7 SEL2 Y6 PWE Y5 Y4 GATE A Y3 Y2 GATE B Y1 Y0 CLMP_Y 27 U4 CHR7 13 CHR6 12 CHR5 CHR4 11 10 CHR3 9 CHR2 8 CHR1 7 CHR0 6 CVBS7 23 CVBS6 22 CVBS5 CVBS4 21 20 CVBS3 17 CVBS2 16 CVBS1 15 CVBS0 14 CVBS0 to 7 TDA8758 CLMP_C CLK SDN 42 220 Ω DEC_LLC R13 VCC DEC1 DEC2 VCCO1 DEC3 VCCO2 IN_ADC_Y VCCD IN_ADC_C VCCA 41 CX3 22 µF 32 21 CCX4 0.1 µF VCCA 10 44 XTAL2 AGC_CAP REG1 OGND1 REG2 OGND2 OE_Y DGND OE_C AGND 31 43 CX12 0.1 µF XTAL1 IN1 DEC_LLC 37 DEC_REF 36 LFCO RES TDA8758 UV7 CHR6 UV6 CHR5 CHR4 UV5 UV4 CHR3 UV3 CHR2 UV2 CHR1 UV1 CHR0 UV0 CVBS7 D7 CVBS6 D6 CVBS5 CVBS4 D5 D4 CVBS3 D3 CVBS2 D2 CVBS1 D1 CVBS0 D0 HREF SDAT HS XTAL VS SAA7151B GTBS XTAL1 24 25 GPSW1 MUXC GPSW2 29 26 ODD 27 4 36 3 RTCO HSY FEIN HCL GPSWO LL27 RSVRD CREF LFCO IICSA RES SDA 12 25 13 5 18 INADCC VCC CX14 0.1 µF VCC 28 52 CX6 22 µF CX5 0.1 µF VCC PAD100 J24 GROUND SCL 37 24 INADCY VCCA CHR7 VCCA PAD100 TEST PT J9 VCC 34 68LLC50 3 HCL HEADER 3 3SIP100 33 43 FSI IN0 18 HSY 48 44 26 CHR0 to 7 SEL1 1 HEADER 3 3SIP100 61 10 33 1 JP14 2 1 60 U2 VDDA SP VDD1 AP VDD2 VSSA VDD3 VSS1 VDD4 VSS2 VSS3 VSS4 56 DEC_UV6 57 DEC_UV5 58 DEC_UV4 59 DEC_UV3 60 DEC_UV2 61 DEC_UV1 62 DEC_UV0 DEC_Y0 to 7 45 DEC_Y7 46 DEC_Y6 47 DEC_Y5 48 DEC_Y4 49 DEC_Y3 50 DEC_Y2 53 DEC_Y1 54 DEC_Y0 42 31 30 DEC_HREF DEC_HS DEC_VS 66 68 65 39 32 64 63 4.7 kΩ R64 DEC_FI DEC_RTC GPSWO 39 43 40 41 SDA SCL VCC 1 2 35 3 2 1 19 38 51 67 JP5 HEADER 3 3SIP100 PAD100 J25 GROUND U3 GND VCCA CX7 0.1 µF VCC CX13 0.1 µF 7 14 LL1 to 5A 11 19 LFCO 4.7 kΩ 2 R12 1 22 kΩ R11 RES 12 5 8 17 LL1 to 5B LL3A LL3B LFCOSEL LFCO2 CE MS CLKREF SAA7197 PORD VSSA RES VSSD VDDA VDDD VSSD VDDD VSSD VSSD 33 Ω R14 10 20 33 Ω 16 R15 15 33 Ω 3 R16 4 6 9 C24 0.1 µF RES 1 2 DEC_LLC 3 JP16 5 7 4 6 8 DEC_LLC2 DEC_CREF RES C21 10 pF HEADER 4X2 8HH100 C22 10 pF 13 18 20SOP300 MBH012 18 XTAL2 Y2 24.576 MHz 2SIP100 XTAL1 C23 0.001 µF L2 10 µH Fig.12 Example of system application (DPC71 evaluation board). 1996 Feb 01 DEC_UV0 to 7 55 DEC_UV7 Philips Semiconductors Product specification YC 8-bit low-power analog-to-digital video interface TDA8758 PACKAGE OUTLINE LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2 c y X 36 25 A 37 24 ZE Q e E HE A A2 (A 3) A1 w M pin 1 index θ bp Lp L 13 48 detail X 12 1 ZD e v M A w M bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp Q v w y mm 1.60 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 7.1 6.9 0.5 9.15 8.85 9.15 8.85 1.0 0.75 0.45 0.69 0.59 0.2 0.12 0.1 Z D (1) Z E (1) θ 0.95 0.55 7 0o 0.95 0.55 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 93-06-15 94-12-19 SOT313-2 1996 Feb 01 EUROPEAN PROJECTION 19 o Philips Semiconductors Product specification YC 8-bit low-power analog-to-digital video interface If wave soldering cannot be avoided, the following conditions must be observed: SOLDERING Introduction • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. • The footprint must be at an angle of 45° to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering LQFP packages LQFP48 (SOT313-2), LQFP64 (SOT314-2) or LQFP80 (SOT315-1). This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Reflow soldering Reflow soldering techniques are suitable for all LQFP packages. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. Wave soldering Wave soldering is not recommended for LQFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. 1996 Feb 01 TDA8758 20 Philips Semiconductors Product specification YC 8-bit low-power analog-to-digital video interface TDA8758 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1996 Feb 01 21 Philips Semiconductors Product specification YC 8-bit low-power analog-to-digital video interface NOTES 1996 Feb 01 22 TDA8758 Philips Semiconductors Product specification YC 8-bit low-power analog-to-digital video interface NOTES 1996 Feb 01 23 TDA8758 Philips Semiconductors – a worldwide company Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428) BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367 Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. (02)805 4455, Fax. (02)805 4466 Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213, Tel. (01)60 101-1236, Fax. (01)60 101-1211 Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands, Tel. (31)40-2783749, Fax. (31)40-2788399 Brazil: Rua do Rocio 220 - 5th floor, Suite 51, CEP: 04552-903-SÃO PAULO-SP, Brazil, P.O. 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(708)296-8556 Uruguay: Coronel Mora 433, MONTEVIDEO, Tel. (02)70-4044, Fax. (02)92 0601 Internet: http://www.semiconductors.philips.com/ps/ For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-2724825 SCDS47 © Philips Electronics N.V. 1996 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 537021/1100/03/pp24 Document order number: Date of release: 1996 Feb 01 9397 750 00606