INTEGRATED CIRCUITS DATA SHEET TDA1548T Bitstream continuous calibration filter-DAC with headphone driver and DSP Product specification Supersedes data of 1995 Aug 02 File under Integrated Circuits, IC01 1995 Nov 15 Philips Semiconductors Product specification Bitstream continuous calibration filter-DAC with headphone driver and DSP TDA1548T FEATURESPRODUCT SPECIFICATION Easy application • Only first-order analog post-filtering required • Headphone amplifiers and digital filter integrated • Component saving common headphone output • Selectable system clock (SYSCLK) 64fs, 256fs or 384fs • 16, 18 or 20 bits I2S-bus or LSB justified serial input format integrated headphone driver featuring unique signal processing functions. The digital processing features are of high sound processing quality due to the wide dynamic range of the bitstream conversion technique. • Input pins suitable with 5 V low supply voltage interfacing • Small package (SSOP28) • Single rail supply (3 V). The TDA1548T supports the I2S-bus data input mode with word lengths of up to 20 bits and the LSB justified serial data input format with word lengths of 16, 18 or 20 bits. The clock system is selectable (64fs, 256fs or 384fs) by means of selection pins. Two cascaded half band filters, linear interpolator and a sample-and-hold function increase the oversampling rate from 1fs to 64fs. A second-order noise shaper converts this oversampled data into a bitstream for the 5-bit continuous calibration DACs. High performance • Superior signal-to-noise ratio • Wide dynamic range • Continuous calibration digital-to-analog conversion combined with noise shaping technique. Features • Low power dissipation On board amplifiers convert the output current to a voltage signal capable of driving a headphone or line output. The common operational amplifier application eliminates the need for capacitors. • Digital volume control • Soft mute • Digital tone control (Bass Boost and Treble) The TDA1548T has some sound processing functions which are controllable by a potentiometer. These functions are volume, bass boost and treble. The flat/min/max switch can also be controlled by a potentiometer. The analog values are converted to a digital code, which is then further translated internally to a set of coefficients for either volume, bass boost or treble. • Digital de-emphasis • Analog control of digital sound control functions. GENERAL DESCRIPTION The TDA1548T is a dual CMOS digital-to-analog converter (DAC) with up-sampling filter and noise shaper and ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA1548T SO28 TDA1548TZ SSOP28 1995 Nov 15 DESCRIPTION VERSION plastic small outline package; 28 leads; body width 7.5 mm SOT136-1 plastic shrink small outline package; 28 leads; body width 5.3 mm SOT341-1 2 Philips Semiconductors Product specification Bitstream continuous calibration filter-DAC with headphone driver and DSP TDA1548T QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDD supply voltage note 1 2.7 3.0 4.0 V IDD supply current note 2 − 15 − mA VoFS(rms) full-scale output voltage VDD = 3 V 0.57 0.64 0.71 V (THD+N)/S total harmonic distortion plus noise as a function of signal 0 dB signal − −65 −60 dB − 0.056 0.1 % − −85 −78 dB − 0.006 0.013 % −60 dB signal; ROL = 32 Ω or ROL = 5 kΩ − −35 −30 dBA − 1.778 3.162 % A-weighted; at code 00000H 90 95 − dBA S/N signal-to-noise ratio BR input bit rate at data input 0 dB signal; ROL = 5 kΩ fsys = 384fs − 48fs − fsys = 256fs − 64fs − fsys = 64fs − 64fs − fsys system clock frequency 2.048 − 18.432 TCFS full-scale temperature coefficient at analog outputs (VOL and VOR) − ±100 × 10−6 − Tamb operating ambient temperature −20 − +70 Notes 1. All VDD and VSS pins must be connected to the same supply or ground respectively. 2. Measured at input code 00000H and VDD = 3 V. 1995 Nov 15 3 MHz °C Philips Semiconductors Product specification Bitstream continuous calibration filter-DAC with headphone driver and DSP TDA1548T BLOCK DIAGRAM handbook, full pagewidth IF1 13 IF2 DATA 14 9 WS BCK 8 7 16 SERIAL DATA INPUT 15 SYSCLK 12 SOFT MUTE CONTROL TIMING CLSEL VOLUME AND SOUND CONTROL VOLUME CONTROL 17 MODE1 20 FILTER STAGE 1 − OP4 + 2 fs 6 AD3S ADVC ADBB ADTR VDDA 1 fs 5 21 19 SOUND CONTROL MODE0 22 MUTE DEEM FILTER STAGE 2 18 ADref 4 fs LINEAR INTERPOLATOR VSSA 8 fs FILTCL RCONV1 CEXT1 1.2 kΩ 3 11 DATA ENCODER DATA ENCODER 10 6 kΩ 1.2 kΩ − OP2 + 1.8 nF CEXT2 27 VOR 16 (4-bit) CALIBRATED CURRENT SINKS − OP3 TDA1548T VSSA 1 28 2 23 24 VDDA VSSA MGC668 VSSO VDDO VCOM Fig.1 Block diagram. 1995 Nov 15 4 VDDD RCONV2 + SSA RIGHT OUTPUT SWITCHES VSSD 26 FILTCR 25 6 kΩ V 16 (4-bit) CALIBRATED CURRENT SOURCES 16 (4-bit) CALIBRATED CURRENT SINKS DDA 10 µF 2nd ORDER NOISE SHAPER REFERENCE SOURCE V Vref 2nd ORDER NOISE SHAPER LEFT OUTPUT SWITCHES − OP1 + VOL 8 x OVERSAMPLING (SAMPLE-AND-HOLD) 16 (4-bit) CALIBRATED CURRENT SOURCES 4 1.8 nF 8 x OVERSAMPLING (SAMPLE-AND-HOLD) Philips Semiconductors Product specification Bitstream continuous calibration filter-DAC with headphone driver and DSP TDA1548T PINNING SYMBOL PIN DESCRIPTION VSSO 1 operational amplifier ground VCOM 2 common output pin VOL 3 left channel audio voltage output FILTCL 4 capacitor for left channel first-order filter function should be connected between this pin and VOL (pin 3) MODE0 5 mode 0 selection pin MODE1 6 mode 1 selection pin BCK 7 bit clock input WS 8 word select input DATA 9 data input VSSO 1 28 V DDO VDDD 10 digital supply voltage VCOM 2 27 VOR VSSD 11 digital ground VOL 3 26 FILTCR SYSCLK 12 system clock 64fs, 256fs or 384fs FILTCL 4 IF1 13 input format selection 1 25 V ref 14 input format selection 2 MODE0 5 IF2 24 V SSA DEEM 15 de-emphasis input (fs = 44.1 kHz) (active HIGH) MODE1 6 23 V DDA MUTE 16 soft-mute input (active HIGH) CLSEL 17 ADref 18 ADTR 19 analog sense input for treble setting BCK 7 22 AD3S TDA1548T WS 8 21 ADVC system clock selection input DATA 9 20 ADBB reference voltage output to external potentiometer VDDD 10 19 ADTR VSSD 11 18 AD ref ADBB 20 analog sense input for bass boost setting ADVC 21 analog sense input for volume control setting AD3S 22 3-position switch input for flat/min/max setting VDDA 23 analog supply voltage VSSA 24 analog ground Vref 25 internal reference voltage (0.5VDDA typ) FILTCR 26 capacitor for right channel first-order filter function should be connected between this pin and VOR (pin 27) VOR 27 right channel audio voltage output VDDO 28 operational amplifier supply voltage 1995 Nov 15 handbook, halfpage SYSCLK 12 17 CLSEL IF1 13 16 MUTE IF2 14 15 DEEM MGC669 Fig.2 Pin configuration. 5 Philips Semiconductors Product specification Bitstream continuous calibration filter-DAC with headphone driver and DSP For each multiplexed timeslot the full approximation cycle is completed, immediately after which the next input will start being sampled. FUNCTIONAL DESCRIPTION The TDA1548T CMOS DAC incorporates an up-sampling digital filter, a linear interpolator, a noise shaper, continuous calibrated current sources and headphone amplifiers. The 1fs input data is increased to an oversampling rate of 64fs. This high-rate oversampling, together with the 5-bit DAC, enables the filtering required for waveform smoothing and out-of-band noise reduction to be achieved by simple first-order analog post-filtering. The time slot for one input lasts 64 steps at a step advance rate of 8 × fs, which amounts to 181 µs at fs = 44.1 kHz. Because four inputs are multiplexed, the sample rate for each analog input is 1.38 kHz. A buffered version of an internally generated reference voltage is available at output pin ADref. Because the internal AD derives from the same reference voltage, this allows for optimum mapping of the external analog control value onto the useful AD input voltage range. The idea is to bias a potentiometer to ADref, using a wiper to control the input voltage between 0 V and ADref. Hysteresis is implemented to improve noise immunity of the AD in order to prevent a stable setting of the potentiometer, to a point near a quantization threshold, from producing two alternating digital codes which could give rise to audible volume or boost changes. An hysteresis of 1 LSB is implemented digital. A shift in code must be at least 2 LSB either up or down from the current value, otherwise the internal digital code will remain at the current value. System clock and data input format The TDA1548T accommodates slave mode only, this means that in all applications the system devices must provide the system clock. The system frequency is selectable at pins CLSEL, MODE0 and MODE1 (see Table 1). The TDA1548T supports the following data input modes (see Table 2): I2S-bus with data word length of up to 20 bits LSB justified serial format with data word length of 16, 18 or 20 bits. The input formats are illustrated in Fig.4. Left and right data-channel words are time multiplexed. SINGLE PIN THREE MODE SELECTION A special input pin AD3S (pin 22), controls the mode in which the sound processing block operates. Not between two but three modes; whether the DSP should follow the AD inputs applying maximum effect, the minimum effect or overrule the boost effects thereby resulting in a flat frequency characteristic in the treble and bass boost sections. Analog control of digital sound processing features Digital sound processing settings are controlled via analog sense inputs that translate an analog voltage from, for example, a potentiometer wiper to a digital code, which is then further translated internally to a set of coefficients for either treble, bass boost or volume. Internally the same AD is used to detect the input level present at this pin as is used for the three sound control pins. An internal bias circuit containing of two MOSTs supplies a mid-range voltage so that this input can be operated with a minimum of external components. A HIGH or LOW input level is created by tying the pin to ADref or ground respectively, the intermediate value is achieved by leaving the pin open-circuit. The analog input value is acquired by an internal 6-bit ADC, sampling the three input pins ADVC, ADBB and ADTR and the three-mode selection pin ADS3 (see Section “Single pin three mode selection”) in a multiplexed fashion. Sampling of the input voltage is performed by a straight forward technique of linear approximation; from the starting value of 0 V, an internal linear approximation voltage is incremented periodically in steps of 1/66th of the scale, with an internal comparator detecting when the approximation value oversteps the input value. Tolerance is built in at the top and bottom end of the scale by dimensioning the resistive elements at the top and bottom of the ladder equals 1R. Thus the ladder is built up of 64 elements of value R, two of value R, making a typical quantization step size of approximately 1.5 V (ADref) divided-by-66 (amount of Rs), equals 22.7 mV. 1995 Nov 15 TDA1548T Volume control Since there is no headroom included into the sound control section, the volume control precedes the sound control. Full volume and neutral setting (flat) of the sound control results in a full-scale output. Any tone boost will immediately cause clipping, which can be avoided by reducing the volume setting. 6 Philips Semiconductors Product specification Bitstream continuous calibration filter-DAC with headphone driver and DSP TDA1548T de-emphasis frequency characteristics for the sample rate 44.1 kHz. With its 18-bit dynamic range, the digital de-emphasis of the TDA1548T is a convenient and component-saving alternative to analog de-emphasis. Soft mute Soft mute is controlled by MUTE (pin 16). When the input is active HIGH the value of the sample is decreased smoothly to zero following a raised cosine curve. 32 coefficients are used to step down the value of the data, each one being used 32 times before stepping on to the next. This amounts to a mute transition time of 23 ms at fs = 44.1 kHz. When MUTE is released (LOW), the samples are returned to the full level again following a raised cosine curve with the same coefficients being used in the reverse order. Mute is synchronized to the sample clock, so that the operation always takes place on complete samples. When the DEEM pin is active HIGH, de-emphasis is enabled. De-emphasis is synchronized to the sample clock, so that operation always takes place on complete samples. Oversampling filter and noise shaper The digital filter is a four times oversampling filter. It consists of two sections which each increase the sample rate by 2. The second order noise shaper operates at 64fs. It shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique, used in combination with a sign-magnitude coding, enables high signal-to-noise ratios to be achieved. The noise shaper outputs a 5-bit PDM bitstream signal to the DAC. Digital sound processing features BASS BOOST A strong bass boost effect, which is useful in compensating for poor bass response of portable headphone sets, is implemented digitally in the TDA1548T and can be controlled by ADBB (pin 20) and AD3S (pin 22). Table 3 shows the bass boost values at different input voltages. Table 4 shows the selection mode status (flat/min/max) at different input voltages. Valid settings range from “flat” (no influence on audio) to +18 dB with step sizes of 2 dB in “minimum” and to +24 dB with step sizes of 2 dB in “maximum”. The programmable bass boost filter is a second-order shelving type with a fixed corner frequency of 130 Hz for the “minimum” setting and a fixed corner frequency of 230 Hz for the “maximum” setting and has a Butterworth characteristic. Because of the exceptional amount of programmable gain, bass boost should be used in conjunction with adequate prior attenuation, using the volume control. Continuous calibration DAC The dual 5-bit DAC uses the continuous calibration technique. This method, based on charge storage, involves exact duplication of a single reference current source. In the TDA1548T, 32 such current sources plus 1 spare source are continuously calibrated. The spare source is included to allow continuous converter operation. The DAC receives a 5-bit data bitstream from the noise shaper. This data is converted to a sign-magnitude code so that no current is switched to the output during digital silence (input 00000H). In this way very high signal-to-noise performance is achieved. TREBLE Component-saving stereo headphone driver A treble effect is implemented digitally in the TDA1548T and can be controlled by ADTR (pin 19) and AD3S (pin 22). Table 3 shows the treble values at different input voltages. Table 4 shows the selection mode status (flat/min/max) at different input voltages. Valid settings range from “flat” (no influence on audio) to +6 dB with step sizes of 2 dB in “minimum” and to +6 dB with a step size of 2 dB in “maximum”. The programmable treble filter is a first-order shelving type with a fixed corner frequency of 2.8 kHz for the “minimum” setting and a fixed corner frequency of 5.0 kHz for the “maximum” setting. High precision, low-noise amplifiers together with the internal conversion resistors RCONV1 and RCONV2 convert the converter output current to a voltage capable of driving a line output or headphone. The voltage is available at VOL and VOR (0.64 V RMS typical). A major component saving feature of the TDA1548T is that no DC-blocking capacitors are needed in the application, despite the asymmetrical supply. The VCOM output, pin 2, is biased to the same voltage that the right and left channel voltage outputs are, Vref, and is capable of sinking the sum of left and right channel load currents. Therefore, connecting a load between one of the outputs and VCOM only gives rise to a negligible amount of DC current through the load. DE-EMPHASIS De-emphasis is controlled by DEEM (pin 15). The digital de-emphasis filter is dimensioned to produce the 1995 Nov 15 7 Philips Semiconductors Product specification Bitstream continuous calibration filter-DAC with headphone driver and DSP Table 1 System clock selection TDA1548T Table 2 Data input formats PINS PINS DESCRIPTION CLSEL MODE0 MODE1 0 0 0 0 0 0 1 1 0 1 1 Table 3 FORMAT IF1 IF2 256fs 0 0 I2S-bus 1 64fs 0 1 LSB justified, 16 bits X reserved 1 1 0 LSB justified, 18 bits 0 384fs 1 1 LSB justified, 20 bits 0 1 reserved 2 1 X reserved 3 Relationship between VC, BB and TR ANALOG INPUT VALUES (V); PINS ADTR, ADBB AND ADVC 1995 Nov 15 VOLUME (ADVC) BASS BOOST (ADBB) TREBLE (ADTR) MAX. MIN. MAX. MIN. ADref × 65/66 −0 0 0 0 0 ADref × 64/66 −0 0 0 0 0 ADref × 63/66 −1 0 0 0 0 ADref × 62/66 −2 0 0 0 2 ADref × 61/66 −3 2 2 2 2 ADref × 60/66 −4 2 2 2 2 ADref × 59/66 −5 4 4 2 2 ADref × 58/66 −6 4 4 2 2 ADref × 57/66 −7 6 6 4 4 ADref × 56/66 −8 6 6 4 4 ADref × 55/66 −9 8 8 4 4 ADref × 54/66 −10 8 8 4 4 ADref × 53/66 −11 10 10 6 6 ADref × 52/66 −12 10 10 6 6 ADref × 51/66 −13 12 12 6 6 ADref × 50/66 −14 12 12 6 6 ADref × 49/66 −15 14 14 .... .... ADref × 48/66 −16 14 14 .... .... ADref × 47/66 −17 16 16 .... .... ADref × 46/66 −18 16 16 .... .... ADref × 45/66 −19 18 18 .... .... ADref × 44/66 −20 18 18 .... .... ADref × /4366 −21 20 18 .... .... ADref × 42/66 −22 20 18 .... .... ADref × 41/66 −23 22 .... .... .... ADref × 40/66 −24 22 .... .... .... ADref × 39/66 −25 24 .... .... .... 8 Philips Semiconductors Product specification Bitstream continuous calibration filter-DAC with headphone driver and DSP ANALOG INPUT VALUES (V); PINS ADTR, ADBB AND ADVC Table 4 VOLUME (ADVC) TDA1548T BASS BOOST (ADBB) TREBLE (ADTR) MAX. MIN. MAX. MIN. ADref × 38/66 −26 24 .... .... .... ADref × 37/66 −27 .... .... .... .... ADref × 36/66 −28 .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... ADref × 5/66 −59 24 18 6 6 ADref × 4/66 −60 24 18 6 6 ADref × 3/66 −∞ 24 18 6 6 ADref × 2/66 −∞ 24 18 6 6 Relationship mode selection ANALOG INPUT VALUE (V); PIN AD3S FLAT, MINIMUM OR MAXIMUM ADref × 65/66 flat ADref × 64/66 flat .... .... 1995 Nov 15 .... .... ADref × 51/66 flat ADref × 50/66 flat ADref × 49/66 minimum ADref × 48/66 minimum .... .... .... .... ADref × 19/66 minimum ADref × 18/66 minimum ADref × 17/66 maximum ADref × 16/66 maximum .... .... .... .... ADref × 3/66 maximum ADref × 2/66 maximum 9 Philips Semiconductors Product specification Bitstream continuous calibration filter-DAC with headphone driver and DSP TDA1548T LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDD supply voltage − 4.5 V Txtal maximum crystal temperature − +150 °C Tstg storage temperature −65 +125 °C Tamb operating ambient temperature Ves electrostatic handling note 1 −20 +70 °C note 2 −3000 +3000 V note 3 −300 +300 V Notes 1. All VDD and VSS connections must be made to the same power supply. 2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor. Pin 18 = −1500 V (min) and +1500 V (max). 3. Equivalent to discharging a 200 pF capacitor via a 2.5 µH series inductor. THERMAL CHARACTERISTICS SYMBOL Rth j-a DESCRIPTION VALUE UNIT SO28 60 K/W SSOP28 80 K/W thermal resistance from junction to ambient in free air QUALITY SPECIFICATION In accordance with UZW-BO/FQ-0601. The numbers of the quality specification can be found in the “Quality Reference Handbook”. The Handbook can be ordered using the code 9397 750 00192. 1995 Nov 15 10 Philips Semiconductors Product specification Bitstream continuous calibration filter-DAC with headphone driver and DSP TDA1548T DC CHARACTERISTICS All voltages referenced to ground (pins 1, 11 and 24); VDDD = VDDA = VDDO = 3 V; Tamb = 25 °C, RL = 32 Ω (note 1); common operational amplifier application; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDDD digital supply voltage pin 10 note 2 2.7 3.0 4.0 V VDDA analog supply voltage pin 23 note 2 2.7 3.0 4.0 V VDDO opamp supply voltage pin 28 note 2 2.7 3.0 4.0 V IDDD digital supply current at digital silence − 4.5 − mA IDDA analog supply current at digital silence − 4.5 − mA IDDO opamp supply current at digital silence; note 3 − 6.0 − mA Ptot total power dissipation note 3 − 50 − mW Digital inputs VIH HIGH level input voltage on pins 5 to 9 and 12 to 17 0.7VDDD − − V VIL LOW level input voltage on pins 5 to 9 and 12 to 17 − − 0.3VDDD V |ILI| input leakage current on pins 7 to 9 and 12 to 17 − − 10 µA CI input capacitance on pins 5 to 9 and 12 to 17 − − 10 pF − − 6 bit Analog inputs pins ADVC, ADBB, ADTR and AD3S RES input resolution CI input capacitance RI input resistance − 10 − pF pins ADBB, ADTR and ADVC 1 − − MΩ pin AD3S − 20 − kΩ Analog reference pin ADref VADref reference voltage pin 18 0.45VDDA 0.5VDDA 0.55VDDA V RL(ADref) reference output load pin 18 3.0 − − kΩ Analog audio pins Vref reference voltage pin 25 0.45VDDA 0.5VDDA 0.55VDDA V RO output resistance pin 25 with respect to VSSO − 3 − kΩ RCONV current-to-voltage conversion resistor − 1.2 − kΩ IO(max) maximum output current (THD + N)/S < 0.1% − 35 − mA CL output load capacitance note 4 − − 50 pF Notes 1. RL is the AC impedance of the external circuitry connected to the audio outputs of the application circuit. 2. All power supply pins (VDD and VSS) must be connected to the same external power supply unit. 3. No operational amplifier load resistor. 4. Load capacitance greater than 50 pF, an inductor of 22 µH connected in parallel with a resistor of 270 Ω must be inserted between the load and the operational amplifier output. 1995 Nov 15 11 Philips Semiconductors Product specification Bitstream continuous calibration filter-DAC with headphone driver and DSP TDA1548T AC CHARACTERISTICS (ANALOG) All voltages referenced to ground (pins 2, 9 and 23); VDDD = VDDA = VDDO = 3 V; fi = 1 kHz; Tamb = 25 °C, RL = 32 Ω (note 1); common operational amplifier application; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT RES input resolution − − 18 bit fsAD AD sample frequency − fs/32 − kHz VADref input voltage range 0 − VADref V VFS(rms) output voltage swing (RMS value) (pins 3 and 27) 0.57 0.64 0.71 V VDC(os) DC offset output voltage w.r.t. reference voltage level Vref − 20 − mV TCFS full scale temperature coefficient − ±100 × 10−6 − SVRR supply voltage ripple rejection VDDA and VDDO C25 = 10 µF; fripple = 1 kHz; Vripple = 100 mV (peak) − 40 − dB UNBAL unbalance between the 2 DAC voltage outputs (pins 3 and 27) maximum volume − 0.1 − dB αct crosstalk between the 2 DAC voltage outputs (pins 3 and 27) one output digital silence the − other maximum volume 50 − dB one output digital silence the − other maximum volume RL = 5 kΩ 90 − dB crosstalk between the 2 DAC voltage outputs (pins 3 and 27) with RL connected to ground one output digital silence the − other maximum volume 70 − dB one output digital silence the − other maximum volume RL = 5 kΩ 100 − dB total harmonic distortion plus noise as a function of signal 0 dB signal − −65 −60 dB − 0.056 0.1 % 0 dB signal; RL = 5 kΩ − −85 −78 dB − 0.006 0.013 % −60 dB signal; RL = 32 Ω or RL = 5 kΩ − −35 −30 dBA − 1.778 3.162 % A-weighted at code 00000H 90 95 − dBA (THD+N)/S S/N signal-to-noise ratio at bipolar zero Note 1. RL is the AC impedance of the external circuitry connected to the audio outputs of the application circuit. 1995 Nov 15 12 Philips Semiconductors Product specification Bitstream continuous calibration filter-DAC with headphone driver and DSP TDA1548T AC CHARACTERISTICS (DIGITAL) All voltages referenced to ground (pins 2, 9 and 23); VDDD = VDDA = VDDO = 2.7 to 4.0 V; Tamb = +70 °C, RL = 32 Ω (note 1); unless otherwise specified. SYMBOL Tcy PARAMETER CONDITIONS clock cycle MIN. TYP. MAX. UNIT fsys = 384fs 54.2 59.1 81.3 ns fsys = 256fs 81.3 88.6 122 ns fsys = 64fs 325.5 354.3 488.3 ns tCW(L) fsys LOW level pulse width 22 − − ns tCW(H) fsys HIGH level pulse width 22 − − ns Serial input data timing (see Fig.3) BR clock input = data input rate fsys = 384fs − 48fs − fsys = 256fs − 64fs − fsys = 64fs − 64fs − fsys system clock frequency 2.048 − 18.432 MHz fWS word select input frequency − 44.1 48.0 kHz tr rise time − − 20 ns tf fall time − − 20 ns tBCK(H) bit clock HIGH time 55 − − ns tBCK(L) bit clock LOW time 55 − − ns ts;DAT data set-up time 20 − − ns th;DAT data hold time 10 − − ns ts;WS word select set-up time 20 − − ns th;WS word select hold time 10 − − ns LEFT handbook, full pagewidth WS RIGHT th;WS tBCK(H) ts;WS t BCK(L) BCK tr DATA tr Tcy ts;DAT t h;DAT LSB MSB MGC670 SAMPLE OUT Fig.3 Timing of input signals. 1995 Nov 15 13 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2 RIGHT >=8 3 1 2 3 MSB B2 >=8 DATA MSB B2 MSB INPUT FORMAT I2 S WS RIGHT LEFT 16 15 2 1 16 B15 LSB MSB 15 2 1 BCK DATA MSB B2 B2 B15 LSB LSB JUSTIFIED FORMAT 16 BITS LEFT 18 BCK RIGHT 17 16 15 2 1 18 B17 LSB MSB 17 16 15 2 1 DATA MSB B2 B3 B4 B2 B3 B4 B17 LSB LSB JUSTIFIED FORMAT 18 BITS WS BCK 20 19 LEFT 18 RIGHT 17 16 15 2 1 20 B19 LSB MSB 19 18 17 16 15 2 1 DATA MSB B2 B3 B4 B5 B6 LSB JUSTIFIED FORMAT 20 BITS B3 B4 B5 B6 B19 LSB MGC671 Product specification Fig.4 Data input formats. B2 TDA1548T handbook, full pagewidth 14 WS Philips Semiconductors LEFT BCK 1 Bitstream continuous calibration filter-DAC with headphone driver and DSP 1995 Nov 15 WS Philips Semiconductors Product specification Bitstream continuous calibration filter-DAC with headphone driver and DSP TDA1548T TEST AND APPLICATION INFORMATION Filter characteristics Table 5 Digital filter characteristics (fs = 44.1 kHz) The band frequencies scale with the sample frequency. BAND ATTENUATION 0 to 20 kHz < 0.001 dB 24 to 64 kHz > 39 dB 64 to 69 kHz > 33 dB 69 to 88 kHz > 37 dB +3 V handbook, full pagewidth 100 µF 100 µF 100 nF 100 nF 100 nF (1) L3 (2) VSSD VDDD VSSA VDDA VSSO VDDO 11 SYSTEM CLOCK INPUT SYSCLK I S-BUS OR LSB-JUSTIFIED SERIAL INPUT DATA 23 1 28 12 25 WS DATA MODE0 MODE1 IF1 IF2 DEEM MUTE CLSEL 4.7 µF 7 100 Ω 8 9 26 +3 V Vref 100 nF BCK 2 24 10 5 27 TDA1548T 6 2 13 14 3 1 nF 22 µH L1(1) VOL 1 nF 4 17 330 Ω L2(1) VCOM 15 16 RIGHT R2(1) FILTCR VOR 47 µF FILTCL 22 µH R1(1) 330 Ω 100 Ω 47 µF LEFT FLAT 10 kΩ MID AD3S 22 MAX 18 19 ADref 20 ADTR 1 kΩ 21 ADBB C(1) 2 kΩ 5 kΩ 6 kΩ 5 kΩ 1 kΩ ADVC C(1) 1 kΩ C(1) 10 kΩ MGB709 (1) Optional. (2) Chip inductor BLM32A07. Fig.5 Application diagram. 1995 Nov 15 15 Philips Semiconductors Product specification Bitstream continuous calibration filter-DAC with headphone driver and DSP TDA1548T PACKAGE OUTLINES SO28: plastic small outline package; 28 leads; body width 7.5 mm SOT136-1 D E A X c y HE v M A Z 15 28 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 14 e bp 0 detail X w M 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.30 0.10 2.45 2.25 0.25 0.49 0.36 0.32 0.23 18.1 17.7 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.9 0.4 inches 0.10 0.012 0.096 0.004 0.089 0.01 0.019 0.013 0.014 0.009 0.71 0.69 0.30 0.29 0.050 0.419 0.043 0.055 0.394 0.016 0.043 0.039 0.01 0.01 0.004 0.035 0.016 Z (1) θ 8o 0o Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT136-1 075E06 MS-013AE 1995 Nov 15 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-01-24 97-05-22 16 Philips Semiconductors Product specification Bitstream continuous calibration filter-DAC with headphone driver and DSP TDA1548T SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm D SOT341-1 E A X c HE y v M A Z 28 15 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 14 bp e detail X w M 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2.0 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 10.4 10.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.1 0.7 8 0o Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT341-1 1995 Nov 15 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 93-09-08 95-02-04 MO-150AH 17 o Philips Semiconductors Product specification Bitstream continuous calibration filter-DAC with headphone driver and DSP TDA1548T SOLDERING SSOP Introduction Wave soldering is not recommended for SSOP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. If wave soldering cannot be avoided, the following conditions must be observed: • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). • The longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. Reflow soldering Even with these conditions, only consider wave soldering SSOP packages that have a body width of 4.4 mm, that is SSOP16 (SOT369-1) or SSOP20 (SOT266-1). Reflow soldering techniques are suitable for all SO and SSOP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. METHOD (SO AND SSOP) During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Wave soldering SO Repairing soldered joints Wave soldering techniques can be used for all SO packages if the following conditions are observed: Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. • The longitudinal axis of the package footprint must be parallel to the solder flow. • The package footprint must incorporate solder thieves at the downstream end. 1995 Nov 15 18 Philips Semiconductors Product specification Bitstream continuous calibration filter-DAC with headphone driver and DSP TDA1548T DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1995 Nov 15 19 Philips Semiconductors – a worldwide company Argentina: IEROD, Av. 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