INTEGRATED CIRCUITS
DATA SHEET
SAA7366
Bitstream conversion ADC for
digital audio systems
Preliminary specification
File under Integrated Circuits, IC01
Philips Semiconductors
May 1994
Philips Semiconductors
Preliminary specification
Bitstream conversion ADC for
digital audio systems
SAA7366
FEATURES
• Integrated buffers for simple interfacing to analog inputs
• 4 flexible serial interface modes
• Overload detection of digital signal ≥−1 dB amplitude
• Selectable high-pass filter
• 18-bit serial output
• 3.4 to 5.5 V operation of digital part
• Standby mode
APPLICATIONS
• SO24 package
The device is designed for digital acquisition of analog
audio signals for digital audio systems such as:
• Small non-critical PCB layout.
• CD-recordable
GENERAL DESCRIPTION
• Digital Compact Cassette (DCC)
The SAA7366 is a CMOS cost effective stereo
analog-to-digital converter (ADC) using the Philips
bitstream conversion technique.
• Digital Audio Tape (DAT).
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
VDDD
digital supply voltage
3.4
5.0
5.5
V
VDDA
analog supply voltage
4.5
5.0
5.5
V
fi
clock input frequency
4.608
12.288
13.568
MHz
THD + N
total harmonic distortion + noise
−
−
−80
dB
DR
dynamic range
90
−
−
dB
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
SAA7366T(1)
PINS
PIN POSITION
MATERIAL
CODE
24
SO24L
plastic
SOT137A
Note
1. Plastic small outline package; 24 leads; body width 7.5 mm; (SOT137A); SOT137-1; 1996 Oct 29.
May 1994
2
Philips Semiconductors
Preliminary specification
Bitstream conversion ADC for
digital audio systems
SAA7366
BLOCK DIAGRAM
VSSA
VREFR
TEST2
15
12
13
operational
amplifier
10 k Ω
BIR
BOR
10 k Ω
3 kΩ
1 pF
STD
10
2
operational
amplifier
16
17
TEST1
REFERENCE
VOLTAGE
GENERATOR
CLOCK
GENERATION
AND
CONTROL
3 kΩ
4
6
VDACN
I REF
VDACP
BOL
BIL
18
5
SIGMADELTA
MODULATOR
14
REFERENCE
CURRENT
GENERATOR
DECIMATION FILTER
TIMING
GENERATOR
SIGMADELTA
MODULATOR
19
3
VSSD
V DDD
OVLD
SAA7366
3 kΩ
20
21
1 pF
10 k Ω
operational
amplifier
HIGH-PASS
FILTER
3 kΩ
10 k Ω
REFERENCE
VOLTAGE
GENERATOR
7
SERIAL OUTPUT
INTERFACE
operational
amplifier
23
22
11
24
VDDA
VREFL
HPEN
SLAVE
Fig.1 Block diagram.
May 1994
STAGE 2
STAGE 1
3 HALF-BAND
COMB
FILTERS
FILTER
CKIN
3
8
9
SDO
SWS
SCK
1
SFOR
MGA911
Philips Semiconductors
Preliminary specification
Bitstream conversion ADC for
digital audio systems
SAA7366
PINNING
SYMBOL
PIN
DESCRIPTION
SFOR
1
Serial interface output format select. Output format is selected as follows: SFOR
HIGH = Format 1; SFOR LOW = Format 2.
STD
2
Standby mode input (active LOW).
OVLD
3
Overload indication output. This pin indicates whether the internal digital signal is within 1 dB
of maximum. In standby mode this output is high impedance.
CKIN
4
System clock input.
VDDD
5
Supply for the digital section (3.4 to 5.5 V).
VSSD
6
Ground supply for the digital section.
SDO
7
Serial interface data output. In standby mode this output is high impedance.
SWS
8
Serial interface word select signal. In master mode this pin outputs the serial interface word
select signal. In slave mode this pin is the word select input to the serial interface. In standby
mode this pin is always an input (high impedance).
SCK
9
Serial interface clock. In master mode this pin outputs the serial interface bit clock. In slave
mode this pin is the input for the external bit clock. In standby mode this output is
high impedance.
TEST1
10
Test input 1. This pin should be left open-circuit.
HPEN
11
High-pass filter enable input. (HPEN HIGH = enabled). If unconnected this pin defaults HIGH.
TEST2
12
Test input 2. This pin should be left open-circuit.
VSSA
13
Ground supply for the analog section.
IREF
14
Current reference output node.
VREFR
15
1⁄
BIR
16
Buffer operational amplifier inverting input for right channel.
BOR
17
Buffer operational amplifier output for right channel.
VDACN
18
Negative 1-bit DAC reference voltage input, connected to 0 V.
VDACP
19
Positive 1-bit DAC reference voltage input, connected to +5 V.
BOL
20
Buffer operational amplifier output for left channel.
BIL
21
Buffer operational amplifier inverting input for left channel.
VREFL
22
1⁄
VDDA
23
Supply for the analog section.
SLAVE
24
Serial interface operating output mode master/slave select as follows: HIGH = slave mode;
LOW = master mode. If unconnected the pin will default LOW.
May 1994
2VDDA
2VDDA
reference generator output for the right channel analog section.
reference generator output for the left channel analog section.
4
Philips Semiconductors
Preliminary specification
Bitstream conversion ADC for
digital audio systems
SFOR
1
24
SLAVE
STD
2
23
VDDA
OVLD
3
22
VREFL
CKIN
4
21
BIL
V DDD
5
20
BOL
VSSD
6
19
V DACP
SDO
7
18
VDACN
SWS
8
17
BOR
SCK
9
16
BIR
TEST1 10
15
VREFR
HPEN 11
14
I REF
TEST2 12
13
VSSA
SAA7366
SAA7366
respectively. By the choice of feedback component values,
the application signal amplitude can be matched to the
requirements of the ADC. Typically the operational
amplifiers are configured as low-pass filters with a gain
of 1 and a pole at approximately 5fs.
Remark: The complete ADC is non-inverting. Hence a
positive DC input (referenced to Vref) will yield a positive
digital output.
Input level
The overall system gain is proportional VDDA, or more
accurately {V(VDACP) − V(VDACN)}. For convenience the
ADC input signal amplitude is defined as that amplitude
seen on BOL or BOR, the operational amplifier outputs
(i.e. the input to the Sigma-Delta modulator). Also, the
0 dB input level is defined as that which provides a −1 dB
(actually −1.08 dB) digital output, relative to full-scale
swing. This offset provides headroom to accommodate
small random DC offsets without causing the digital output
to clip.
MGA912
Fig.2 Pin configuration.
Hence:
V ( V DACP ) – V ( V DACN )
V I ( 0 dB ) = --------------------------------------------------------------- = V (RMS)
5
The user of the IC should ensure, that when all sources of
signal amplitude variation are taken into account, the
maximum input signal should conform to the 0 dB level. If
not, clipping may occur. In the event that the maximum
signal level cannot be pre-determined, e.g. a live
microphone input, the average signal level should be set
at −10 to −20 dB down. The exact value will depend on the
application and the balance between head room and
operating signal-to-noise ratio.
FUNCTIONAL DESCRIPTION
General
The SAA7366 is a bitstream conversion CMOS ADC for
digital audio systems. The conversion is achieved using a
third order Sigma-Delta modulator (SDM), operating at
128 times the output sample frequency (fs). The high
oversampling ratio greatly simplifies the design of the
analog input anti-alias filter. In most cases the internal
buffer operational amplifier, configured as a low-pass filter
will suffice. The 1-bit code from the Sigma-Delta modulator
is filtered and down-sampled (decimated) to 1fs in two
stages of filtering. An optional high-pass filter is provided
to remove DC, if required. The device has been designed
with ease of use, low board area and low application costs
in mind.
Behaviour during overload
As defined earlier the maximum input level for normal
operation is 0 dB. If the input level exceeds this value
clipping may occur. Infringements are limited to the
maximum permitted positive or negative values, 217 − 1 or
−217 respectively. If the high-pass filter has been enabled
the clipped output samples may have non-maximum
values due to the removal of the DC content. Input signals
in the range of 0 to 1 dB may or may not be clipped
depending on the values of DC dither and small random
offsets in the analog circuitry.
Clock frequency
The external clock, input on pin CKIN, operates at
256 times fs, which can range from 18 kHz to 53 kHz.
Input buffer
When using the recommended application circuitry,
clipping will initially be observed on negative peaks due to
the use of negative DC dither.
Two input buffers are provided, one for each channel, for
signal amplitude matching, signal buffering and anti-alias
filter purposes. These are configured for inverting use.
Access is provided by pins BIL, BIR (inverting inputs) and
BOL, BOR (outputs) for left and right channels
May 1994
The maximum level of overload that can be safely
tolerated is application circuit dependent. In the case of the
5
Philips Semiconductors
Preliminary specification
Bitstream conversion ADC for
digital audio systems
SAA7366
recommended circuit the following applies: the inverting
operational amplifier inputs BIL/BIR are protected from
excessive voltages (currents) by diodes to VDDA and VSSA.
These have absolute maximum ratings of IIK = ±20 mA,
with a safe practical limit of ±2 mA. Given the input resistor
of 10 kΩ, ±2 mA diode current and the operation of the
operational amplifier a maximum signal (applied to the
input resistor) of ±30 V can be handled safely. This level
represents an overload of 26 dB.
Table 2 High-pass filter characteristics.
ITEM
During overload the in-band portion of the waveform will be
correctly converted. The out-of-band portion will be limited
as detailed above.
VALUE
(dB)
Pass band ripple
none
Pass band gain
0
Droop
at 0.00045fs
Attenuation at DC
at 0.00000036fs
>40
Dynamic range
0 to 0.45fs
116
0.029
Serial interface
The serial interface provides 2 formats in both master and
slave modes (see Figs 3 and 4). In both modes the
interface provides up to 18 significant bits of output data
per channel.
Sigma-Delta modulator
The SAA7366 has two third order Sigma-Delta modulators
with a quantization noise floor of approximately −104 dB.
The scaling of the feedback has been optimized for stable
operation even during overload. Thus with a maximum
signal swing of 0 V to VDDA on the input the digital output
remains well behaved, i.e. it does not burst into random
oscillation. During overload the output is simply a clipped
version of the input. The gain of this stage is −4.95 dB.
During standby mode (STD = LOW) all interface pins are
in their high-impedance state. On recovery from standby
the serial data output SDO is held LOW until valid data is
available from the decimation filter. This time depends on
whether the high-pass filter is selected or not as follows:
HPEN = 0; T = 1024/fs, T = 21.3 ms when fs = 48 kHz
Decimation filter
HPEN = 1; T = 8192/fs, T = 170.6 ms when fs = 48 kHz
Decimation from 128fs is performed in two stages. The first
stage is a comb filter, which decimates from 128 to 8fs.
The second stage, consists of 3 half-band filters, each
decimating by a factor of 2.
Overload Detection Indication (OVLD)
The OVLD output is used to indicate whenever the data, in
either the left or right channel, is within 1 dB of the
maximum possible digital swing. When this condition is
detected the OVLD output is forced HIGH for at least 512fs
cycles (10.6 ms at fs = 48 kHz). This time-out is reset for
each infringement.
The overall characteristics are given in Table 1.
Table 1 Overall filter characteristics.
ITEM
CONDITION
VALUE
(dB)
Pass band ripple 0 to 0.45fs Hz
±0.1
0.45 to 0.47fs
−0.5
Stop band
>0.55fs
−60
Dynamic range
0 to 0.42fs
110
Gain
DC
3.87
Standby mode (STD)
The STD pin activates a power saving mode when the
device function is not required. This pin can also be used
as a chip enable, as follows.
On a HIGH-to-LOW transition, of the STD pin, the internal
control circuitry starts a timed power-down sequence. This
takes approximately 32 system clock cycles to complete.
Transitions on STD which are shorter than 32 clock cycles
have an indeterminate effect. However, the device will
always recover correctly.
High-pass filter
An optional high-pass filter is provided to remove
unwanted DC components. The operation is selected
when HPEN is HIGH. The filter has the characteristics
given in Table 2.
May 1994
CONDITION
6
Philips Semiconductors
Preliminary specification
Bitstream conversion ADC for
digital audio systems
SAA7366
During standby the following occurs:
On a LOW-to-HIGH transition the device reverts back to its
normal function. This process takes approximately 32
system clock cycles. Before SDO is enabled the output
data is forced LOW. SDO remains LOW until good data is
available from the decimation filter.
• The internal logic clock is disabled
• The serial interface pins are forced to high impedance
• The OVLD output is forced LOW
• The analog circuitry is disabled
The STD pin has a Schmitt-trigger input. A simple
power-on reset function can be effected using an external
capacitor to VSSD and resistor to VDDD.
• The nominal external analog node voltages are
maintained by a low-power circuit. This feature ensures
a fast recovery from standby mode.
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDDA
analog supply voltage
−0.5
+6.5
V
VI
DC input voltage
−0.5
+6.5
V
IIK
DC input diode current
−
±20
mA
note 1
VO
DC output voltage
−0.5
VDD + 0.5
V
IO
DC output source or sink current
−
±20
mA
IDDtot
total DC supply current
−
±0.5
A
ISStot
total DC supply current
−
±0.5
A
Tamb
operating ambient temperature
−40
+85
°C
Tstg
storage temperature
−65
+150
°C
Ves1
electrostatic handling
note 2
−2000
+2000
V
Ves2
electrostatic handling
note 3
−200
+200
V
Notes
1. VSSD and VSSA pins must be externally connected to a common potential.
2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor with a rise time of 15 ns.
3. Equivalent to discharging a 200 pF capacitor via a 2.5 µH series inductor.
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
CHARACTERISTICS
VDDD = 3.4 to 5.5 V; VDDA = 4.5 to 5.5 V; Tamb = −40 to +85 °C; fs = 18 to 53 kHz; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VDDA
analog supply voltage
IDDA
analog supply current
VDDD
digital supply voltage
IDDD
Ptot
May 1994
4.5
5.0
5.5
V
fs = 48 kHz
−
13
−
mA
3.4
5.0
5.5
V
digital supply current
fs = 48 kHz
−
56
−
mA
total power consumption
fs = 48 kHz
−
345
−
mW
7
Philips Semiconductors
Preliminary specification
Bitstream conversion ADC for
digital audio systems
SYMBOL
PARAMETER
SAA7366
CONDITIONS
MIN.
TYP.
MAX.
UNIT
ISTD
standby supply current
−
65
−
µA
PSTD
standby power consumption
−
325
−
µW
Digital part: inputs
SFOR, SLAVE AND HPEN
VIL
LOW level input voltage
note 1
−0.5
−
+0.8
V
VIH
HIGH level input voltage
note 1
2.0
−
VDDD + 0.5
V
ILI
input leakage current
note 2
−10
−
+10
µA
CI
input capacitance
−
−
10
pF
VIL
LOW level input voltage
−0.5
−
+0.3VDDD
V
VIH
HIGH level input voltage
0.7VDDD
−
VDDD + 0.5
V
ILI
input leakage current
−10
−
+10
µA
CI
input capacitance
−
−
10
pF
−0.5
−
+0.4VDDD
V
CLKIN
note 2
STD (SCHMITT-TRIGGER)
VIL
LOW level input voltage
note 1
note 1
VIH
HIGH level input voltage
∆VI
input hysteresis
ILI
input leakage current
CI
input capacitance
note 2
2.4
−
VDDD + 0.5
V
−
600
−
mV
−10
−
+10
µA
−
−
10
pF
Digital part: Input/Outputs
SWS AND SCK
VIL
LOW level input voltage
note 1
−0.5
−
+0.8
V
VIH
HIGH level input voltage
note 1
2.0
−
VDDD + 0.5
V
ILI
leakage current in 3-state
note 2
−10
−
+10
µA
CI
input capacitance
−
−
10
pF
VOL
LOW level output voltage
IO = −400 µA;
note 1
−
−
0.4
V
VOH
HIGH level output voltage
IO = 20 µA;
note 1
2.4
−
−
V
CL
output load capacitance
−
−
50
pF
Digital part: Outputs
OVLD
VOL
LOW level output voltage
IO = −400 µA;
note 1
−
−
0.4
V
VOH
HIGH level output voltage
IO = 20 µA;
note 1
2.4
−
−
V
CL
output load capacitance
−
−
50
pF
May 1994
8
Philips Semiconductors
Preliminary specification
Bitstream conversion ADC for
digital audio systems
SYMBOL
PARAMETER
SAA7366
CONDITIONS
MIN.
TYP.
MAX.
UNIT
SDO
VOL
LOW level output voltage
IO = −400 µA;
note 1
−
−
0.4
V
VOH
HIGH level output voltage
IO = 20 µA;
note 1
2.4
−
−
V
ILI
leakage current in 3-state
note 2
−10
−
+10
µA
CL
output load capacitance
−
−
50
pF
Digital part: timing
CKIN
tr
clock input rise time
−
−
10
ns
tf
clock input fall time
−
−
10
ns
fi
clock input frequency
note 3
4.608
12.288
13.568
MHz
msr
mark-to-space ratio
fs > 32 kHz
40
−
60
%
fs ≤ 32 kHz
30
−
70
%
50
ns
ns
Serial interface master and slave modes (see Figs 5, 6 and 7)
SCK
tr
clock rise time
note 4
−
−
tf
clock fall time
note 4
−
−
50
tL
clock LOW time
T = 1/64fs
0.40T
−
0.60T
tH
clock HIGH time
T = 1/64fs
0.40T
−
0.60T
fclk
clock frequency
master mode
64fs
64fs
64fs
slave mode
−
−
64fs
burst clock idle time
slave mode;
T = 1/fs
0
−
0.05T
tr
word select rise time
note 4
−
−
50
ns
tf
word select fall time
note 4
−
−
50
ns
twL
word select LOW time
T = 1/fs
0.45T
0.50T
0.55T
twH
word select HIGH time
T = 1/fs
0.45T
0.50T
0.55T
fwc
word select frequency
1fs
1fs
1fs
tidle
SWS
td
word select delay from SCK
master mode
−50
−
+50
ns
td
word select delay from SCK
slave mode
50
−
−
ns
tsu
word select set-up time to SCK slave mode
150
−
−
ns
th
data output hold time
100
−
−
ns
tsu
data output set-up time
100
−
−
ns
tr
data output rise time
note 4
−
−
50
ns
tf
data output fall time
note 4
−
−
50
ns
SDO
May 1994
9
Philips Semiconductors
Preliminary specification
Bitstream conversion ADC for
digital audio systems
SYMBOL
PARAMETER
SAA7366
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Analog part (VDDD = VDDA = 5 V; Tamb = 25 °C; fs = 48 kHz)
VOLTAGE REFERENCE: VREFL AND VREFR
VO
output voltage
0.475VDDA
0.5VDDA
0.525VDDA
V
Zn
DC impedance
normal mode
−
750
−
Ω
Zs
DC impedance
standby mode
−
100
−
kΩ
−
0.5VDDA
−
V
−
76
−
µA
input voltage
−
VSSA
−
V
input voltage
−
VDDA
−
V
−
< ±10
−
mV
decoupled to
VREF
−
10
−
kΩ
−
100
−
Ω
f = 0 to 20 kHz
−
−85
−
dB
CURRENT REFERENCE: IREF
VO
output voltage
IO
output current
R = 33 kΩ
DAC REFERENCE: VDACN
VI
VDACP
VI
BUFFER OPERATIONAL AMPLIFIERS: BIL, BOL, BIR AND BOR
Voffset
input offset voltage
RLmax
maximum load resistance;
(drive capability)
ZO
output impedance
THD + N
total harmonic distortion plus
noise
ADC PERFORMANCE; NOTE 5
tgd
group delay
T = 1/fs
tbf
−
tbf
µs
αsb
stop band attenuation
f > 0.546fs
60
−
−
dB
DR
dynamic range
note 6
90
−
−
dB
THD + N
total harmonic distortion plus
noise
note 7
−
−
−80
dB
S/N
signal-to-noise ratio
A-weighted
−
tbf
−
dB
αcs
channel separation
note 8
−
tbf
−
dB
G
gain
note 9
−1.2
−1
−0.8
dB
Notes
1. Minimum VIL, VOL and maximum VIH, VOH are peak values to allow for transients.
2. ILImin and ILOmin measured at VI = 0 V; ILImax and ILOmax measured at VI = VDDD.
3. fi is a multiple (×256) of the system sampling frequency (fs) which can vary between 18 kHz and 53 kHz.
4. CL = 50 pF (valid for master mode only).
5. Device measured with external components shown in recommended application diagram Fig.8.
6. Input is 1 kHz and −60 dB.
7. Input is 1 kHz and 0 dB.
8. Measured by applying a 1 kHz, 0 dB signal to one channel and monitoring the level of 1 kHz (fundamental) on the
other channel.
9. See also Section “Input level” of Chapter “Functional description”; valid for left or right channel.
May 1994
10
SWS
May 1994
11
SDO
SCK
FORMAT 1
FORMAT 2
MSB
18 CLOCKS
MSB
18 CLOCKS
LSB
14 CLOCKS
RIGHT DATA
RIGHT DATA
MSB
MGA914
Bitstream conversion ADC for
digital audio systems
Fig.3 Serial interface master mode format.
LSB
14 CLOCKS
LEFT DATA
LEFT DATA
1 STEREO WORD
Philips Semiconductors
Preliminary specification
SAA7366
May 1994
12
idle
MSB
idle
MSB
LSB
LSB
idle
n CLOCKS
RIGHT DATA
n CLOCKS
MSB
MSB
1 STEREO WORD
idle
RIGHT DATA
Fig.4 Serial interface slave mode formats.
n CLOCKS
LEFT DATA
n CLOCKS
LEFT DATA
LSB
LSB
MGA915
MSB
MSB
Bitstream conversion ADC for
digital audio systems
1 < n < 33.
Up to 18 significant bits are available.
SDO
SCK
SWS
FORMAT 1
SDO
SCK
SWS
FORMAT 2
1 STEREO WORD
Philips Semiconductors
Preliminary specification
SAA7366
Philips Semiconductors
Preliminary specification
Bitstream conversion ADC for
digital audio systems
tr
tf
SAA7366
tL
tH
timing reference
levels
2.0 V
SCK
0.8 V
td
2.0 V
SWS
0.8 V
tr
SDO
t su
th
tf
MSB
FORMAT 1
VALID
2.0 V
MSB
FORMAT 2
t wH
0.8 V
t wL
SWS
MGA916
Fig.5 Serial interface master mode timing.
tr
tf
tL
tH
timing reference
levels
2.0 V
SCK
0.8 V
t su
td
SWS
2.0 V
0.8 V
tr
SDO
VALID
t su
th
tf
MSB
FORMAT 1
2.0 V
MSB
FORMAT 2
t wH
0.8 V
t wL
SWS
MGA917
Fig.6 Serial interface slave mode timing.
May 1994
13
Philips Semiconductors
Preliminary specification
Bitstream conversion ADC for
digital audio systems
SAA7366
SWS
t idle
t idle
SCK
MGA918
Fig.7 Serial interface slave mode burst clock.
May 1994
14
May 1994
47
µF
4.7 Ω
47
µF
47
nF
15
3
4
21
CKIN
BIL
68 pF
10 k Ω
620 k Ω
R dither
10 k Ω
270
Ω
270
Ω
V DACN
4.7 Ω
6
7
SDO
SWS
to serial
interface
receiver
circuit
8
17
BOR
68 pF
10 k Ω
Fig.8 Application circuit.
9
SCK
16
BIR
HPEN
11
VSSA
MGA913
TEST2
12
13
VDDD or VSSD
TEST1
10
15
22 nF
33 k Ω
47
µF
I REF
14
47
nF
VREFR
(1)
right channel input
Bitstream conversion ADC for
digital audio systems
(1) These capacitors should preferably be surface mounted components located as close as possible to the device pins.
VSSD
SAA7366
18
(1)
VDACP
19
(1)
47 µF
47 nF
VDDD
5V
5
20
BOL
47 nF
47 µF
330 k Ω
R dither
10 k Ω
47 µF
47 µF
5V
100 k Ω
100 k Ω
system
clock
input
OVLD
to microcontroller
overload detection
from microcontroller
power-down control
VDDD or VSSD
STD
2
1
SFOR
23
24
VREFL
22
(1)
VDDA
(1)
47
nF
left channel input
SLAVE
VDDD or VSSD
5V
handbook, full pagewidth
Philips Semiconductors
Preliminary specification
SAA7366
APPLICATION INFORMATION
Philips Semiconductors
Preliminary specification
Bitstream conversion ADC for
digital audio systems
SAA7366
PACKAGE OUTLINE
handbook, full pagewidth
15.6
15.2
7.6
7.4
10.65
10.00
0.1 S
S
A
0.9 (4x)
0.4
24
13
2.45
2.25
1.1
1.0
0.3
0.1
2.65
2.35
0.32
0.23
pin 1
index
1
1.1
0.5
12
detail A
1.27
0.49
0.36
0.25 M
(24x)
Dimensions in mm.
Fig.9 Plastic SOL, 24-pin (SO24L; SOT137A).
May 1994
16
0 to 8o
MBC235 - 1
Philips Semiconductors
Preliminary specification
Bitstream conversion ADC for
digital audio systems
SAA7366
applied to the substrate by screen printing, stencilling or
pressure-syringe dispensing before device placement.
SOLDERING
Plastic small-outline packages
Several techniques exist for reflowing; for example,
thermal conduction by heated belt, infrared, and
vapour-phase reflow. Dwell times vary between 50 and
300 s according to method. Typical reflow temperatures
range from 215 to 250 °C.
BY WAVE
During placement and before soldering, the component
must be fixed with a droplet of adhesive. After curing the
adhesive, the component can be soldered. The adhesive
can be applied by screen printing, pin transfer or syringe
dispensing.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 min at 45 °C.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder bath is
10 s, if allowed to cool to less than 150 °C within 6 s.
Typical dwell time is 4 s at 250 °C.
REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING
IRON OR PULSE-HEATED SOLDER TOOL)
Fix the component by first soldering two, diagonally
opposite, end pins. Apply the heating tool to the flat part of
the pin only. Contact time must be limited to 10 s at up to
300 °C. When using proper tools, all other pins can be
soldered in one operation within 2 to 5 s at between 270
and 320 °C. (Pulse-heated soldering is not recommended
for SO packages.)
A modified wave soldering technique is recommended
using two solder waves (dual-wave), in which a turbulent
wave with high upward pressure is followed by a smooth
laminar wave. Using a mildly-activated flux eliminates the
need for removal of corrosive residues in most
applications.
For pulse-heated solder tool (resistance) soldering of VSO
packages, solder is applied to the substrate by dipping or
by an extra thick tin/lead plating before package
placement.
BY SOLDER PASTE REFLOW
Reflow soldering requires the solder paste (a suspension
of fine solder particles, flux and binding agent) to be
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
May 1994
17
Philips Semiconductors
Preliminary specification
Bitstream conversion ADC for
digital audio systems
SAA7366
NOTES
May 1994
18
Philips Semiconductors
Preliminary specification
Bitstream conversion ADC for
digital audio systems
SAA7366
NOTES
May 1994
19
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SCD31
© Philips Electronics N.V. 1994
All rights are reserved. Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation
or contract, is believed to be accurate and reliable and may be changed without
notice. No liability will be accepted by the publisher for any consequence of its
use. Publication thereof does not convey nor imply any license under patent- or
other industrial or intellectual property rights.
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513061/1500/01/pp20
Document order number:
Date of release: May 1994
9397 731 80011