INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC58 Dual AND-OR gate Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification Dual AND-OR gate 74HC58 FEATURES • Output capability: standard • ICC category: SSI GENERAL DESCRIPTION The 74HC58 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The “58” provides two sections of AND-OR gates. One section contains a 2-wide, 3-input (1A to 1F) AND-OR gate and the second section contains a 2-wide, 2-input (2A to 2D) AND-OR gate. QUICK REFERENCE DATA GND = 0 V; Tamb = 15 °C; tr = tf = 6 ns SYMBOL PARAMETER CONDITIONS TYPICAL UNIT HC tPHL/ tPLH propagation delay CL = 15 pF; VCC = 5 V 1n to 1Y 11 2n to 2Y CI input capacitance CPD power dissipation capacitance per gate notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in V ∑ (CL × VCC2 × fo) = sum of outputs 2. For HC the condition is VI = GND to VCC ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. December 1990 2 ns 9 ns 3.5 pF 18 pF Philips Semiconductors Product specification Dual AND-OR gate 74HC58 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1, 12, 13, 9, 10, 11 1A to 1F data inputs 2, 3, 4, 5 2A to 2D data inputs 8, 6 1Y, 2Y data outputs 7 GND ground (0 V) 14 VCC positive supply voltage Fig.1 Pin configuration. December 1990 Fig.2 Logic symbol. 3 Fig.3 IEC logic symbol. Philips Semiconductors Product specification Dual AND-OR gate 74HC58 Fig.4 Functional diagram. Fig.5 Logic diagram. FUNCTION TABLE (1) INPUTS 1A 1B 1C 1D 1E 1F 2A 1Y L L L X X X X X L L X X X X X L X X L X X L X X L X X L X X L L L L L X X X X X H L X X X X H X L L L X H X L X X H X X X L X H X L X X L H X L L L L H H December 1990 INPUTS OUTPUT L L X X X H 2B X X L L X H 2C L X L X H X Note 1. H = HIGH voltage level L = LOW voltage level X = don’t care 4 OUTPUT 2D X L X L H X 2Y L L L L H H Philips Semiconductors Product specification Dual AND-OR gate 74HC58 DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: SSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER −40 to +85 +25 min. typ. −40 to +125 UNIT VCC WAVEFORMS (V) max. min. max. min. max. tPHL/ tPLH propagation delay 1A,1B,1C,1D,1E, 1F to 1Y 36 13 10 115 23 20 145 29 25 175 35 30 ns 2.0 4.5 6.0 Fig.6 tPHL/ tPLH propagation delay 2A,2B,2C,2D to 2Y 30 11 9 100 20 17 125 25 21 150 30 26 ns 2.0 4.5 6.0 Fig.6 tTHL/ tTLH output transition time 19 7 6 75 15 13 95 19 16 110 22 19 ns 2.0 4.5 6.0 Fig.6 AC WAVEFORMS handbook, full pagewidth nA, nB, nC, nD, 1E, 1F INPUT VM (1) t PHL nY OUTPUT t PLH V M (1) MBA336 (1) HC : VM = 50%; VI = GND to V CC. Fig.6 t THL t TLH Waveforms showing the input (nA, nB, nC, nD, 1E, 1F) to output (nY) propagation delays and the output transition times. PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. December 1990 5