PHILIPS P80C552IBA

INTEGRATED CIRCUITS
80C552/83C552
Single-chip 8-bit microcontroller with
10-bit A/D, capture/compare timer,
high-speed outputs, PWM
Product data
Supersedes data of 1998 Aug 13
2002 Sep 03
Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
80C552/83C552
FEATURES
• 80C51 central processing unit
• 8k × 8 ROM expandable externally to 64 kbytes
• ROM code protection
• An additional 16-bit timer/counter coupled to four capture registers
and three compare registers
•
•
•
•
•
•
DESCRIPTION
The 80C552/83C552 (hereafter generically referred to as 8XC552)
Single-Chip 8-Bit Microcontroller is manufactured in an advanced
CMOS process and is a derivative of the 80C51 microcontroller
family. The 8XC552 has the same instruction set as the 80C51.
Three versions of the derivative exist:
• 83C552—8 kbytes mask programmable ROM
•
•
•
80C552—ROMless version of the 83C552
87C552—8 kbytes EPROM (described in a separate chapter)
The 8XC552 contains a non-volatile 8k × 8 read-only program
memory (83C552), a volatile 256 × 8 read/write data memory, five
8-bit I/O ports, one 8-bit input port, two 16-bit timer/event counters
(identical to the timers of the 80C51), an additional 16-bit timer
coupled to capture and compare latches, a 15-source,
two-priority-level, nested interrupt structure, an 8-input ADC, a dual
DAC pulse width modulated interface, two serial interfaces (UART
and I2C-bus), a “watchdog” timer and on-chip oscillator and timing
circuits. For systems that require extra capability, the 8XC552 can
be expanded using standard TTL compatible memories and logic.
256 × 8 RAM, expandable externally to 64 kbytes
Capable of producing eight synchronized, timed outputs
A 10-bit ADC with eight multiplexed analog inputs
Two 8-bit resolution, pulse width modulation outputs
Five 8-bit I/O ports plus one 8-bit input port shared with analog
inputs
I2C-bus serial I/O port with byte oriented master and slave
functions
Full-duplex UART compatible with the standard 80C51
On-chip watchdog timer
Three speed ranges:
– 3.5 to 16 MHz
– 3.5 to 24 MHz (ROM, ROMless only)
•
Three operating ambient temperature ranges:
– P83C552xBx: 0 °C to +70 °C
– P83C552xFx: –40 °C to +85 °C
(XTAL frequency max. 24 MHz)
– P83C552xHx: –40 °C to +125 °C
(XTAL frequency max. 16 MHz)
In addition, the 8XC552 has two software selectable modes of
power reduction—idle mode and power-down mode. The idle mode
freezes the CPU while allowing the RAM, timers, serial ports, and
interrupt system to continue functioning. The power-down mode
saves the RAM contents but freezes the oscillator, causing all other
chip functions to be inoperative.
LOGIC SYMBOL
XTAL1
XTAL2
EA
ALE
PSEN
AVSS
AVDD
AVref+
AVref–
STADC
PWM0
PWM1
The device also functions as an arithmetic processor having
facilities for both binary and BCD arithmetic plus bit-handling
capabilities. The instruction set consists of over 100 instructions: 49
one-byte, 45 two-byte, and 17 three-byte. With a 16 MHz (24 MHz)
crystal, 58% of the instructions are executed in 0.75 µs (0.5 µs) and
40% in 1.5 µs (1 µs). Multiply and divide instructions require 3 µs
(2 µs).
PORT 0
VSS
VDD
PORT 1
•
•
•
Two standard 16-bit timer/counters
PORT 2
PORT 5
ADC0-7
LOW ORDER
ADDRESS AND
DATA BUS
CT0I
CT1I
CT2I
CT3I
T2
RT2
SCL
SDA
HIGH ORDER
ADDRESS AND
DATA BUS
CMT0
CMT1
RST
EW
PORT 3
PORT 4
CMSR0-5
RxD/DATA
TxD/CLOCK
INT0
INT1
T0
T1
WR
RD
SU01691
2002 Sep 03
2
853-1467 28849
Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
80C552/83C552
PIN CONFIGURATIONS
P5.7/ADC7
1
68
67
66
65
64
63
62
AVDD
P5.6/ADC6
2
P5.5/ADC5
3
P5.4/ADC4
4
P5.3/ADC3
PWM0
5
P5.2/ADC2
PWM1
6
P5.0/ADC0
EW
7
P5.1/ADC1
P4.0/CMSR0
8
STADC
P4.1/CMSR1
9
V DD
P4.2/CMSR2
Plastic Leaded Chip Carrier
61
P4.3/CMSR3 10
60 AVSS
P4.4/CMSR4
11
59 AVREF+
P4.5/CMSR5 12
58 AVREF–
P4.6/CMT0 13
57 P0.0/AD0
P4.7/CMT1 14
56 P0.1/AD1
RST 15
55 P0.2/AD2
P1.0/CT0I 16
54 P0.3/AD3
P1.1/CT1I 17
53 P0.4/AD4
PLASTIC LEADED CHIP CARRIER
P1.2/CT2I 18
52 P0.5/AD5
P1.3/CT3I 19
51 P0.6/AD6
P1.4/T2 20
50 P0.7/AD7
34
35
36
37
38
39
40
41
42
43
P2.3/A11
33
P2.4/A12
32
P2.2/A10
31
P2.1/A09
30
P2.0/A08
29
VSS
28
VSS
27
NC*
44 P2.5/A13
XTAL1
45 P2.6/A14
NC*
P3.1/TxD 25
P3.2/INT0 26
XTAL2
46
NC*
47 PSEN
P3.0/RxD 24
P3.7/RD
P1.7/SDA 23
P3.5/T1
48
P3.6/WR
P1.6/SCL 22
P3.4/T0
49 EA
P3.3/INT1
P1.5/RT2 21
ALE
P2.7/A15
SU00932
* Do not connect.
2002 Sep 03
3
Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
80C552/83C552
73
72
P5.6/ADC6
74
P5.5/ADC5
STADC
IC
75
P5.4/ADC4
PWM0
76
P5.3/ADC3
PWM1
77
P5.2/ADC2
EW
78
P5.1/ADC1
NC*
79
P5.0/ADC0
NC*
80
V DD
P4.0/SMSR0
Plastic Quad Flat Pack
71
70
69
68
67
66
65
P4.1/CMSR1
1
64 P5.7/ADC7
P4.2/CMSR2
2
63 AVDD
NC*
3
62 NC*
P4.3/CMSR3
4
61 AVSS
P4.4/CMSR4
5
60 AVREF+
P4.5/CMSR5
6
59 AVREF–
P4.6/CMT0
7
58 P0.0/AD0
P4.7/CMT1
8
57 P0.1/AD1
RST
9
56 P0.2/AD2
P1.0/CT0I 10
55 P0.3/AD3
11
54 P0.4/AD4
P1.1/CT1I
P1.2/CT2I 12
53 P0.5/AD5
PLASTIC QUAD FLAT PACK
P1.3/CT3I
13
52
P1.4/T2 14
P0.6/AD6
51 P0.7/AD7
P1.5/RT2 15
50
EA
P1.6/SCL 16
49 ALE
P1.7/SDA 17
48 PSEN
P3.0/RxD 18
47 P2.7/A15
P3.1/TxD 19
46 P2.6/A14
P3.2/INT0 20
45 P2.5/A13
NC* 21
44 NC*
NC* 22
43 NC*
P3.3/INT1 23
42 P2.4/A12
PP3.4/T0 24
P3.7/RD
NC*
NC*
NC*
XTAL2
XTAL1
34
35
36
37
38
39
40
P2.2/A10
P3.6/WR
33
P2.1/A09
32
P2.0/A08
31
NC*
30
VSS
29
VSS
28
IC
27
VSS
26
P3.5/T1
41 P2.3/A11
25
SU00931
* Do not connect.
IC = Internally connected (do not use).
2002 Sep 03
4
Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
80C552/83C552
BLOCK DIAGRAM
T0
T1
3
INT0
3
INT1
3
PWM0 PWM1
VDD
3
AVSS
ADC0-7 SDA
AVREF
– +
VSS
AVDD
STADC
5
SCL
1
XTAL1
T0, T1
TWO 16-BIT
TIMER/EVENT
COUNTERS
XTAL2
PROGRAM
MEMORY
8k x 8 ROM
CPU
DATA
MEMORY
256 x 8 RAM
DUAL
PWM
SERIAL
I2C PORT
ADC
EA
ALE
80C51 CORE
EXCLUDING
ROM/RAM
PSEN
3
WR
8-BIT INTERNAL BUS
3
RD
16
0
AD0-7
PARALLEL I/O
PORTS AND
EXTERNAL BUS
2
SERIAL
UART
PORT
A8-15
3
P0
P1
P2
P3
TxD
3
RxD
1
P5
P4
CT0I-CT3I
ALTERNATE FUNCTION OF PORT 0
3
ALTERNATE FUNCTION OF PORT 3
1
ALTERNATE FUNCTION OF PORT 1
4
ALTERNATE FUNCTION OF PORT 4
2
ALTERNATE FUNCTION OF PORT 2
5
ALTERNATE FUNCTION OF PORT 5
0
T2
16-BIT
TIMER/
EVENT
COUNTERS
FOUR
16-BIT
CAPTURE
LATCHES
8-BIT
PORT
1
16
1
T2
RT2
T2
16-BIT
COMPARATORS
wITH
REGISTERS
COMPARATOR
OUTPUT
SELECTION
T3
WATCHDOG
TIMER
4
CMSR0-CMSR5
CMT0, CMT1
RST
EW
SU01692
2002 Sep 03
5
1
Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
80C552/83C552
ORDERING INFORMATION
PHILIPS
PART ORDER NUMBER
PART MARKING
ROMless
DRAWING
NUMBER
TEMPERATURE (°C)
AND PACKAGE
FREQ
((MHz))
ROM1
P80C552EBA
P83C552EBA/xxx
SOT188-2
0 to +70,
Plastic Leaded Chip Carrier
16
P80C552EBB
P83C552EBB/xxx
SOT318-2
0 to +70,
Plastic Quad Flat Pack
16
P80C552EFA
P83C552EFA/xxx
SOT188-2
–40 to +85,
Plastic Leaded Chip Carrier
16
P80C552EFB
P83C552EFB/xxx
SOT318-2
–40 to +85,
Plastic Quad Flat Pack
16
P80C552EHA
P83C552EHA/xxx
SOT188-2
–40 to +125,
Plastic Leaded Chip Carrier
16
P80C552EHB
P83C552EHB/xxx
SOT318-2
–40 to +125,
Plastic Quad Flat Pack
16
P80C552IBA
P83C552IBA/xxx
SOT188-2
0 to +70,
Plastic Leaded Chip Carrier
24
P80C552IBB
P83C552IBB/xxx
SOT318-2
0 to +70,
Plastic Quad Flat Pack
24
P80C552IFA
P83C552IFA/xxx
SOT188-2
–40 to +85,
Plastic Leaded Chip Carrier
24
P80C552IFB
P83C552IFB/xxx
SOT318-2
–40 to +85,
Plastic Quad Flat Pack
24
NOTE:
1. xxx denotes the ROM code number.
2. For EPROM device specification, refer to 87C552 datasheet.
2002 Sep 03
6
Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
80C552/83C552
PIN DESCRIPTION
PIN NO.
MNEMONIC
PLCC
QFP
TYPE
VDD
2
72
I
Digital Power Supply: +5 V power supply pin during normal operation, idle and
power-down mode.
STADC
3
74
I
Start ADC Operation: Input starting analog to digital conversion (ADC operation can also
be started by software). This pin must not float.
PWM0
4
75
O
Pulse Width Modulation: Output 0.
PWM1
5
76
O
Pulse Width Modulation: Output 1.
EW
6
77
I
Enable Watchdog Timer: Enable for T3 watchdog timer and disable power-down mode.
This pin must not float.
P0.0-P0.7
57-50
58-51
I/O
Port 0: Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written
to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed
low-order address and data bus during accesses to external program and data memory. In
this application it uses strong internal pull-ups when emitting 1s.
P1.0-P1.7
16-23
16-21
22-23
16-19
20
21
22
23
10-17
10-15
16-17
10-13
14
15
16
17
I/O
I/O
I/O
I
I
I
I/O
I/O
Port 1: 8-bit I/O port. Alternate functions include:
(P1.0-P1.5): Quasi-bidirectional port pins.
(P1.6, P1.7): Open drain port pins.
CT0I-CT3I (P1.0-P1.3): Capture timer input signals for timer T2.
T2 (P1.4): T2 event input.
RT2 (P1.5): T2 timer reset signal. Rising edge triggered.
SCL (P1.6): Serial port clock line I2C-bus.
SDA (P1.7): Serial port data line I2C-bus.
Port 1 is also used to input the lower order address byte during EPROM programming and
verification. A0 is on P1.0, etc.
P2.0-P2.7
39-46
38-42,
45-47
I/O
Port 2: 8-bit quasi-bidirectional I/O port.
Alternate function: High-order address byte for external memory (A08-A15).
P3.0-P3.7
24-31
18-20,
23-27
18
19
20
23
24
25
26
27
I/O
Port 3: 8-bit quasi-bidirectional I/O port. Alternate functions include:
80, 1-2
4-8
80, 1-2
4-6
7, 8
I/O
Port 4: 8-bit quasi-bidirectional I/O port. Alternate functions include:
O
CMSR0-CMSR5 (P4.0-P4.5): Timer T2 compare and set/reset outputs on a match with
timer T2.
CMT0, CMT1 (P4.6, P4.7): Timer T2 compare and toggle outputs on a match with timer T2.
68-62,
1
71-64,
I
RST
15
9
I/O
Reset: Input to reset the 8XC552. It also provides a reset pulse as output when timer T3
overflows.
XTAL1
35
32
I
Crystal Input 1: Input to the inverting amplifier that forms the oscillator, and input to the
internal clock generator. Receives the external clock signal when an external oscillator is
used.
XTAL2
34
31
O
Crystal Input 2: Output of the inverting amplifier that forms the oscillator. Left open-circuit
when an external clock is used.
24
25
26
27
28
29
30
31
P4.0-P4.7
7-14
7-12
13, 14
P5.0-P5.7
2002 Sep 03
NAME AND FUNCTION
RxD(P3.0): Serial input port.
TxD (P3.1): Serial output port.
INT0 (P3.2): External interrupt.
INT1 (P3.3): External interrupt.
T0 (P3.4): Timer 0 external input.
T1 (P3.5): Timer 1 external input.
WR (P3.6): External data memory write strobe.
RD (P3.7): External data memory read strobe.
O
Port 5: 8-bit input port.
ADC0-ADC7 (P5.0-P5.7): Alternate function: Eight input channels to ADC.
7
Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
80C552/83C552
PIN DESCRIPTION (Continued)
PIN NO.
MNEMONIC
VSS
PLCC
QFP
TYPE
NAME AND FUNCTION
36, 37
34-36
I
Two Digital ground pins.
PSEN
47
48
O
Program Store Enable: Active-low read strobe to external program memory.
ALE
48
49
O
Address Latch Enable: Latches the low byte of the address during accesses to external
memory. It is activated every six oscillator periods. During an external data memory
access, one ALE pulse is skipped. ALE can drive up to eight LS TTL inputs and handles
CMOS inputs without an external pull-up.
EA
49
50
I
External Access: When EA is held at TTL level high, the CPU executes out of the internal
program ROM provided the program counter is less than 8192. When EA is held at TTL
low level, the CPU executes out of external program memory. EA is not allowed to float.
AVREF–
58
59
I
Analog to Digital Conversion Reference Resistor: Low-end.
AVREF+
59
60
I
Analog to Digital Conversion Reference Resistor: High-end.
AVSS
60
61
I
Analog Ground
AVDD
61
63
I
Analog Power Supply
NOTE:
1. To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher or lower than VDD + 0.5 V or VSS – 0.5 V,
respectively.
service routine and continued), or by a hardware reset which starts
the processor in the same manner as a power-on reset.
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier. The pins can be configured for use as an on-chip
oscillator, as shown in the logic symbol, page 2.
POWER-DOWN MODE
In the power-down mode, the oscillator is stopped and the
instruction to invoke power-down is the last instruction executed.
Only the contents of the on-chip RAM are preserved. A hardware
reset is the only way to terminate the power-down mode. The control
bits for the reduced power modes are in the special function register
PCON. Table 1 shows the state of the I/O ports during low current
operating modes.
To drive the device from an external clock source, XTAL1 should be
driven while XTAL2 is left unconnected. There are no requirements
on the duty cycle of the external clock signal, because the input to
the internal clock circuitry is through a divide-by-two flip-flop.
However, minimum and maximum high and low times specified in
the data sheet must be observed.
RESET
A reset is accomplished by holding the RST pin high for at least two
machine cycles (24 oscillator periods), while the oscillator is running.
To insure a good power-on reset, the RST pin must be high long
enough to allow the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At power-on, the voltage on
VDD and RST must come up at the same time for a proper start-up.
ROM CODE PROTECTION (83C552)
The 83C552 has an additional security feature. ROM code
protection may be selected by setting a mask–programmable
security bit (i.e., user dependent). This feature may be requested
during ROM code submission. When selected, the ROM code is
protected and cannot be read out at any time by any test mode or by
any instruction in the external program memory space.
IDLE MODE
The MOVC instructions are the only instructions that have access to
program code in the internal or external program memory. The EA
input is latched during RESET and is “don’t care” after RESET
(also if the security bit is not set). This implementation prevents
reading internal program code by switching from external program
memory to internal program memory during a MOVC instruction or
any other instruction that uses immediate data.
In the idle mode, the CPU puts itself to sleep while some of the
on-chip peripherals stay active. The instruction to invoke the idle
mode is the last instruction executed in the normal operating mode
before the idle mode is activated. The CPU contents, the on-chip
RAM, and all of the special function registers remain intact during
this mode. The idle mode can be terminated either by any enabled
interrupt (at which time the process is picked up at the interrupt
Table 1. External Pin Status During Idle and Power-Down Modes
PROGRAM
MEMORY
ALE
PSEN
Idle
Internal
1
Idle
External
1
Power-down
Internal
Power-down
External
MODE
2002 Sep 03
PORT 2
PORT 3
PORT 4
PWM0/
PWM1
Data
Data
Data
Data
1
Data
Address
Data
Data
1
Data
Data
Data
Data
Data
1
Float
Data
Data
Data
Data
1
PORT 0
PORT 1
1
Data
1
Float
0
0
0
0
8
Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
80C552/83C552
Serial Control Register (S1CON) – See Table 2
CR2
S1CON (D8H)
ENS1
STA
STO
SI
AA
CR1
CR0
Bits CR0, CR1 and CR2 determine the serial clock frequency that is generated in the master mode of operation.
Table 2. Serial Clock Rates
BIT FREQUENCY (kHz) AT fOSC
CR2
CR1
CR0
6 MHZ
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
23
27
31
37
6.25
50
100
0.24 < 62.5
0 < 255
12 MHz
16 MHz
47
54
63
75
12.5
100
200
0.49 < 62.5
0 < 254
62.5
71
83.3
100
17
133 1
267 1
0.65 < 55.6
0 < 253
24 MHz2
94
107 1
125 1
150 1
25
200 1
400 1
0.98 < 50.0
0 <251
fOSC DIVIDED BY
256
224
192
160
960
120
60
96 × (256 – (reload value Timer 1))
reload value Timer 1 in Mode 2.
NOTES:
1. These frequencies exceed the upper limit of 100kHz of the I2C-bus specification and cannot be used in an I2C-bus application.
2. At fOSC = 24 MHz the maximum I2C bus rate of 100kHz cannot be realized due to the fixed divider rates.
ABSOLUTE MAXIMUM RATINGS1, 2, 3
RATING
UNIT
Storage temperature range
–65 to +150
°C
Voltage on any other pin to VSS
–0.5 to +6.5
V
Input, output DC current on any single I/O pin
5.0
mA
Power dissipation
(based on package heat transfer limitations, not device power consumption)
1.0
W
PARAMETER
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.
2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.
3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise
noted.
DEVICE SPECIFICATIONS
SUPPLY VOLTAGE (V)
TYPE
FREQUENCY (MHz)
MIN
MAX
MIN
MAX
TEMPERATURE RANGE (°C)
P83(0)C552EBx
4.5
5.5
3.5
16
0 to +70
P83(0)C552EFx
4.5
5.5
3.5
16
–40 to +85
P83(0)C552EHx
4.5
5.5
3.5
16
–40 to +125
P83(0)C552IBx
4.5
5.5
3.5
24
0 to +70
P83(0)C552IFx
4.5
5.5
3.5
24
–40 to +85
2002 Sep 03
9
Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
80C552/83C552
DC ELECTRICAL CHARACTERISTICS
VSS, AVSS = 0 V; VDD, AVDD = 5 V ± 10%
TEST
SYMBOL
PARAMETER
MAX
UNIT
IDD
Supply current operating:
P83(0)C552EBx
P83(0)C552EFx
P83(0)C552EHx
P83(0)C552IBx
P83(0)C552IFx
See notes 1 and 2
fOSC = 16 MHz
fOSC = 16 MHz
fOSC = 16 MHz
fOSC = 24 MHz
fOSC = 24 MHz
45
45
40
55
55
mA
mA
mA
mA
mA
Idle mode:
P83(0)C552EBx
P83(0)C552EFx
P83(0)C552EHx
P83(0)C552IBx
P83(0)C552IFx
See notes 1 and 3
fOSC = 16 MHz
fOSC = 16 MHz
fOSC = 16 MHz
fOSC = 24 MHz
fOSC = 24 MHz
10
10
9
12.5
12.5
mA
mA
mA
mA
mA
Power-down current:
See notes 1 and 4;
2 V < VPD < VDD max
50
50
150
µA
µA
µA
IID
IPD
CONDITIONS
LIMITS
MIN
P83(0)C552xBx
P83(0)C552xFx
P83(0)C552xHx
Inputs
VIL
Input low voltage, except EA, P1.6, P1.7
–0.5
0.2VDD–0.1
V
VIL1
Input low voltage to EA
–0.5
0.2VDD–0.3
V
P1.7/SDA5
VIL2
Input low voltage to P1.6/SCL,
VIH
Input high voltage, except XTAL1, RST, P1.6/SCL, P1.7/SDA
–0.5
0.3VDD
V
0.2VDD+0.9
VDD+0.5
V
VIH1
VIH2
Input high voltage, XTAL1, RST
0.7VDD
VDD+0.5
V
Input high voltage, P1.6/SCL, P1.7/SDA5
0.7VDD
6.0
V
IIL
Logical 0 input current, ports 1, 2, 3, 4, except P1.6, P1.7
VIN = 0.45 V
–50
µA
ITL
Logical 1-to-0 transition current, ports 1, 2, 3, 4, except P1.6, P1.7
±IIL1
Input leakage current, port 0, EA, STADC, EW
See note 6
–650
µA
0.45 V < VI < VDD
10
µA
±IIL2
Input leakage current, P1.6/SCL, P1.7/SDA
0 V < VI < 6 V
0 V < VDD < 5.5 V
10
µA
±IIL3
Input leakage current, port 5
0.45 V < VI < VDD
1
µA
IOL = 1.6mA7
0.45
V
3.2mA7
0.45
V
0.4
V
Outputs
VOL
Output low voltage, ports 1, 2, 3, 4, except P1.6, P1.7
VOL1
Output low voltage, port 0, ALE, PSEN, PWM0, PWM1
IOL =
VOL2
Output low voltage, P1.6/SCL, P1.7/SDA
IOL = 3.0mA7
VOH
Output high voltage, ports 1, 2, 3, 4, except P1.6/SCL, P1.7/SDA
–IOH = 60µA
–IOH = 25µA
–IOH = 10µA
2.4
0.75VDD
0.9VDD
V
V
V
VOH1
Output high voltage (port 0 in external bus mode, ALE,
PSEN PWM0,
PWM0 PWM1)8
PSEN,
–IOH = 400µA
–IOH = 150µA
–IOH = 40µA
2.4
0.75VDD
0.9VDD
V
V
V
VOH2
Output high voltage (RST)
–IOH = 400µA
–IOH = 120µA
2.4
0.8VDD
V
V
RRST
Internal reset pull-down resistor
CIO
Pin capacitance
2002 Sep 03
50
Test freq = 1 MHz,
Tamb = 25 °C
10
150
kΩ
10
pF
Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
80C552/83C552
DC ELECTRICAL CHARACTERISTICS (Continued)
TEST
SYMBOL
PARAMETER
CONDITIONS
LIMITS
MIN
MAX
UNIT
1.2
1.0
mA
mA
50
50
100
50
50
µA
µA
µA
µA
µA
50
50
100
µA
µA
µA
AVDD+0.2
V
AVDD+0.2
V
V
50
kΩ
15
pF
Analog Inputs
AIDD
Analog supply current: operating: (16 MHz)
Analog supply current: operating: (24 MHz)
AIID
Idle mode:
P83(0)C552EBx
P83(0)C552EFx
P83(0)C552EHx
P83(0)C552IBx
P83(0)C552IFx
AIPD
Port 5 = 0 to AVDD
Port 5 = 0 to AVDD
Power-down mode:
2 V < AVPD < AVDD
max
P83(0)C552xBx
P83(0)C552xFx
P83(0)C552xHx
AVIN
Analog input voltage
AVSS–0.2
AVREF
Reference voltage:
AVREF–
AVREF+
AVSS–0.2
RREF
Resistance between AVREF+ and AVREF–
CIA
Analog input capacitance
10
tADS
Sampling time
8tCY
µs
tADC
Conversion time (including sampling time)
50tCY
µs
DLe
Differential non-linearity10, 11, 12
±1
LSB
ILe
Integral non-linearity10, 13
±2
LSB
error10, 14
OSe
Offset
Ge
Gain error10, 15
error10, 16
Ae
Absolute voltage
MCTC
Channel to channel matching
517
±2
LSB
±0.4
%
±3
LSB
±1
LSB
Ct
Crosstalk between inputs of port
0–100kHz
–60
dB
NOTES FOR DC ELECTRICAL CHARACTERISTICS:
1. See Figures 10 through 15 for IDD test conditions.
2. The operating supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10 ns; VIL = VSS + 0.5 V;
VIH = VDD – 0.5 V; XTAL2 not connected; EA = RST = Port 0 = EW = VDD; STADC = VSS.
3. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10 ns; VIL = VSS + 0.5 V;
VIH = VDD – 0.5 V; XTAL2 not connected; Port 0 = EW = VDD; EA = RST = STADC = VSS.
4. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = EW = VDD;
EA = RST = STADC = XTAL1 = VSS.
5. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I2C specification, so an input voltage below 1.5 V will be recognized as a
logic 0 while an input voltage above 3.0 V will be recognized as a logic 1.
6. Pins of ports 1 (except P1.6, P1.7), 2, 3, and 4 source a transition current when they are being externally driven from 1 to 0. The transition
current reaches its maximum value when VIN is approximately 2 V.
7. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no
single output sinks more than 5mA and no more than two outputs exceed the test conditions.
8. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9 VDD specification when the
address bits are stabilizing.
9. The following condition must not be exceeded: VDD – 0.2 V < AVDD < VDD + 0.2 V.
10. Conditions: AVREF– = 0 V; AVDD = 5.0 V, AVREF+ (80C552, 83C552) = 5.12 V. ADC is monotonic with no missing codes. Measurement by
continuous conversion of AVIN = –20 mV to 5.12 V in steps of 0.5 mV.
11. The differential non-linearity (DLe) is the difference between the actual step width and the ideal step width. (See Figure 1.)
12. The ADC is monotonic; there are no missing codes.
13. The integral non-linearity (ILe) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset error. (See Figure 1.)
2002 Sep 03
11
Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
80C552/83C552
14. The offset error (OSe) is the absolute difference between the straight line which fits the actual transfer curve (after removing gain error), and
a straight line which fits the ideal transfer curve. (See Figure 1.)
15. The gain error (Ge) is the relative difference in percent between the straight line fitting the actual transfer curve (after removing offset error),
and the straight line which fits the ideal transfer curve. Gain error is constant at every point on the transfer curve. (See Figure 1.)
16. The absolute voltage error (Ae) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated
ADC and the ideal transfer curve.
17. This should be considered when both analog and digital signals are simultaneously input to port 5.
Offset
error
OSe
Gain
error
Ge
1023
1022
1021
1020
1019
1018
(2)
7
(1)
Code
Out
6
5
(5)
4
(4)
3
(3)
2
1
1 LSB
(ideal)
0
1
2
3
4
5
6
7
1018
1019
1020
1022
1023
1024
AVIN (LSBideal)
Offset
error
OSe
(1)
(2)
Example of an actual transfer curve.
The ideal transfer curve.
(3)
(4)
Differential non-linearity (DLe).
Integral non-linearity (ILe).
(5)
Center of a step of the actual transfer curve.
1 LSB =
AVREF+
– AVREF–
1024
SU01693
Figure 1. ADC Conversion Characteristic
2002 Sep 03
1021
12
Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
80C552/83C552
AC ELECTRICAL CHARACTERISTICS1, 2
16 MHz version
16 MHz CLOCK
SYMBOL
FIGURE
PARAMETER
MIN
VARIABLE CLOCK
MAX
MIN
MAX
UNIT
3.5
16
MHz
1/tCLCL
2
Oscillator frequency
tLHLL
2
ALE pulse width
85
2tCLCL–40
ns
tAVLL
2
Address valid to ALE low
8
tCLCL–55
ns
tLLAX
2
Address hold after ALE low
28
tCLCL–35
tLLIV
2
ALE low to valid instruction in
tLLPL
2
ALE low to PSEN low
23
tPLPH
2
PSEN pulse width
143
tPLIV
2
PSEN low to valid instruction in
tPXIX
2
Input instruction hold after PSEN
tPXIZ
2
Input instruction float after PSEN
38
tCLCL–25
ns
tAVIV
2
Address to valid instruction in
208
5tCLCL–105
ns
tPLAZ
2
PSEN low to address float
10
10
ns
tRLRH
3
RD pulse width
275
6tCLCL–100
tWLWH
4
WR pulse width
275
6tCLCL–100
tRLDV
3
RD low to valid data in
tRHDX
3
Data hold after RD
tRHDZ
3
Data float after RD
55
2tCLCL–70
ns
tLLDV
3
ALE low to valid data in
350
8tCLCL–150
ns
tAVDV
3
Address to valid data in
398
9tCLCL–165
ns
tLLWL
3, 4
ALE low to RD or WR low
138
3tCLCL+50
ns
tAVWL
3, 4
Address valid to WR low or RD low
120
4tCLCL–130
ns
tQVWX
4
Data valid to WR transition
3
tCLCL–60
ns
tDW
4
Data before WR
288
7tCLCL–150
ns
tWHQX
4
Data hold after WR
13
tCLCL–50
tRLAZ
3
RD low to address float
tWHLH
3, 4
150
ns
4tCLCL–100
tCLCL–40
ns
3tCLCL–45
83
0
ns
ns
3tCLCL–105
0
ns
ns
Data Memory
148
0
23
ns
5tCLCL–165
0
238
3tCLCL–50
0
RD or WR high to ALE high
ns
103
tCLCL–40
ns
ns
ns
0
ns
tCLCL+40
ns
External Clock
tCHCX
5
High time4
20
20
tCLCX
5
Low time4
20
20
tCLCH
5
Rise time4
20
20
ns
tCHCL
5
Fall time4
20
20
ns
ns
ns
Serial Timing – Shift Register Mode4 (Test Conditions: Tamb = 0 °C to +70 °C; VSS = 0 V; Load Capacitance = 80 pF)
tXLXL
6
Serial port clock cycle time
0.75
12tCLCL
µs
tQVXH
6
Output data setup to clock rising edge
492
10tCLCL–133
ns
tXHQX
6
Output data hold after clock rising edge
8
2tCLCL–117
ns
tXHDX
6
Input data hold after clock rising edge
0
0
tXHDV
6
Clock rising edge to input data valid
492
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
3. tCLCL = 1/fOSC = one oscillator clock period.
tCLCL = 83.3ns at fOSC = 12 MHz.
tCLCL = 62.5ns at fOSC = 16 MHz.
4. These values are characterized but not 100% production tested.
2002 Sep 03
13
ns
10tCLCL–133
ns
Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
80C552/83C552
AC ELECTRICAL CHARACTERISTICS (Continued)1, 2
24 MHz version
24 MHz CLOCK
SYMBOL
FIGURE
PARAMETER
MIN
MAX
VARIABLE CLOCK
MIN
MAX
UNIT
3.5
24
MHz
1/tCLCL
2
Oscillator frequency
tLHLL
2
ALE pulse width
43
2tCLCL–40
ns
tAVLL
2
Address valid to ALE low
17
tCLCL–25
ns
tLLAX
2
Address hold after ALE low
17
tCLCL–25
tLLIV
2
ALE low to valid instruction in
tLLPL
2
ALE low to PSEN low
17
tCLCL–25
ns
tPLPH
2
PSEN pulse width
80
3tCLCL–45
ns
tPLIV
2
PSEN low to valid instruction in
tPXIX
2
Input instruction hold after PSEN
tPXIZ
2
Input instruction float after PSEN
17
tCLCL–25
ns
tAVIV
2
Address to valid instruction in
128
5tCLCL–80
ns
tPLAZ
2
PSEN low to address float
10
10
ns
tRLRH
3
RD pulse width
150
6tCLCL–100
ns
tWLWH
4
WR pulse width
150
6tCLCL–100
ns
tRLDV
3
RD low to valid data in
tRHDX
3
Data hold after RD
tRHDZ
3
Data float after RDxs
55
2tCLCL–28
ns
tLLDV
3
ALE low to valid data in
183
8tCLCL–150
ns
tAVDV
3
Address to valid data in
210
9tCLCL–165
ns
tLLWL
3, 4
ALE low to RD or WR low
75
3tCLCL+50
ns
tAVWL
3, 4
Address valid to WR low or RD low
92
4tCLCL–75
ns
tQVWX
4
Data valid to WR transition
12
tCLCL–30
ns
tDW
4
Data before WR
162
7tCLCL–130
ns
tWHQX
4
Data hold after WR
17
tCLCL–25
tRLAZ
3
RD low to address float
tWHLH
3, 4
102
ns
4tCLCL–65
65
3tCLCL–60
0
0
ns
ns
ns
Data Memory
118
5tCLCL–90
0
0
175
3tCLCL–50
ns
ns
0
RD or WR high to ALE high
17
67
tCLCL–25
ns
0
ns
tCLCL+25
ns
External Clock
tCHCX
5
High time3
17
17
tCLCX
5
Low time3
17
17
tCLCH
5
Rise time3
tCHCL
5
Fall
time3
ns
ns
5
20
ns
5
20
ns
Serial Timing – Shift Register Mode3 (Test Conditions: Tamb = 0 °C to +70 °C; VSS = 0 V; Load Capacitance = 80 pF)
tXLXL
6
Serial port clock cycle time
0.5
12tCLCL
µs
tQVXH
6
Output data setup to clock rising edge
283
10tCLCL–133
ns
tXHQX
6
Output data hold after clock rising edge
23
2tCLCL–60
ns
tXHDX
6
Input data hold after clock rising edge
0
0
tXHDV
6
Clock rising edge to input data valid
283
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
3. These values are characterized but not 100% production tested.
4. tCLCL = 1/fOSC = one oscillator clock period.
tCLCL = 41.7ns at fOSC = 24 MHz.
2002 Sep 03
14
ns
10tCLCL–133
ns
Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
80C552/83C552
AC ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL
PARAMETER
INPUT
OUTPUT
I2C Interface (Refer to Figure 9)
tHD;STA
START condition hold time
≥ 14 tCLCL
> 4.0 µs 1
tLOW
SCL low time
≥ 16 tCLCL
> 4.7 µs 1
tHIGH
SCL high time
≥ 14 tCLCL
> 4.0 µs 1
tRC
SCL rise time
≤ 1 µs
–2
tFC
SCL fall time
≤ 0.3 µs
< 0.3 µs 3
tSU;DAT1
Data set-up time
≥ 250ns
> 20 tCLCL – tRD
tSU;DAT2
SDA set-up time (before rep. START cond.)
≥ 250ns
> 1 µs 1
tSU;DAT3
SDA set-up time (before STOP cond.)
≥ 250ns
> 8 tCLCL
tHD;DAT
Data hold time
≥ 0ns
> 8 tCLCL – tFC
tSU;STA
Repeated START set-up time
≥ 14 tCLCL
> 4.7 µs 1
tSU;STO
STOP condition set-up time
≥ 14 tCLCL
> 4.0 µs 1
tBUF
Bus free time
≥ 14 tCLCL
> 4.7 µs 1
tRD
SDA rise time
≤ 1 µs
–2
tFD
SDA fall time
≤ 0.3 µs
< 0.3 µs 3
NOTES:
1. At 100 kbit/s. At other bit rates this value is inversely proportional to the bit-rate of 100 kbit/s.
2. Determined by the external bus-line capacitance and the external bus-line pull-resistor, this must be < 1 µs.
3. Spikes on the SDA and SCL lines with a duration of less than 3 tCLCL will be filtered out. Maximum capacitance on bus-lines SDA and
SCL = 400 pF.
4. tCLCL = 1/fOSC = one oscillator clock period at pin XTAL1. For 62 ns, 42 ns < tCLCL < 285 ns (16 MHz, 24 MHz > fOSC > 3.5 MHz) the SI01
interface meets the I2C-bus specification for bit-rates up to 100 kbit/s.
2002 Sep 03
15
Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
80C552/83C552
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has five characters. The first character is always
‘t’ (= time). The other characters, depending on their positions,
indicate the name of a signal or the logical status of that signal. The
designations are:
A – Address
C – Clock
D – Input data
H – Logic level high
I – Instruction (program memory contents)
L – Logic level low, or ALE
P – PSEN
Q – Output data
R – RD signal
t – Time
V – Valid
W – WR signal
X – No longer a valid logic level
Z – Float
Examples: tAVLL = Time for address valid to
ALE low.
tLLPL = Time for ALE low to
PSEN low.
tLHLL
ALE
tAVLL
tPLPH
tLLPL
tLLIV
PSEN
tPLIV
tLLAX
A0–A7
PORT 0
tPXIZ
tPLAZ
tPXIX
A0–A7
INSTR IN
tAVIV
PORT 2
A8–A15
A8–A15
SU01694
Figure 2. External Program Memory Read Cycle
ALE
tWHLH
PSEN
tLLDV
tLLWL
tRLRH
RD
tAVLL
tLLAX
tRLAZ
PORT 0
tRHDZ
tRLDV
tRHDX
A0–A7
FROM RI OR DPL
DATA IN
A0–A7 FROM PCL
INSTR IN
tAVWL
tAVDV
PORT 2
P2.0–P2.7 OR A8–A15 FROM DPH
A8–A15 FROM PCH
SU01695
Figure 3. External Data Memory Read Cycle
2002 Sep 03
16
Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
80C552/83C552
ALE
tWHLH
PSEN
tWLWH
tLLWL
WR
tLLAX
tAVLL
tWHQX
tQVWX
tDW
A0–A7
FROM RI OR DPL
PORT 0
DATA OUT
A0–A7 FROM PCL
INSTR IN
tAVWL
PORT 2
P2.0–P2.7 OR A8–A15 FROM DPH
A8–A15 FROM PCH
SU01696
Figure 4. External Data Memory Write Cycle
tr
tHIGH
VIH1
VIH1
0.8 V
tf
VIH1
0.8 V
VIH1
0.8 V
0.8 V
tLOW
tCLCL
SU01697
Figure 5. External Clock Drive XTAL1
INSTRUCTION
0
1
2
3
4
5
6
7
8
ALE
tXLXL
CLOCK
tXHQX
tQVXH
OUTPUT DATA
0
1
2
3
4
5
6
7
WRITE TO SBUF
tXHDX
tXHDV
SET TI
INPUT DATA
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
CLEAR RI
SET RI
SU01678
Figure 6. Shift Register Mode Timing
2002 Sep 03
17
Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
VDD–0.5
80C552/83C552
VLOAD+0.1 V
0.2 VDD+0.9
TIMING
REFERENCE
POINTS
VLOAD
0.2 VDD–0.1
0.45 V
VLOAD–0.1 V
VOH–0.1 V
VOL+0.1 V
NOTE:
FOR TIMING PURPOSES, A PORT IS NO LONGER FLOATING WHEN A 100MV
CHANGE FROM LOAD VOLTAGE OCCURS, AND BEGINS TO FLOAT WHEN A
100 mV CHANGE FROM THE LOADED VOH/VOL LEVEL OCCURS. IOH/IOL > +
20mA.
SU01700
NOTE:
AC INPUTS DURING TESTING ARE DRIVEN AT VDD–0.5 FOR A LOGIC ‘1’ AND
0.45 V FOR A LOGIC ‘0’. TIMING MEASUREMENTS ARE MADE AT VIH MIN FOR A
LOGIC ‘1’ AND VIL MAX FOR A LOGIC ‘0’.
SU01699
Figure 8. Float Waveform
Figure 7. AC Testing Input/Output
repeated START condition
START or repeated START condition
START condition
tSU;STA
STOP condition
tRD
SDA
(INPUT/OUTPUT)
0.7 VCC
0.3 VCC
tBUF
tFD
tRC
tFC
tSU;STO
0.7 VCC
SCL
(INPUT/OUTPUT)
0.3 VCC
tSU;DAT3
tHD;STA
tLOW
tHIGH
tSU;DAT1
tHD;DAT
Figure 9. Timing SIO1 (I2C) Interface
2002 Sep 03
18
tSU;DAT2
SU01701
Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
80C552/83C552
50
(1)
40
30
IDD, ID mA
(2)
20
(3)
10
(4)
0
0
4
8
12
16 (1)
(2)
(3)
(4)
f (MHz)
NOTE:
These values are valid only within the frequency specifications of the device under test.
Maximum operating mode; VDD = 6 V
Maximum operating mode; VDD = 4 V
Maximum idle mode; VDD = 6 V
Maximum idle mode; VDD = 4 V
SU01702
Figure 10. 16 MHz Version Supply Current (IDD) as a Function of Frequency at XTAL1 (fOSC)
60
(1)
50
(2)
40
IDD, ID mA
30
20
(3)
10
(4)
0
0
4
8
f (MHz)
12
16
20
24
(1)
5.5 V
(2)
4.5 V
(3)
NOTE:
These values are valid only within the frequency specifications of the device under test.
(4)
Maximum operating mode; VDD =
Maximum operating mode; VDD =
Maximum idle mode; VDD = 5.5 V
Maximum idle mode; VDD = 4.5 V
SU01703
Figure 11. 24 MHz Version Supply Current (IDD) as a Function of Frequency at XTAL1 (fOSC)
2002 Sep 03
19
Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
VDD
80C552/83C552
VDD
IDD
P1.6
P1.7
VDD
VDD
VDD–0.5
VDD
0.7VDD
0.5 V
RST
STADC
(NC)
XTAL2
CLOCK SIGNAL
XTAL1
0.2VDD–0.1
P0
tCHCL
EA
tCLCX
tCHCX
tCLCH
EW
tCLCL
AVSS
VSS
AVref–
SU01706
SU01704
Figure 12. IDD Test Condition, Active Mode
All other pins are disconnected1
VDD
Figure 14. Clock Signal Waveform for IDD Tests in Active and
Idle Modes tCLCH = tCHCL = 5ns
VDD
VDD
IDD
P1.6
P1.7
VDD
RST
VDD
CLOCK SIGNAL
XTAL1
VDD
P0
EW
(NC)
EA
XTAL2
XTAL1
AVSS
VSS
VDD
STADC
P0
XTAL2
VDD
RST
STADC
(NC)
IDD
P1.6
P1.7
AVref–
VSS
EW
EA
AVSS
AVref–
SU01705
SU01707
Figure 13. IDD Test Condition, Idle Mode
All other pins are disconnected2
Figure 15. IDD Test Condition, Power Down Mode
All other pins are disconnected. VDD = 2 V to 5.5 V3
NOTES:
1. Active Mode:
a. The following pins must be forced to VDD: EA, RST, Port 0, and EW.
b. The following pins must be forced to VSS: STADC, AVss, and AVref–.
c. Ports 1.6 and 1.7 should be connected to VDD through resistors of sufficiently high value such that the sink current into these pins cannot
exceed the IOL1 spec of these pins.
d. The following pins must be disconnected: XTAL2 and all pins not specified above.
2. Idle Mode:
a. The following pins must be forced to VDD: Port 0 and EW.
b. The following pins must be forced to VSS: RST, STADC, AVss,, AVref–, and EA.
c. Ports 1.6 and 1.7 should be connected to VDD through resistors of sufficiently high value such that the sink current into these pins cannot
exceed the IOL1 spec of these pins. These pins must not have logic 0 written to them prior to this measurement.
d. The following pins must be disconnected: XTAL2 and all pins not specified above.
3. Power Down Mode:
a. The following pins must be forced to VDD: Port 0 and EW.
b. The following pins must be forced to VSS: RST, STADC, XTAL1, AVss,, AVref–, and EA.
c. Ports 1.6 and 1.7 should be connected to VDD through resistors of sufficiently high value such that the sink current into these pins cannot
exceed the IOL1 spec of these pins. These pins must not have logic 0 written to them prior to this measurement.
d. The following pins must be disconnected: XTAL2 and all pins not specified above.
2002 Sep 03
20
Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
PLCC68: plastic leaded chip carrier; 68 leads
2002 Sep 03
80C552/83C552
SOT188-2
21
Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
80C552/83C552
QFP80: plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
2002 Sep 03
22
SOT318-2
Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
80C552/83C552
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent
to use the components in the I2C system provided the system conforms to the
I2C specifications defined by Philips. This specification can be ordered using the
code 9398 393 40011.
Data sheet status
Data sheet status [1]
Product
status [2]
Definitions
Objective data
Development
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be
published at a later date. Philips Semiconductors reserves the right to change the specification
without notice, in order to improve the design and supply the best possible product.
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply.
Changes will be communicated according to the Customer Product/Process Change Notification
(CPCN) procedure SNW-SQ-650A.
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
 Koninklijke Philips Electronics N.V. 2002
All rights reserved. Printed in U.S.A.
Contact information
For additional information please visit
http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
Date of release: 09-02
For sales offices addresses send e-mail to:
[email protected].
Document order number:
2002 Sep 03
23
9397 750 10294