PHILIPS SC80C31BCCA44

INTEGRATED CIRCUITS
80C31/80C51/87C51
CMOS single-chip 8-bit microcontrollers
Product specification
IC20 Data Handbook
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
DESCRIPTION
80C31/80C51/87C51
PIN CONFIGURATIONS
The Philips 80C31/80C51/87C51 is a high-performance
microcontroller fabricated with Philips high-density CMOS
technology. The CMOS 8XC51 is functionally compatible with the
NMOS 8031/8051 microcontrollers. The Philips CMOS technology
combines the high speed and density characteristics of HMOS with
the low power attributes of CMOS. Philips epitaxial substrate
minimizes latch-up sensitivity.
The 8XC51 contains a 4k × 8 ROM (80C51) EPROM (87C51), a 128
× 8 RAM, 32 I/O lines, two 16-bit counter/timers, a five-source,
two-priority level nested interrupt structure, a serial I/O port for either
multi-processor communications, I/O expansion or full duplex UART,
and on-chip oscillator and clock circuits.
P1.0 1
40 V
CC
P1.1 2
39 P0.0/AD0
P1.2 3
38 P0.1/AD1
P1.3 4
37 P0.2/AD2
P1.4 5
36 P0.3/AD3
P1.5 6
35 P0.4/AD4
P1.6 7
34 P0.5/AD5
P1.7 8
33 P0.6/AD6
RST 9
In addition, the device has two software selectable modes of power
reduction—idle mode and power-down mode. The idle mode freezes
the CPU while allowing the RAM, timers, serial port, and interrupt
system to continue functioning. The power-down mode saves the
RAM contents but freezes the oscillator, causing all other chip
functions to be inoperative.
RxD/P3.0 10
TxD/P3.1 11
CERAMIC
AND
PLASTIC
DUAL
IN-LINE
PACKAGE
32 P0.7/AD7
31 EA/VPP
30 ALE/PROG
INT0/P3.2 12
29 PSEN
INT1/P3.3 13
28 P2.7/A15
T0/P3.4 14
27 P2.6/A14
T1/P3.5 15
26 P2.5/A13
WR/P3.6 16
25 P2.4/A12
RD/P3.7 17
24 P2.3/A11
– 4k × 8 EPROM (87C51)
XTAL2 18
23 P2.2/A10
– ROMless (80C31)
XTAL1 19
22 P2.1/A9
20
21 P2.0/A8
FEATURES
• 8031/8051 compatible
– 4k × 8 ROM (80C51)
– 128 × 8 RAM
VSS
– Two 16-bit counter/timers
– Full duplex serial channel
6
– Boolean processor
• Memory addressing capability
1
40
7
39
– 64k ROM and 64k RAM
CERAMIC
AND
PLASTIC
LEAD
CHIP
CARRIER
• Power control modes:
– Idle mode
– Power-down mode
17
• CMOS and TTL compatible
• Five speed ranges at VCC = 5V
18
– 12MHz
29
28
34
44
– 16MHz
– 24MHz
1
– 33MHz
• Five package styles
• Extended temperature ranges
• OTP package available
33
PLASTIC
QUAD
FLAT
PACK
11
23
12
22
SU00001
SEE PAGE 3 FOR QFP AND LCC PIN FUNCTIONS.
1996 Aug 16
2
853–0169 17187
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
CERAMIC AND PLASTIC LEADED CHIP CARRIER
PIN FUNCTIONS
6
1
80C31/80C51/87C51
PLASTIC QUAD FLAT PACK
PIN FUNCTIONS
44
40
7
34
39
1
33
LCC
PQFP
17
11
29
18
28
12
Pin
16
17
18
Function
P3.4/T0
P3.5/T1
P3.6/WR
Pin
31
32
33
P1.2
P1.3
P1.4
P1.5
19
20
21
22
P3.7/RD
XTAL2
XTAL1
VSS
34
35
36
37
8
9
10
11
P1.6
P1.7
RST
P3.0/RxD
23
24
25
26
NC*
P2.0/A8
P2.1/A9
P2.2/A10
12
13
14
15
NC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
27
28
29
30
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
Pin
1
2
3
4
5
6
7
Function
NC*
P1.0
P1.1
* DO NOT CONNECT
Function
P2.7/A15
PSEN
ALE/PROG
Function
P1.5
P1.6
P1.7
Pin
16
17
18
Function
VSS
NC*
P2.0/A8
Pin
31
32
33
Function
P0.6/AD6
P0.5/AD5
P0.4/AD4
NC*
EA/VPP
P0.7/AD7
P0.6/AD6
4
5
6
7
RST
P3.0/RxD
NC*
P3.1/TxD
19
20
21
22
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
34
35
36
37
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
38
39
40
41
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
8
9
10
11
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
23
24
25
26
P2.5/A13
P2.6/A14
P2.7/A15
PSEN
38
39
40
41
VCC
NC*
P1.0
P1.1
42
43
44
P0.1/AD1
P0.0/AD0
VCC
12
13
14
15
P3.6/WR
P3.7/RD
XTAL2
XTAL1
27
28
29
30
ALE/PROG
NC*
EA/VPP
P0.7/AD7
42
43
44
P1.2
P.13
P1.4
* DO NOT CONNECT
LOGIC SYMBOL
VSS
PORT 0
XTAL1
ADDRESS AND
DATA BUS
PORT 1
PORT 2
RxD
TxD
INT0
INT1
T0
T1
WR
RD
PORT 3
SECONDARY FUNCTIONS
XTAL2
RST
EA/VPP
PSEN
ALE/PROG
ADDRESS BUS
SU00004
1996 Aug 16
22
Pin
1
2
3
SU00002
VCC
23
3
SU00003
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C31/80C51/87C51
ORDERING INFORMATION
PHILIPS NORTH AMERICA
Freq
MHz
DRAWING
NUMBER
SC87C51CCF40
0590B
0 to +70, Ceramic Dual In-line Package, UV
3.5 to 12
SC87C51CCK44
1472A
0 to +70, Ceramic Leaded Chip Carrier, UV
3.5 to 12
SC87C51CCN40
SOT129-1
SC80C31BCCN40
SC80C51BCCN40
SOT129-1
0 to +70, Plastic Dual In-line Package, OTP
3.5 to 12
SC87C51CCA44
ROMless
DRAWING
NUMBER
TEMPERATURE RANGE oC
AND PACKAGE1
EPROM
ROM
SOT187-2
SC80C31BCCA44
SC80C51BCCA44
SOT187-2
0 to +70, Plastic Leaded Chip Carrier, OTP
3.5 to 12
SC87C51CCB44
SOT307-2
SC80C31BCCB44
SC80C51BCCB44
SOT307-2
0 to +70, Plastic Quad Flat Pack, OTP
3.5 to 12
SC87C51ACF40
0590B
–40 to +85, Ceramic Dual In-line Package, UV
3.5 to 12
SC87C51ACN40
SOT129-1
SC80C31BACN40
SC80C51BACN40
SOT129-1
–40 to +85, Plastic Dual In-line Package, OTP
3.5 to 12
SC87C51ACA44
SOT187-2
SC80C31BACA44
SC80C51BACA44
SOT187-2
–40 to +85, Plastic Leaded Chip Carrier, OTP
3.5 to 12
SC87C51ACB44
SOT307-2
SC80C31BACB44
SC80C51BACB44
SOT307-2
–40 to +85, Plastic Quad Flat Pack, OTP
3.5 to 12
SC87C51CGF40
0590B
0 to +70, Ceramic Dual In-line Package, UV
3.5 to 16
SC87C51CGK44
1472A
0 to +70, Ceramic Leaded Chip Carrier, UV
3.5 to 16
SC87C51CGN40
SOT129-1
SC80C31BCGN40
SC80C51BCGN40
SOT129-1
0 to +70, Plastic Dual In-line Package, OTP
3.5 to 16
SC87C51CGA44
SOT187-2
SC80C31BCGA44
SC80C51BCGA44
SOT187-2
0 to +70, Plastic Leaded Chip Carrier, OTP
3.5 to 16
SC87C51CGB44
SOT307-2
SC80C31BCGB44
SC80C51BCGB44
SOT307-2
0 to +70, Plastic Quad Flat Pack, OTP
3.5 to 16
SC87C51AGF40
0590B
–40 to +85, Ceramic Dual In-line Package, UV
3.5 to 16
SC87C51AGN40
SOT129-1
SC80C31BAGN40
SC80C51BAGN40
SOT129-1
–40 to +85, Plastic Dual In-line Package, OTP
3.5 to 16
SC87C51AGA44
SOT187-2
SC80C31BAGA44
SC80C51BAGA44
SOT187-2
–40 to +85, Plastic Leaded Chip Carrier, OTP
3.5 to 16
SC87C51AGB44
SOT307-2
SC80C31BAGB44
SC80C51BAGB44
SOT307-2
–40 to +85, Plastic Quad Flat Pack, OTP
3.5 to 16
SC87C51CPF40
0590B
0 to +70, Ceramic Dual In-line Package, UV
3.5 to 24
SC87C51CPK44
1472A
0 to +70, Ceramic Leaded Chip Carrier, UV
3.5 to 24
SC87C51CPN40
SOT129-1
SC80C31BCPN40
SC80C51BCPN40
SOT129-1
0 to +70, Plastic Dual In-line Package, OTP
3.5 to 24
SC87C51CPA44
SOT187-2
SC80C31BCPA44
SC80C51BCPA44
SOT187-2
0 to +70, Plastic Leaded Chip Carrier, OTP
3.5 to 24
SC87C51APF40
0590B
SC87C51APN40
SOT129-1
SC80C31BAPN40
SC80C51BAPN40
SOT129-1
–40 to +85, Plastic Dual In-line Package, OTP
3.5 to 24
SC87C51APA44
SOT187-2
SC80C31BAPA44
SC80C51BAPA44
SOT187-2
–40 to +85, Plastic Leaded Chip Carrier, OTP
3.5 to 24
SC87C51CYF40
0590B
0 to +70, Ceramic Dual In-line Package, UV
3.5 to 33
SC87C51CYK44
1472A
0 to +70, Ceramic Leaded Chip Carrier, UV
3.5 to 33
SC87C51CYN40
SOT129-1
SC80C31BCYN40
SC80C51BCYN40
SOT129-1
0 to +70, Plastic Dual In-line Package, OTP
3.5 to 33
SC87C51CYA44
SOT187-2
SC80C31BCYA44
SC80C51BCYA44
SOT187-2
0 to +70, Plastic Leaded Chip Carrier, OTP
3.5 to 33
–40 to +85, Ceramic Dual In-line Package, UV
1. OTP = One Time Programmable EPROM. UV = UV Erasable EPROM
2. SOT311 replaced by SOT307-2.
1996 Aug 16
4
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C31/80C51/87C51
ORDERING INFORMATION (Continued)
PHILIPS
ROMless
ROMless
(ORDER NUMBER)
(MARKING NUMBER)
PCB80C31-2 N
PCB80C31BH2-12P
PCB80C31-2 A
ROM
TEMPERATURE RANGE oC
AND PACKAGE1
Freq
MHz
SOT129-1
0 to +70, Plastic Dual In-line Package, OTP
0.5 to 12
PCB80C31BH2-12WP PCB80C51BH-2WP
SOT187-2
0 to +70, Plastic Leaded Chip Carrier, OTP
0.5 to 12
PCB80C31BH2-12H
PCB80C51BH-2H
SOT307-22
0 to +70, Plastic Quad Flat Pack, OTP
0.5 to 12
PCB80C31-3 N
PCB80C31BH3-16P
PCB80C51BH-3P
SOT129-1
0 to +70, Plastic Dual In-line Package, OTP
1.2 to 16
PCB80C31-3 A
PCB80C31BH3-16WP PCB80C51BH-3WP
SOT187-2
0 to +70, Plastic Leaded Chip Carrier, OTP
1.2 to 16
PCB80C31BH3-16H
PCB80C51BH-3H
SOT307-22
0 to +70, Plastic Quad Flat Pack, OTP
1.2 to 16
PCF80C31-3 N
PCF80C31BH3-16P
PCF80C51BH-3P
SOT129-1
–40 to +85, Plastic Dual In-line Package, OTP
1.2 to 16
PCF80C31-3 A
PCF80C31BH3-16WP
PCF80C51BH-3WP
SOT187-2
–40 to +85, Plastic Leaded Chip Carrier, OTP
1.2 to 16
PCF80C31BH3-16H
PCF80C51BH-3H
SOT307-22
–40 to +85, Plastic Quad Flat Pack, OTP
1.2 to 16
PCA80C31BH3-16P
PCA80C51BH-3P
SOT129-1
–40 to +125, Plastic Dual In-line Package
1.2 to 16
PCA80C31BH3-16WP PCA80C51BH-3WP
SOT187-2
–40 to +125, Plastic Leaded Chip Carrier
1.2 to 16
PCB80C31-4 N
PCB80C31BH4-24P
SOT129-1
0 to +70, Plastic Dual In-line Package, OTP
1.2 to 24
PCB80C31-4 A
PCB80C31BH4-24WP PCB80C51BH-4WP
SOT187-2
0 to +70, Plastic Leaded Chip Carrier, OTP
1.2 to 24
PCB80C31BH4-24H
PCB80C51BH-4H
SOT307-22
0 to +70, Plastic Quad Flat Pack, OTP
1.2 to 24
PCF80C31-4 N
PCF80C31BH4-24P
PCF80C51BH-4P
SOT129-1
–40 to +85, Plastic Dual In-line Package, OTP
1.2 to 24
PCF80C31-4 A
PCF80C31BH4-24WP
PCF80C51BH-4WP
SOT187-2
–40 to +85, Plastic Leaded Chip Carrier, OTP
1.2 to 24
PCF80C31BH4-24H
PCF80C51BH-4H
SOT307-22
–40 to +85, Plastic Leaded Chip Carrier, OTP
1.2 to 24
PCB80C31-5 N
PCB80C31BH5-30P
PCB80C51BH-5P
SOT129-1
0 to +70, Plastic Dual In-line Package
1.2 to 33
PCB80C31-5 A
PCB80C31BH5-30WP PCB80C51BH-5WP
SOT187-2
0 to +70, Plastic Leaded Chip Carrier
1.2 to 33
PCB80C31-5 B
PCB80C31BH5-30H
SOT307-22
0 to +70, Plastic Quad Flat Pack
1.2 to 33
1996 Aug 16
PCB80C51BH-2P
DRAWING
NUMBER
PCB80C51BH-4P
PCB80C51BH-5H
5
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C31/80C51/87C51
BLOCK DIAGRAM
P0.0–P0.7
P2.0–P2.7
PORT 0
DRIVERS
PORT 2
DRIVERS
VCC
VSS
RAM ADDR
REGISTER
PORT 0
LATCH
RAM
B
REGISTER
PORT 2
LATCH
ROM/EPROM
STACK
POINTER
ACC
PROGRAM
ADDRESS
REGISTER
TMP1
TMP2
PCON
ALU
SCON
TMOD
TCON
TH0
TL0
TH1
SBUF
IE
IP
BUFFER
TL1
PSW
INTERRUPT, SERIAL
PORT AND TIMER BLOCKS
PC
INCREMENTER
PSEN
ALE/PROG
EA/VPP
TIMING
AND
CONTROL
RST
INSTRUCTION
REGISTER
PROGRAM
COUNTER
PD
DPTR
PORT 1
LATCH
PORT 3
LATCH
PORT 1
DRIVERS
PORT 3
DRIVERS
P1.0–P1.7
P3.0–P3.7
OSCILLATOR
XTAL1
XTAL2
SU00005
1996 Aug 16
6
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C31/80C51/87C51
PIN DESCRIPTION
PIN NO.
MNEMONIC
DIP
LCC
QFP
TYPE
VSS
20
22
16
I
Ground: 0V reference.
VCC
40
44
38
I
Power Supply: This is the power supply voltage for normal, idle, and power-down
operation.
39–32
43–36
37–30
I/O
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to
them float and can be used as high-impedance inputs. Port 0 is also the multiplexed
low-order address and data bus during accesses to external program and data memory. In
this application, it uses strong internal pull-ups when emitting 1s. Port 0 also outputs the
code bytes during program verification in the 87C51. External pull-ups are required during
program verification.
P1.0–P1.7
1–8
2–9
40-44,
1–3
I/O
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, port 1 pins that are externally pulled low will source current because of the internal
pull-ups. (See DC Electrical Characteristics: IIL). Port 1 also receives the low-order address
byte during program memory verification.
P2.0–P2.7
21–28
24–31
18–25
I/O
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, port 2 pins that are externally being pulled low will source current because of the
internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2 emits the high-order
address byte during fetches from external program memory and during accesses to
external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it
uses strong internal pull-ups when emitting 1s. During accesses to external data memory
that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function
register.
P3.0–P3.7
10–17
11,
13–19
5,
7–13
I/O
10
11
12
13
14
15
16
17
11
13
14
15
16
17
18
19
5
7
8
9
10
11
12
13
I
O
I
I
I
I
O
O
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, port 3 pins that are externally being pulled low will source current because of the
pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also serves the special features of
the 80C51 family, as listed below:
RxD (P3.0): Serial input port
TxD (P3.1): Serial output port
INT0 (P3.2): External interrupt
INT1 (P3.3): External interrupt
T0 (P3.4): Timer 0 external input
T1 (P3.5): Timer 1 external input
WR (P3.6): External data memory write strobe
RD (P3.7): External data memory read strobe
RST
9
10
4
I
Reset: A high on this pin for two machine cycles while the oscillator is running, resets the
device. An internal diffused resistor to VSS permits a power-on reset using only an external
capacitor to VCC.
ALE/PROG
30
33
27
I/O
Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the
address during an access to external memory. In normal operation, ALE is emitted at a
constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking.
Note that one ALE pulse is skipped during each access to external data memory. This pin is
also the program pulse input (PROG) during EPROM programming.
PSEN
29
32
26
O
Program Store Enable: The read strobe to external program memory. When the device is
executing code from the external program memory, PSEN is activated twice each machine
cycle, except that two PSEN activations are skipped during each access to external data
memory. PSEN is not activated during fetches from internal program memory.
EA/VPP
31
35
29
I
External Access Enable/Programming Supply Voltage: EA must be externally held low
to enable the device to fetch code from external program memory locations 0000H to
0FFFH. If EA is held high, the device executes from internal program memory unless the
program counter contains an address greater than 0FFFH. This pin also receives the
12.75V programming supply voltage (VPP) during EPROM programming.
XTAL1
19
21
15
I
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator
circuits.
XTAL2
18
20
14
O
Crystal 2: Output from the inverting oscillator amplifier.
P0.0–0.7
1996 Aug 16
NAME AND FUNCTION
7
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
Table 1.
SYMBOL
80C31/80C51/87C51
80C52/80C54/80C58 Special Function Registers
DESCRIPTION
DIRECT
ADDRESS
BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION
MSB
LSB
RESET
VALUE
ACC*
Accumulator
E0H
E7
E6
E5
E4
E3
E2
E1
E0
00H
AUXR#
Auxiliary
8EH
–
–
–
–
–
–
–
AO
xxxxxxx0B
AUXR1#
Auxiliary 1 (Note 2)
A2H
–
–
–
–
WUPD
0
–
DPS
xxxx00x0B
B*
B register
F0H
F7
F6
F5
F4
F3
F2
F1
F0
DPTR:
DPH
DPL
Data Pointer (2 bytes)
Data Pointer High
Data Pointer Low
83H
82H
IE*
Interrupt Enable
A8H
IP*
Interrupt Priority
B8H
IPH#
Interrupt Priority High
B7H
P0*
Port 0
80H
00H
00H
00H
AF
AE
AD
AC
AB
AA
A9
A8
EA
EC
ET2
ES
ET1
EX1
ET0
EX0
BF
BE
BD
BC
BB
BA
B9
B8
–
–
PT2
PS
PT1
PX1
PT0
PX0
B7
B6
B5
B4
B3
B2
B1
B0
–
–
PT2H
PSH
PT1H
PX1H
PT0H
PX0H
87
86
85
84
83
82
81
80
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
97
96
95
94
93
92
91
90
–
–
–
–
–
T2EX
T2
P1*
Port 1
90H
–
A7
A6
A5
A4
A3
A2
A1
A0
P2*
Port 2
A0H
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
B7
B6
B5
B4
B3
B2
B1
B0
00H
x0000000B
x0000000B
FFH
FFH
FFH
P3*
Port 3
B0H
RD
WR
T1
T0
INT1
INT0
TxD
RxD
FFH
PCON#1
Power Control
87H
SMOD1
SMOD0
–
–
GF1
GF0
PD
IDL
00xx0000B
D7
D6
D5
D4
D3
D2
D1
D0
PSW*
Program Status Word
D0H
CY
AC
F0
RS1
RS0
OV
–
P
SADDR#
SADEN#
Slave Address
Slave Address Mask
A9H
B9H
SBUF
Serial Data Buffer
99H
SCON*
Serial Control
98H
SP
Stack Pointer
81H
TCON*
Timer Control
88H
T2MOD#
TH0
TH1
TL0
TL1
Timer 2 Mode Control
Timer High 0
Timer High 1
Timer Low 0
Timer Low 1
C9H
8CH
8DH
8AH
8BH
00H
00H
xxxxxxxxB
9F
9E
9D
9C
9B
9A
99
98
SM0/FE
SM1
SM2
REN
TB8
RB8
TI
RI
8F
8E
8D
8C
8B
8A
89
88
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
CF
CE
CD
CC
CB
CA
C9
C8
–
–
–
–
–
–
T2OE
DCEN
C/T
M1
M0
GATE
C/T
M1
M0
00H
07H
TMOD
Timer Mode
89H
GATE
* SFRs are bit addressable.
# SFRs are modified from or added to the 80C51 SFRs.
– Reserved bits.
1. Reset value depends on reset source.
2. Available only on SC80C51.
1996 Aug 16
00H
8
00H
xxxxxx00B
00H
00H
00H
00H
00H
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C31/80C51/87C51
OSCILLATOR CHARACTERISTICS
IDLE MODE
XTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier. The pins can be configured for use as an on-chip
oscillator, as shown in the logic symbol.
In idle mode, the CPU puts itself to sleep while all of the on-chip
peripherals stay active. The instruction to invoke the idle mode is the
last instruction executed in the normal operating mode before the
idle mode is activated. The CPU contents, the on-chip RAM, and all
of the special function registers remain intact during this mode. The
idle mode can be terminated either by any enabled interrupt (at
which time the process is picked up at the interrupt service routine
and continued), or by a hardware reset which starts the processor in
the same manner as a power-on reset.
To drive the device from an external clock source, XTAL1 should be
driven while XTAL2 is left unconnected. There are no requirements
on the duty cycle of the external clock signal, because the input to
the internal clock circuitry is through a divide-by-two flip-flop.
However, minimum and maximum high and low times specified in
the data sheet must be observed.
POWER-DOWN MODE
RESET
In the power-down mode, the oscillator is stopped and the
instruction to invoke power-down is the last instruction executed.
Only the contents of the on-chip RAM are preserved. A hardware
reset is the only way to terminate the power-down mode. the control
bits for the reduced power modes are in the special function register
PCON.
A reset is accomplished by holding the RST pin high for at least two
machine cycles (24 oscillator periods), while the oscillator is running.
To insure a good power-up reset, the RST pin must be high long
enough to allow the oscillator time to start up (normally a few
milliseconds) plus two machine cycles.
Table 2 shows the state of I/O ports during low current operating
modes.
Table 2. External Pin Status During Idle and Power-Down Modes
MODE
PROGRAM MEMORY
ALE
PSEN
PORT 0
PORT 1
PORT 2
PORT 3
Idle
Internal
1
1
Data
Data
Data
Data
Idle
External
1
1
Float
Data
Address
Data
Power-down
Internal
0
0
Data
Data
Data
Data
Power-down
External
0
0
Float
Data
Data
Data
ROM CODE SUBMISSION
When submitting ROM code for the 80C51, the following must be specified:
1. 4k byte user ROM data
2. 64 byte ROM encryption key (SC80C51 only)
3. ROM security bits (SC80C51 only).
ADDRESS
CONTENT
BIT(S)
COMMENT
0000H to 0FFFH
DATA
7:0
User ROM Data
1000H to 101FH
KEY
7:0
ROM Encryption Key
1020H
SEC
0
ROM Security Bit 1
1020H
SEC
1
ROM Security Bit 2
Security Bit 1: When programmed, this bit has two effects on masked ROM parts:
1. External MOVC is disabled, and
2. EA# is latched on Reset.
Security Bit 2: When programmed, this bit inhibits Verify User ROM.
1996 Aug 16
9
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C31/80C51/87C51
Electrical Deviations from Commercial Specifications for Extended Temperature Range (87C51)
DC and AC parameters not included here are the same as in the commercial temperature range table.
DC ELECTRICAL CHARACTERISTICS
Tamb = –40°C to +85°C, VCC = 5V ±10%, VSS = 0V (Philips North America SC87C51);
For SC87C51 (33MHz only), Tamb = 0°C to +70°C, VCC = 5V ±5%
Tamb = –40°C to +85°C, VCC = 5V ±10%, VSS = 0V (PCB80C31/51 and PCF80C31/51 Philips Parts Only)
TEST
SYMBOL
PARAMETER
CONDITIONS
LIMITS
MIN
MAX
UNIT
VIL
Input low voltage, except EA (Philips North America)
–0.5
0.2VCC–0.15
V
VIL
Input low voltage, except EA (Philips)
–0.5
0.2VCC–0.25
V
VIL1
Input low voltage to EA
–0.5
0.2VCC–0.45
V
VIH
Input high voltage, except XTAL1, RST
0.2VCC+1
VCC+0.5
V
VIH1
Input high voltage to XTAL1, RST
0.7VCC+0.1
VCC+0.5
V
IIL
Logical 0 input current, ports 1, 2, 3
VIN = 0.45V
–75
µA
ITL
Logical 1-to-0 transition current, ports 1, 2, 3
VIN = 2.0V
–750
µA
ICC
Power supply current:
Active mode1 @ 16MHz (Philips PCB80C31/51, PCF80C31/51)
Active mode @ 12MHz (Philips North America SC87C51)
Idle mode2 @ 16MHz (Philips PCB80C31/51, PCF80C31/51)
Idle mode @ 12MHz (Philips North America SC87C51)
Power-down mode3 (Philips PCB80C31/51, PCF80C31/51)
Power-down mode (Philips North America SC87C51)
25
20
6.5
5
75
50
mA
mA
mA
mA
µA
µA
VCC = 4.5–5.5V
NOTES:
1. The operating supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10ns; VIL = VSS + 0.5V;
VIH = VCC – 0.5V; XTAL2 not connected; EA = RST = Port 0 = VCC.
2. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10ns; VIL = VSS + 0.5V;
VIH = VCC – 0.5V; XTAL2 not connected; EA = Port 0 = VCC; RST = VSS.
3. The power-down current is measured with all output pins disconnected, XTAL2 not connected, EA = Port 0 = VCC; RST = VSS.
ABSOLUTE MAXIMUM RATINGS1, 2, 3
PARAMETER
RATING
UNIT
0 to +70 or –40 to +85
°C
–65 to +150
°C
0 to +13.0
V
–0.5 to +6.5
V
Maximum IOL per I/O pin
15
mA
Power dissipation (based on package heat transfer limitations, not device power consumption)
1.5
W
Operating temperature under bias
Storage temperature range
Voltage on EA/VPP pin to VSS
Voltage on any other pin to VSS
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.
2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.
3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise
noted.
1996 Aug 16
10
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C31/80C51/87C51
DC ELECTRICAL CHARACTERISTICS
Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5V ±20%, VSS = 0V (PCB80C31/51 and PCF80C31/51) (12, 16, and 24MHz versions)
Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5V ±10%, VSS = 0V (87C51 12, 16, and 24MHz versions) (PCB80C31/51 33MHz version);
For SC87C51 (33MHz only) Tamb = 0°C to +70°C, VCC = 5V ±5%
TEST
SYMBOL
VIL
PARAMETER
Input low voltage, except
CONDITIONS
EA7
EA7
VIL1
Input low voltage to
VIH
Input high voltage, except XTAL1, RST7
VIH1
Input high voltage, XTAL1,
RST7
311
VOL
Output low voltage, ports 1, 2,
VOL1
Output low voltage, port 0, ALE, PSEN11
TYPICAL1
MAX
UNIT
–0.5
0.2VCC–0.1
V
0
0.2VCC–0.3
V
0.2VCC+0.9
VCC+0.5
V
0.7VCC
VCC+0.5
V
1.6mA2
0.45
V
IOL = 3.2mA2
0.45
V
IOL =
PSEN3
LIMITS
MIN
VOH
Output high voltage, ports 1, 2, 3, ALE,
VOH1
Output high voltage (port 0 in external bus mode)
IIL
Logical 0 input current, ports 1, 2, 37
VIN = 0.45V
–50
µA
ITL
Logical 1-to-0 transition current, ports 1, 2, 37
See note 4
–650
µA
ILI
Input leakage current, port 0
VIN = VIL or VIH
±10
µA
18
19
4.4
4
50
mA
mA
mA
mA
µA
300
150
kΩ
kΩ
ICC
RRST
IOH = –60µA,
IOH = –25µA
IOH = –10µA
2.4
0.75VCC
0.9VCC
V
V
V
IOH = –800µA,
IOH = –300µA
IOH = –80µA
2.4
0.75VCC
0.9VCC
V
V
V
current:7
Power supply
Active mode @ 12MHz8 (Philips)
Active mode @ 12MHz5 (Philips North America)
Idle mode @ 12MHz9 (Philips)
Idle mode @ 12MHz (Philips North America)
Power-down mode10 (Philips and
Philips North America)
See note 6
11.5
1.3
3
Internal reset pull-down resistor
(Philips North America)
(Philips)
50
50
CIO
Pin capacitance12
10
pF
NOTES:
1. Typical ratings are not guaranteed. The values listed are at room temperature, 5V.
2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no
single output sinks more than 5mA and no more than two outputs exceed the test conditions.
3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VCC specification when the
address bits are stabilizing.
4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when VIN is approximately 2V.
5. ICCMAX at other frequencies (for Philips North America parts) is given by: Active mode: ICCMAX = 1.43 X FREQ + 1.90;
Idle mode: ICCMAX = 0.14 X FREQ +2.31, where FREQ is the external oscillator frequency in MHz. ICCMAX is given in mA. See Figure 8.
6. See Figures 9 through 12 for ICC test conditions.
7. For Philips North America parts when Tamb = –40°C to +85°C or Philips parts when Tamb = –40°C to +125°C, see DC Electrical
Characteristics table on previous page.
8. The operating supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10ns; VIL = VSS + 0.5V;
VIH = VCC – 0.5V; XTAL2 not connected; EA = RST = Port 0 = VCC.
9. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10ns; VIL = VSS + 0.5V;
VIH = VCC – 0.5V; XTAL2 not connected; EA = Port 0 = VCC; RST = VSS.
10. The power-down current is measured with all output pins disconnected, XTAL2 not connected, EA = Port 0 = VCC; RST = VSS.
11. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
15mA
Maximum IOL per port pin:
26mA
Maximum IOL per 8-bit port:
67mA
Maximum IOL total for all outputs:
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
test conditions.
12. Pin capacitance for the ceramic DIP package is 15pF maximum.
1996 Aug 16
11
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C31/80C51/87C51
DC ELECTRICAL CHARACTERISTICS FOR PHILIPS NORTH AMERICA DEVICES (SC80C31 AND SC80C51)
Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5V ±10%; VSS = 0V
SYMBOL
TEST
CONDITIONS
PARAMETER
VIL
Input low voltage
VIH
Input high voltage (ports 0, 1, 2, 3, EA)
VIH1
Input high voltage, XTAL1, RST
VOL
Output low voltage, ports 1, 2, 38
VOL1
MIN
TYP1
UNIT
MAX
–0.5
0.2VCC–0.1
V
0.2VCC+0.9
VCC+0.5
V
0.7VCC
VCC+0.5
V
VCC = 4.5V
IOL = 1.6mA2
0.4
V
Output low voltage, port 0, ALE, PSEN8, 7
VCC = 4.5V
IOL = 3.2mA2
0.4
V
VOH
Output high voltage, ports 1, 2, 3 3
VCC = 4.5V
IOH = –30µA
VCC – 0.7
V
VOH1
Output high voltage (port 0 in external bus mode),
ALE9, PSEN3
VCC = 4.5V
IOH = –3.2mA
VCC – 0.7
V
IIL
Logical 0 input current, ports 1, 2, 3
VIN = 0.4V
–1
ITL
Logical 1-to-0 transition current, ports 1, 2, 36
ILI
Input leakage current, port 0
ICC
Power supply current (see Figure 8):
Active mode @ 16MHz5
Idle mode @ 16MHz5
Power-down mode
RRST
Internal reset pull-down resistor
CIO
Pin capacitance10 (except EA)
4.5V < VCC < 5.5V
LIMITS
–50
µA
VIN = 2.0V
See note 4
–650
µA
0.45 < VIN < VCC – 0.3
±10
µA
32
5
50
75
µA
µA
µA
µA
225
kΩ
15
pF
See note 5
11.5
1.3
3
Tamb = 0 to +70°C
Tamb = –40 to +85°C
40
NOTES:
1. Typical ratings are not guaranteed. The values listed are at room temperature, 5V.
2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no
single output sinks more than 5mA and no more than two outputs exceed the test conditions.
3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the (VCC–0.7) specification when the
address bits are stabilizing.
4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when VIN is approximately 2V.
5. See Figures 9 through 12 for ICC test conditions.
Active Mode:
ICC = 1.5 × FREQ + 8.0;
Idle Mode:
ICC = 0.14 × FREQ +2.31; See Figure 8.
6. This value applies to Tamb = 0°C to +70°C. For Tamb = –40°C to +85°C, ITL = –750µA.
7. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
8. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
15mA (*NOTE: This is 85°C specification.)
Maximum IOL per port pin:
Maximum IOL per 8-bit port:
26mA
71mA
Maximum total IOL for all outputs:
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
test conditions.
9. ALE is tested to VOH1, except when ALE is off then VOH is the voltage specification.
10. Pin capacitance is characterized but not tested. Pin capacitance is less than 25pF. Pin capacitance of ceramic package is less than 15pF
(except EA it is 25pF).
1996 Aug 16
12
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C31/80C51/87C51
AC ELECTRICAL CHARACTERISTICS FOR SC87C51 12–33MHz PHILIPS NORTH AMERICA DEVICES
Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5V ±10%, VSS = 0V (SC87C51 12, 16 and 24MHz versions);
For SC87C51 (33MHz only) Tamb = = 0°C to +70°C, VCC = 5V ±5%
VARIABLE CLOCK3
SYMBOL
FIGURE
1/tCLCL
Oscillator frequency:
SC87C51
PARAMETER
MIN
MAX
UNIT
Speed Versions
C
G
P
Y
3.5
3.5
3.5
3.5
12
16
24
33
MHz
MHz
MHz
MHz
tLHLL
1
ALE pulse width
2tCLCL–40
ns
tAVLL
1
Address valid to ALE low
tCLCL–13
ns
tLLAX
1
Address hold after ALE low
tCLCL–20
ns
tLLIV
1
ALE low to valid instruction in
tLLPL
1
ALE low to PSEN low
tCLCL–13
ns
tPLPH
1
PSEN pulse width
3tCLCL–20
ns
tPLIV
1
PSEN low to valid instruction in
tPXIX
1
Input instruction hold after PSEN
tPXIZ
1
Input instruction float after PSEN
tCLCL–10
ns
tAVIV
1
Address to valid instruction in
5tCLCL–55
ns
tPLAZ
1
PSEN low to address float
10
ns
4tCLCL–65
3tCLCL–45
0
ns
ns
ns
Data Memory
tRLRH
2, 3
RD pulse width
6tCLCL–100
ns
tWLWH
2, 3
WR pulse width
6tCLCL–100
ns
tRLDV
2, 3
RD low to valid data in
tRHDX
2, 3
Data hold after RD
tRHDZ
2, 3
Data float after RD
2tCLCL–28
ns
tLLDV
2, 3
ALE low to valid data in
8tCLCL–150
ns
tAVDV
2, 3
Address to valid data in
9tCLCL–165
ns
tLLWL
2, 3
ALE low to RD or WR low
3tCLCL–50
3tCLCL+50
ns
tAVWL
2, 3
Address valid to WR low or RD low
4tCLCL–75
ns
tQVWX
2, 3
Data valid to WR transition
tCLCL–20
ns
tWHQX
2, 3
Data hold after WR
tCLCL–20
ns
tRLAZ
2, 3
RD low to address float
tWHLH
2, 3
RD or WR high to ALE high
5tCLCL–90
0
tCLCL–20
ns
ns
0
ns
tCLCL+25
ns
External Clock
tCHCX
5
High time
12
ns
tCLCX
5
Low time
12
ns
tCLCH
5
Rise time
20
ns
tCHCL
5
Fall time
20
ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. For all Philips North America speed versions only.
4. Interfacing the 87C51 to devices with float times up to 50ns is permitted. This limited bus contention will not cause damage to port 0 drivers.
1996 Aug 16
13
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C31/80C51/87C51
AC ELECTRICAL CHARACTERISTICS FOR PHILIPS DEVICES
Tamb = 0°C to +70°C, VCC = 5V ±20%, VSS = 0V (PCB80C31/51, PCF80C31/51)1, 2, 4, 5
VARIABLE CLOCK3
SYMBOL
FIGURE
1/tCLCL
PARAMETER
MIN
MAX
UNIT
Oscillator frequency: Speed Versions
PCB8031/51
–2
PCA/PCB/PCF80C31/51
–3
PCB/PCF80C31/51
–4
PCB/FB80C31/51
–5
0.5
1.2
1.2
1.2
12
16
24
33
MHz
MHz
MHz
MHz
tLHLL
1
ALE pulse width
2tCLCL–40
ns
tAVLL
1
Address valid to ALE low
tCLCL–25
ns
tLLAX
1
Address hold after ALE low
tCLCL–25
ns
tLLIV
1
ALE low to valid instruction in
tLLPL
1
ALE low to PSEN low
tCLCL–25
ns
tPLPH
1
PSEN pulse width
3tCLCL–45
ns
tPLIV
1
PSEN low to valid instruction in
tPXIX
1
Input instruction hold after PSEN
tPXIZ
1
Input instruction float after PSEN
tCLCL–25
ns
tAVIV
1
Address to valid instruction in
5tCLCL–80
ns
tPLAZ
1
PSEN low to address float
10
ns
4tCLCL–65
3tCLCL–60
0
ns
ns
ns
Data Memory
tRLRH
2, 3
RD pulse width
6tCLCL–100
ns
tWLWH
2, 3
WR pulse width
6tCLCL–100
ns
tRLDV
2, 3
RD low to valid data in
tRHDX
2, 3
Data hold after RD
tRHDZ
2, 3
Data float after RD
2tCLCL–28
ns
tLLDV
2, 3
ALE low to valid data in
8tCLCL–150
ns
tAVDV
2, 3
Address to valid data in
9tCLCL–165
ns
tLLWL
2, 3
ALE low to RD or WR low
3tCLCL–50
3tCLCL+50
ns
tAVWL
2, 3
Address valid to WR low or RD low
4tCLCL–75
ns
tQVWX
2, 3
Data valid to WR transition
tCLCL–30
ns
tWHQX
2, 3
Data hold after WR
tCLCL–25
tRLAZ
2, 3
RD low to address float
tWHLH
2, 3
RD or WR high to ALE high
5tCLCL–90
0
tCLCL–25
ns
ns
ns
0
ns
tCLCL+25
ns
External Clock
tCHCX
5
High time
15
ns
tCLCX
5
Low time
15
ns
tCLCH
5
Rise time
20
ns
tCHCL
5
Fall time
20
ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. For all Philips speed versions only.
4. Interfacing the 80C31/51 to devices with float times up to 30ns is permitted. This limited bus contention will not cause damage to port 0
drivers.
5. VCC = 5V ±10% for 33MHz.
1996 Aug 16
14
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C31/80C51/87C51
AC ELECTRICAL CHARACTERISTICS FOR PHILIPS NORTH AMERICA DEVICES (SC80C31 AND SC80C51)
Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5V ±10%, VSS = 0V1, 2, 3
16MHz CLOCK
SYMBOL
FIGURE
PARAMETER
MIN
MAX
VARIABLE CLOCK
MIN
MAX
UNIT
3.5
16
MHz
1/tCLCL
1
Oscillator frequency
Speed versions : C, G
tLHLL
1
ALE pulse width
85
2tCLCL–40
ns
tAVLL
1
Address valid to ALE low
22
tCLCL–40
ns
tLLAX
1
Address hold after ALE low
32
tLLIV
1
ALE low to valid instruction in
tLLPL
1
ALE low to PSEN low
32
tCLCL–30
ns
tPLPH
1
PSEN pulse width
142
3tCLCL–45
ns
tCLCL–30
150
in4
ns
4tCLCL–100
82
tPLIV
1
PSEN low to valid instruction
tPXIX
1
Input instruction hold after PSEN
tPXIZ
1
Input instruction float after PSEN
37
tCLCL–25
ns
tAVIV
1
Address to valid instruction in4
207
5tCLCL–105
ns
tPLAZ
1
PSEN low to address float
10
10
ns
0
3tCLCL–105
ns
0
ns
ns
Data Memory
tRLRH
2, 3
RD pulse width
275
6tCLCL–100
ns
tWLWH
2, 3
WR pulse width
275
6tCLCL–100
ns
tRLDV
2, 3
RD low to valid data in
tRHDX
2, 3
Data hold after RD
tRHDZ
2, 3
Data float after RD
65
2tCLCL–60
ns
tLLDV
2, 3
ALE low to valid data in
350
8tCLCL–150
ns
tAVDV
2, 3
Address to valid data in
397
9tCLCL–165
ns
tLLWL
2, 3
ALE low to RD or WR low
137
3tCLCL+50
ns
tAVWL
2, 3
Address valid to WR low or RD low
122
4tCLCL–130
ns
tQVWX
2, 3
Data valid to WR transition
13
tCLCL–50
ns
tWHQX
2, 3
Data hold after WR
13
tCLCL–50
ns
Data valid to WR high
287
147
0
tQVWH
3
tRLAZ
2, 3
RD low to address float
tWHLH
2, 3
RD or WR high to ALE high
23
5tCLCL–165
0
239
3tCLCL–50
ns
7tCLCL–150
0
103
tCLCL–40
ns
ns
0
ns
tCLCL+40
ns
External Clock
tCHCX
5
High time
20
20
tCLCL–tCLCX
ns
tCLCX
5
Low time
20
20
tCLCL–tCHCX
ns
tCLCH
5
Rise time
20
20
ns
tCHCL
5
Fall time
20
20
ns
tXLXL
4
Serial port clock cycle time
750
12tCLCL
ns
tQVXH
4
Output data setup to clock rising edge
492
10tCLCL–133
ns
tXHQX
4
Output data hold after clock rising edge
8
2tCLCL–117
ns
tXHDX
4
Input data hold after clock rising edge
0
0
ns
Shift Register
tXHDV
4
Clock rising edge to input data valid
492
10tCLCL–133
ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. Interfacing the 80C31/51 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0
drivers.
4. See application note AN457 for external memory interfacing.
1996 Aug 16
15
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C31/80C51/87C51
AC ELECTRICAL CHARACTERISTICS FOR PHILIPS NORTH AMERICA DEVICES (SC80C31 AND SC80C51)
Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5V ±10%, VSS = 0V1, 2, 3
24MHz CLOCK
SYMBOL
FIGURE
1/tCLCL
1
PARAMETER
MIN
Oscillator frequency
Speed versions : P (24MHz)
: Y (33MHz)
3.5
MAX
VARIABLE CLOCK4
MIN
MAX
3.5
33
33MHz CLOCK
MIN
MAX
3.5
33
24
UNIT
MHz
tLHLL
1
ALE pulse width
43
2tCLCL–40
21
ns
tAVLL
1
Address valid to ALE low
17
tCLCL–25
5
ns
tLLAX
1
Address hold after ALE low
17
tLLIV
1
ALE low to valid instruction in
tLLPL
1
ALE low to PSEN low
17
tPLPH
1
PSEN pulse width
80
tPLIV
1
PSEN low to valid instruction in
tPXIX
1
Input instruction hold after PSEN
tPXIZ
1
Input instruction float after PSEN
17
tCLCL–25
5
ns
tAVIV
1
Address to valid instruction in
128
5tCLCL–80
70
ns
tPLAZ
1
PSEN low to address float
10
10
10
ns
tCLCL–25
102
ns
4tCLCL–65
tCLCL–25
5
3tCLCL–45
65
0
55
ns
45
3tCLCL–60
0
ns
ns
30
0
ns
ns
Data Memory
tRLRH
2, 3
RD pulse width
150
6tCLCL–100
82
tWLWH
2, 3
WR pulse width
150
tRLDV
2, 3
RD low to valid data in
tRHDX
2, 3
Data hold after RD
tRHDZ
2, 3
Data float after RD
55
2tCLCL–28
32
ns
tLLDV
2, 3
ALE low to valid data in
183
8tCLCL–150
90
ns
tAVDV
2, 3
Address to valid data in
210
9tCLCL–165
105
ns
tLLWL
2, 3
ALE low to RD or WR low
75
140
ns
tAVWL
2, 3
Address valid to WR low or RD low
92
4tCLCL–75
45
ns
tQVWX
2, 3
Data valid to WR transition
12
tCLCL–30
0
ns
tWHQX
2, 3
Data hold after WR
17
tCLCL–25
5
ns
tQVWH
3
Data valid to WR high
162
7tCLCL–130
80
ns
tRLAZ
2, 3
RD low to address float
tWHLH
2, 3
RD or WR high to ALE high
17
6tCLCL–100
118
0
82
5tCLCL–90
0
175
3tCLCL–50
0
67
ns
60
0
3tCLCL+50
40
0
tCLCL–25
ns
tCLCL+25
5
ns
ns
0
ns
55
ns
External Clock
tCHCX
5
High time
17
17
tCLCL–tCLCX
ns
tCLCX
5
Low time
17
17
tCLCL–tCHCX
ns
tCLCH
5
Rise time
5
5
ns
tCHCL
5
Fall time
5
5
ns
tXLXL
4
Serial port clock cycle time
505
12tCLCL
360
ns
tQVXH
4
Output data setup to clock rising edge
283
10tCLCL–133
167
ns
tXHQX
4
Output data hold after clock rising edge
3
2tCLCL–80
tXHDX
4
Input data hold after clock rising edge
0
0
Shift Register
ns
0
ns
tXHDV
4
Clock rising edge to input data valid
283
10tCLCL–133
167
ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. Interfacing the SC80C31/51 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0
drivers.
4. Variable clock is specified for oscillator frequencies greater than 16MHz to 33MHz. For frequencies equal or less than 16MHz, see 16MHz
“AC Electrial Characteristics”, page 15.
1996 Aug 16
16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C31/80C51/87C51
EXPLANATION OF THE AC SYMBOLS
P – PSEN
Q – Output data
R – RD signal
t – Time
V – Valid
W – WR signal
X – No longer a valid logic level
Z – Float
Examples: tAVLL = Time for address valid to ALE low.
tLLPL= Time for ALE low to PSEN low.
Each timing symbol has five characters. The first character is always
‘t’ (= time). The other characters, depending on their positions,
indicate the name of a signal or the logical status of that signal. The
designations are:
A – Address
C – Clock
D – Input data
H – Logic level high
I – Instruction (program memory contents)
L – Logic level low, or ALE
tLHLL
ALE
tAVLL
tLLPL
tPLPH
tLLIV
tPLIV
PSEN
tLLAX
INSTR IN
A0–A7
PORT 0
tPXIZ
tPLAZ
tPXIX
A0–A7
tAVIV
PORT 2
A0–A15
A8–A15
SU00006
Figure 1. External Program Memory Read Cycle
ALE
tWHLH
PSEN
tLLDV
tLLWL
tRLRH
RD
tAVLL
tLLAX
tRLAZ
PORT 0
tRHDZ
tRLDV
tRHDX
A0–A7
FROM RI OR DPL
DATA IN
A0–A7 FROM PCL
INSTR IN
tAVWL
tAVDV
PORT 2
P2.0–P2.7 OR A8–A15 FROM DPH
A0–A15 FROM PCH
SU00007
Figure 2. External Data Memory Read Cycle
1996 Aug 16
17
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C31/80C51/87C51
ALE
tWHLH
PSEN
tWLWH
tLLWL
WR
tLLAX
tAVLL
A0–A7
FROM RI OR DPL
PORT 0
tWHQX
tQVWX
DATA OUT
A0–A7 FROM PCL
INSTR IN
tAVWL
PORT 2
P2.0–P2.7 OR A8–A15 FROM DPH
A0–A15 FROM PCH
SU00008
Figure 3. External Data Memory Write Cycle
INSTRUCTION
0
1
2
3
4
5
6
7
8
ALE
tXLXL
CLOCK
tXHQX
tQVXH
OUTPUT DATA
0
1
2
WRITE TO SBUF
3
4
5
6
7
tXHDX
tXHDV
SET TI
INPUT DATA
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
CLEAR RI
SET RI
SU00027
Figure 4. Shift Register Mode Timing
VCC–0.5
0.45V
0.7VCC
0.2VCC–0.1
tCHCL
tCHCX
tCLCH
tCLCX
tCLCL
SU00009
Figure 5. External Clock Drive
1996 Aug 16
18
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
VCC–0.5
80C31/80C51/87C51
0.2VCC+0.9
0.2VCC–0.1
0.45V
NOTE:
AC inputs during testing are driven at VCC –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’.
Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’.
SU00010
Figure 6. AC Testing Input/Output
VLOAD+0.1V
VOH–0.1V
TIMING
REFERENCE
POINTS
VLOAD
VLOAD–0.1V
VOL+0.1V
NOTE:
For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs,
and begins to float when a 100mV change from the loaded VOH/VOL level occurs. IOH/IOL ≥ ±20mA.
SU00011
Figure 7. Float Waveform
MAX ACTIVE MODE
(ICCMAX = 1.43 freq + 1.9)
45
40
35
30
TYP ACTIVE MODE
25
ICC mA
20
15
10
MAX IDLE MODE
5
TYP IDLE MODE
4MHz
8MHz
12MHz
16MHz
20MHz
24MHz
30MHz
33MHz
FREQ AT XTAL1
SU00012
Figure 8. ICC vs. FREQ
Valid only within frequency specifications of the device under test
1996 Aug 16
19
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C31/80C51/87C51
VCC
VCC
ICC
ICC
VCC
VCC
VCC
VCC
RST
RST
VCC
P0
P0
EA
EA
(NC)
XTAL2
(NC)
XTAL2
CLOCK SIGNAL
XTAL1
CLOCK SIGNAL
XTAL1
VSS
VSS
SU00719
SU00720
Figure 9. ICC Test Condition, Active Mode
All other pins are disconnected
VCC–0.5
Figure 10. ICC Test Condition, Idle Mode
All other pins are disconnected
0.7VCC
0.45V
0.2VCC–0.1
tCHCL
tCHCX
tCLCH
tCLCX
tCLCL
SU00015
Figure 11. Clock Signal Waveform for ICC Tests in Active and Idle Modes
tCLCH = tCHCL = 5ns
VCC
ICC
VCC
VCC
RST
P0
EA
(NC)
XTAL2
XTAL1
VSS
SU00016
Figure 12. ICC Test Condition, Power Down Mode
All other pins are disconnected. VCC = 2V to 5.5V
1996 Aug 16
20
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C31/80C51/87C51
EPROM CHARACTERISTICS
Program Verification
The 87C51 is programmed by using a modified Quick-Pulse
Programming algorithm. It differs from older methods in the value
used for VPP (programming supply voltage) and in the width and
number of the ALE/PROG pulses.
If security bit 2 has not been programmed, the on-chip program
memory can be read out for program verification. The address of the
program memory locations to be read is applied to ports 1 and 2 as
shown in Figure 15. The other pins are held at the ‘Verify Code Data’
levels indicated in Table 3. The contents of the address location will
be emitted on port 0. External pull-ups are required on port 0 for this
operation.
The 87C51 contains two signature bytes that can be read and used
by an EPROM programming system to identify the device. The
signature bytes identify the device as an 87C51 manufactured by
Philips Corporation.
If the encryption table has been programmed, the data presented at
port 0 will be the exclusive NOR of the program byte with one of the
encryption bytes. The user will have to know the encryption table
contents in order to correctly decode the verification data. The
encryption table itself cannot be read out.
Table 3 shows the logic levels for reading the signature bytes, and
for programming the program memory, the encryption table, and the
security bits. The circuit configuration and waveforms for quick-pulse
programming are shown in Figures 13 and 14. Figure 15 shows the
circuit configuration for normal program memory verification.
Reading the Signature Bytes
The signature bytes are read by the same procedure as a normal
verification of locations 030H and 031H, except that P3.6 and P3.7
need to be pulled to a logic low. The values are:
(030H) = 15H indicates manufactured by Philips
(031H) = 92H indicates 87C51
Quick-Pulse Programming
The setup for microcontroller quick-pulse programming is shown in
Figure 13. Note that the 87C51 is running with a 4 to 6MHz
oscillator. The reason the oscillator needs to be running is that the
device is executing internal address and program data transfers.
Program/Verify Algorithms
The address of the EPROM location to be programmed is applied to
ports 1 and 2, as shown in Figure 13. The code byte to be
programmed into that location is applied to port 0. RST, PSEN and
pins of ports 2 and 3 specified in Table 3 are held at the ‘Program
Code Data’ levels indicated in Table 3. The ALE/PROG is pulsed
low 25 times as shown in Figure 14.
Any algorithm in agreement with the conditions listed in Table 3, and
which satisfies the timing specifications, is suitable.
Erasure Characteristics
Erasure of the EPROM begins to occur when the chip is exposed to
light with wavelengths shorter than approximately 4,000 angstroms.
Since sunlight and fluorescent lighting have wavelengths in this
range, exposure to these light sources over an extended time (about
1 week in sunlight, or 3 years in room level fluorescent lighting)
could cause inadvertent erasure. For this and secondary effects,
it is recommended that an opaque label be placed over the
window. For elevated temperature or environments where solvents
are being used, apply Kapton tape Fluorglas part number 2345–5, or
equivalent.
To program the encryption table, repeat the 25 pulse programming
sequence for addresses 0 through 1FH, using the ‘Pgm Encryption
Table’ levels. Do not forget that after the encryption table is
programmed, verification cycles will produce only encrypted data.
To program the security bits, repeat the 25 pulse programming
sequence using the ‘Pgm Security Bit’ levels. After one security bit is
programmed, further programming of the code memory and
encryption table is disabled. However, the other security bit can still
be programmed.
The recommended erasure procedure is exposure to ultraviolet light
(at 2537 angstroms) to an integrated dose of at least 15W-sec/cm2.
Exposing the EPROM to an ultraviolet lamp of 12,000µW/cm2 rating
for 20 to 39 minutes, at a distance of about 1 inch, should be
sufficient.
Note that the EA/VPP pin must not be allowed to go above the
maximum specified VPP level for any amount of time. Even a narrow
glitch above that voltage can cause permanent damage to the
device. The VPP source should be well regulated and free of glitches
and overshoot.
Erasure leaves the array in an all 1s state.
Table 3. EPROM Programming Modes
RST
PSEN
ALE/PROG
EA/VPP
P2.7
P2.6
P3.7
P3.6
Read signature
MODE
1
0
1
1
0
0
0
0
Program code data
1
0
0*
VPP
1
0
1
1
Verify code data
1
0
1
1
0
0
1
1
Pgm encryption table
1
0
0*
VPP
1
0
1
0
Pgm security bit 1
1
0
0*
VPP
1
1
1
1
Pgm security bit 2
1
0
0*
VPP
1
1
0
0
NOTES:
1. ‘0’ = Valid low for that pin, ‘1’ = valid high for that pin.
2. VPP = 12.75V +0.25V.
3. VCC = 5V±10% during programming and verification.
4. *ALE/PROG receives 25 programming pulses while VPP is held at 12.75V. Each programming pulse is low for 100µs (±10µs) and high for a
minimum of 10µs.
Trademark phrase of Intel Corporation.
1996 Aug 16
21
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C31/80C51/87C51
+5V
VCC
A0–A7
P0
P1
1
RST
EA/VPP
1
P3.6
ALE/PROG
1
P3.7
87C51
XTAL2
4–6MHz
XTAL1
PGM DATA
+12.75V
25 100µs PULSES TO GROUND
PSEN
0
P2.7
1
P2.6
0
A8–A11
P2.0–P2.3
VSS
SU00017
Figure 13. Programming Configuration
25 PULSES
1
ALE/PROG:
0
10µs MIN
1
ALE/PROG:
100µs+10
0
SU00018
Figure 14. PROG Waveform
+5V
VCC
A0–A7
P0
P1
PGM DATA
1
RST
EA/VPP
1
1
P3.6
ALE/PROG
1
1
P3.7
PSEN
0
87C51
XTAL2
4–6MHz
XTAL1
P2.7
0 ENABLE
P2.6
0
P2.0–P2.3
A8–A11
VSS
SU00019
Figure 15. Program Verification
1996 Aug 16
22
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C31/80C51/87C51
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
Tamb = 21°C to +27°C, VCC = 5V±10%, VSS = 0V (See Figure 16)
SYMBOL
PARAMETER
MIN
MAX
UNIT
12.5
13.0
V
VPP
Programming supply voltage
IPP
Programming supply current
1/tCLCL
Oscillator frequency
tAVGL
Address setup to PROG low
48tCLCL
tGHAX
Address hold after PROG
48tCLCL
tDVGL
Data setup to PROG low
48tCLCL
tGHDX
Data hold after PROG
48tCLCL
tEHSH
P2.7 (ENABLE) high to VPP
48tCLCL
tSHGL
VPP setup to PROG low
10
µs
tGHSL
VPP hold after PROG
10
µs
tGLGH
PROG width
90
tAVQV
Address to data valid
48tCLCL
tELQZ
ENABLE low to data valid
48tCLCL
tEHQZ
Data float after ENABLE
0
tGHGL
PROG high to PROG low
10
P1.0–P1.7
P2.0–P2.4
4
50
mA
6
MHz
µs
110
48tCLCL
µs
PROGRAMMING*
VERIFICATION*
ADDRESS
ADDRESS
tAVQV
DATA IN
PORT 0
DATA OUT
tDVGL
tAVGL
tGHDX
tGHAX
ALE/PROG
tGLGH
tSHGL
tGHGL
tGHSL
LOGIC 1
LOGIC 1
EA/VPP
LOGIC 0
tEHSH
tELQV
tEHQZ
P2.7
ENABLE
SU00020
NOTE:
*
FOR PROGRAMMING VERIFICATION SEE FIGURE 13.
FOR VERIFICATION CONDITIONS SEE FIGURE 15.
Figure 16. EPROM Programming and Verification
1996 Aug 16
23
1996 Aug 16
853–0590B 06688
24
SEATING
PLANE
–T–
–D–
0.023 (0.58)
0.015 (0.38)
0.070 (1.78)
0.050 (1.27)
T
0.100 (2.54) BSC
E D
0.010 (0.254)
2.087 (53.01)
2.038 (51.77)
SEE NOTE 6
0.098 (2.49)
0.040 (1.02)
0.165 (4.19)
0.125 (3.18)
0.015 (0.38)
0.010 (0.25)
0.055 (1.40)
0.020 (0.51)
0.175 (4.45)
0.145 (3.68)
0.695 (17.65)
0.600 (15.24)
BSC
0.600 (15.24)
(NOTE 4)
0.620 (15.75)
0.590 (14.99)
(NOTE 4)
6. Denotes window location for EPROM products.
5. Pin numbers start with Pin #1 and continue
counterclockwise to Pin #40 when viewed
from the top.
0.225 (5.72) MAX.
0.598 (15.19)
0.571 (14.50)
2. Dimension and tolerancing per ANSI Y14. 5M-1982.
3. “T”, “D”, and “E” are reference datums on the body
and include allowance for glass overrun and meniscus
on the seal line, and lid to base mismatch.
4. These dimensions measured with the leads
constrained to be perpendicular to plane T.
NOTES:
1. Controlling dimension: Inches. Millimeters are
shown in parentheses.
0590B
PIN # 1
–E–
0.098 (2.49)
0.040 (1.02)
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C31/80C51/87C51
40-PIN (600 mils wide) CERAMIC DUAL IN-LINE (F) PACKAGE (WITH WINDOW (FA) PACKAGE)
1996 Aug 16
853-1472A 05854
25
8.13 (0.320)
7.37 (0.290)
8.13 (0.320)
7.37 (0.290)
12.7 (0.500)
NOMINAL
SEE DETAIL A
SEATING
PLANE
0.482 (0.019 + 0.002)
BASE PLANE
45 ° TYP.
4 PLACES
0.73 + 0.08 (0.029 + 0.003)
SEATING
PLANE
DETAIL A
TYP. ALL SIDES
mm/(inch)
1.02 + 0.25 (0.040 + 0.010)
1.52 (0.060) REF.
1.27 (0.050) TYP.
4.83 (0.190)
3.94 (0.155)
6
0.51 (0.02) X 45 °
6
0.38 (0.015)
0.25 (0.010)
0.15 (0.006)
0.15 (0.006) MIN.
0.25 (0.010) R MIN.
+ 5°
–10 °
DETAIL B
mm/(inch)
90°
0.508 (0.020) R MIN.
0.076 (0.003) MIN.
6. Backside solder relief is optional and
dimensions are for reference only.
5. All dimensions and tolerances include
lead trim offset and lead plating finish.
3. Dimensions do not include glass protrusion.
Glass protrusion to be 0.005 inches maximum
on each side.
4. Controlling dimension millimeters.
2. UV window is optional.
NOTES:
1. All dimensions and tolerances to conform
to ANSI Y14.5–1982.
CMOS single-chip 8-bit microcontrollers
SEE DETAIL B
SEATING
PLANE
4.83 (0.190)
3.94 (0.155)
40X
1.27 (0.050)
17.65 (0.656)
17.40 (0.685)
3 X 0.63 (0.025) R MIN.
3
16.89 (0.665)
16.00 (0.630)
17.65 (0.695)
17.40 (0.685)
3.05 (0.120)
2.29 (0.090)
1472A
2
1.02 (0.040) X 45°
CHAMFER
45
17.65 (0.695)
17.40 (0.685)
16.89 (0.665)
16.00 (0.630)
3
Philips Semiconductors
Product specification
80C31/80C51/87C51
44-PIN CERQUAD J-BEND (K) PACKAGE
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
DIP40: plastic dual in-line package; 40 leads (600 mil)
1996 Aug 16
26
80C31/80C51/87C51
SOT129-1
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
PLCC44: plastic leaded chip carrier; 44 leads
1996 Aug 16
80C31/80C51/87C51
SOT187-2
27
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C31/80C51/87C51
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
1996 Aug 16
28
SOT307-2
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
NOTES
1996 Aug 16
29
80C31/80C51/87C51
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C31/80C51/87C51
DEFINITIONS
Data Sheet Identification
Product Status
Definition
Objective Specification
Formative or in Design
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
Preliminary Specification
Preproduction Product
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Product Specification
Full Production
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work
right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only.
Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Philips Semiconductors and Philips Electronics North America Corporation register
eligible circuits under the Semiconductor Chip Protection Act.
 Copyright Philips Electronics North America Corporation 1996
All rights reserved. Printed in U.S.A.