INTEGRATED CIRCUITS 80C851/83C851 CMOS single-chip 8-bit microcontroller with on-chip EEPROM Product specification Supersedes data of 1992 Nov 25 IC20 Data Handbook 1998 Jul 03 Philips Semiconductors Product specification CMOS single-chip 8-bit microcontroller with on-chip EEPROM DESCRIPTION 80C851/83C851 FEATURES The Philips 80C851/83C851 is a high-performance microcontroller fabricated with Philips high-density CMOS technology. The 80C851/83C851 has the same instruction set as the 80C51. The Philips CMOS technology combines the high speed and density characteristics of HMOS with the low power attributes of CMOS. The Philips epitaxial substrate minimizes latch-up sensitivity. The 80C851/83C851 contains a 4k × 8 ROM with mask-programmable ROM code protection, a 128 × 8 RAM, 256 × 8 EEPROM, 32 I/O lines, two 16-bit counter/timers, a seven-source, five vector, two-priority level nested interrupt structure, a serial I/O port for either multi-processor communications, I/O expansion or full duplex UART, and on-chip oscillator and clock circuits. In addition, the 80C851/83C851 has two software selectable modes of power reduction — idle mode and power-down mode. The idle mode freezes the CPU while allowing the RAM, timers, serial port, and interrupt system to continue functioning. The power-down mode saves the RAM and EEPROM contents but freezes the oscillator, causing all other chip functions to be inoperative. • 80C51 based architecture – 4k × 8 ROM – 128 × 8 RAM – Two 16-bit counter/timers – Full duplex serial channel – Boolean processor • Non-volatile 256 × 8-bit EEPROM (electrically erasable programmable read only memory) – On-chip voltage multiplier for erase/write – 10,000 erase/write cycles per byte – 10 years non-volatile data retention – Infinite number of read cycles – User selectable security mode – Block erase capability • Mask-programmable ROM code protection • Memory addressing capability – 64k ROM and 64k RAM • Power control modes: – Idle mode – Power-down mode • CMOS and TTL compatible • 1.2 to 16MHz or 3.5 to 24MHz • Three package styles • Three temperature ranges • ROM code protection ORDERING INFORMATION PHILIPS PART ORDER NUMBER PART MARKING NORTH AMERICA PHILIPS PART ORDER NUMBER ROMless Version ROM Version ROMless Version ROM Version TEMPERATURE RANGE °C AND PACKAGE FREQ. (MHz) DRAWING NUMBER P80C851 FBP P83C851 FBP S80C851-4N40 S83C851-4N40 0 to +70, Plastic Dual In-line Package 1.2 to 16 SOT129-1 P80C851 IBP P83C851 IBP 0 to +70, Plastic Dual In-line Package 3.5 to 24 SOT129-1 P80C851 FBA P83C851 FBA 0 to +70, Plastic Leaded Chip Carrier 1.2 to 16 SOT187-1 P80C851 IBA P83C851 IBA 0 to +70, Plastic Leaded Chip Carrier 3.5 to 24 SOT187-1 P80C851 FBB P83C851 FBB 0 to +70, Plastic Quad Flat Pack 1.2 to 16 SOT307-2 P80C851 IBB P83C851 IBB 0 to +70, Plastic Quad Flat Pack 3.5 to 24 SOT307-2 P80C851 FFP P83C851 FFP S80C851-5N40 S83C851-5N40 –40 to +85, Plastic Dual In-line Package 1.2 to 16 SOT129-1 P80C851 FFA P83C851 FFA S80C851-5A44 S83C851-5A44 –40 to +85, Plastic Leaded Chip Carrier 1.2 to 16 SOT187-1 P80C851 FFB P83C851 FFB S80C851-5B44 S83C851-5B44 –40 to +85, Plastic Quad Flat Pack 1.2 to 16 SOT307-2 P80C851 FHP P83C851 FHP S80C851-6N40 S83C851-6N40 –40 to +125, Plastic Dual In-line Package 1.2 to 16 SOT129-1 P80C851 FHA P83C851 FHA S80C851-6A44 S83C851-6A44 –40 to +125, Plastic Leaded Chip Carrier 1.2 to 16 SOT187-1 P80C851 FHB P83C851 FHB S80C851-6B44 S83C851-6B44 –40 to +125, Plastic Quad Flat Pack 1.2 to 16 SOT307-2 1998 Jul 03 S80C851-4A44 S80C851-4B44 S83C851-4A44 S83C851-4B44 2 Philips Semiconductors Product specification CMOS single-chip 8-bit microcontroller with on-chip EEPROM 80C851/83C851 BLOCK DIAGRAM FREQUENCY REFERENCE XTAL2 COUNTERS T0 XTAL1 OSCILLATOR AND TIMING PROGRAM MEMORY (4K x 8 ROM) DATA MEMORY (128 x 8 RAM) 64K BYTE BUS EXPANSION CONTRTOL PROGRAMMABLE I/O T1 TWO 16-BIT TIMER/EVENT COUNTERS CPU INTERNAL INTERRUPTS INT0 INT1 CONTROL PARALLEL PORTS, ADDRESS/DATA BUS AND I/O PINS EXTERNAL INTERRUPTS LOGIC SYMBOL VDD VSS PORT 0 XTAL1 ADDRESS AND DATA BUS 1998 Jul 03 RxD TxD INT0 INT1 T0 T1 WR RD PORT 1 PORT 2 RST EA PSEN ALE PORT 3 SECONDARY FUNCTIONS XTAL2 ADDRESS BUS 3 PROG SERIAL PORT FULL DUPLEX UART SYNCHRONOUS SHIFT SERIAL IN SERIAL OUT SHARED WITH PORT 3 EEPROM (256 x 8) Philips Semiconductors Product specification CMOS single-chip 8-bit microcontroller with on-chip EEPROM PIN CONFIGURATIONS 80C851/83C851 PLASTIC LEADED CHIP CARRIER PIN FUNCTIONS P1.0 1 40 VDD P1.1 2 39 P0.0/AD0 P1.2 3 38 P0.1/AD1 P1.3 4 37 P0.2/AD2 P1.4 5 36 P0.3/AD3 P1.5 6 35 P0.4/AD4 6 1 P1.6 7 34 P0.5/AD5 33 P0.6/AD6 RST 9 32 P0.7/AD7 RxD/P3.0 10 TxD/P3.1 11 DUAL IN-LINE PACKAGE 30 ALE 39 33 PQFP 17 11 29 18 23 28 Function 34 1 PLCC Pin 31 EA 44 40 7 P1.7 8 PLASTIC QUAD FLAT PACK PIN FUNCTIONS Pin 12 Function Pin Function 22 Pin Function 1 NC* 23 NC* 1 P1.5 23 P2.5/A13 2 P1.0 24 P2.0/A8 2 P1.6 24 P2.6/A14 3 P1.1 25 P2.1/A9 3 P1.7 25 P2.7/A15 INT0/P3.2 12 29 PSEN 4 P1.2 26 P2.2/A10 4 RST 26 PSEN INT1/P3.3 13 28 P2.7/A15 5 P1.3 27 P2.3/A11 5 P3.0/RxD 27 ALE 27 P2.6/A14 6 P1.4 28 P2.4/A12 6 NC* 28 NC* T0/P3.4 14 7 P1.5 29 P2.5/A13 7 P3.1/TxD 29 EA T1/P3.5 15 26 P2.5/A13 8 P1.6 30 P2.6/A14 8 P3.2/INT0 30 P0.7/AD7 9 P1.7 31 P2.7/A15 9 P3.3/INT1 31 P0.6/AD6 WR/P3.6 16 25 P2.4/A12 10 RST 32 PSEN 10 P3.4/T0 32 P0.5/AD5 RD/P3.7 17 24 P2.3/A11 XTAL2 18 23 P2.2/A10 XTAL1 19 22 P2.1/A9 VSS 20 21 P2.0/A8 6 1 40 7 39 11 P3.0/RxD 33 ALE 11 P3.5/T1 33 P0.4/AD4 12 NC* 34 NC* 12 P3.6/WR 34 P0.3/AD3 13 P3.1/TxD 35 EA 13 P3.7RD 35 P0.2/AD2 14 P3.2/INT0 36 P0.7/AD7 14 XTAL2 36 P0.1/AD1 15 P3.3/INT1 37 P0.6/AD6 15 XTAL1 37 P0.0/AD0 16 P3.4/T0 38 P0.5/AD5 16 VSS 38 VDD 17 P3.5/T1 39 P0.4/AD4 17 NC* 39 VSS 18 P3.6/WR 40 P0.3/AD3 18 P2.0/A8 40 P1.0 19 P3.7/RD 41 P0.2/AD2 19 P2.1/A9 41 P1.1 20 XTAL2 42 P0.1/AD1 20 P2.2/A10 42 P1.2 21 XTAL1 43 P0.0/AD0 21 P2.3/A11 43 P1.3 22 VSS 44 VDD 22 P2.4/A12 44 P1.4 * NO INTERNAL CONNECTION PLASTIC LEADED CHIP CARRIER 17 29 18 28 34 44 1 33 PLASTIC QUAD FLAT PACK 11 23 12 1998 Jul 03 22 4 * NO INTERNAL CONNECTION Philips Semiconductors Product specification CMOS single-chip 8-bit microcontroller with on-chip EEPROM 80C851/83C851 PIN DESCRIPTION PIN NO. MNEMONIC DIP LCC QFP TYPE VSS 20 22 16, 39 I Ground: 0V reference. VDD 40 44 38 I Power Supply: This is the power supply voltage for normal, idle, and power-down operation. 39–32 43–36 37–30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. P1.0–P1.7 1–8 2–9 40–44, 1–3 I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). P2.0–P2.7 21–28 24–31 18–25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function register. P3.0–P3.7 10–17 11, 13–19 5, 7–13 I/O 10 11 12 13 14 15 16 17 11 13 14 15 16 17 18 19 5 7 8 9 10 11 12 13 I O I I I I O O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also serves the special features of the SC80C51 family, as listed below: RxD (P3.0): Serial input port TxD (P3.1): Serial output port INT0 (P3.2): External interrupt INT1 (P3.3): External interrupt T0 (P3.4): Timer 0 external input T1 (P3.5): Timer 1 external input WR (P3.6): External data memory write strobe RD (P3.7): External data memory read strobe RST 9 10 4 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VDD. ALE 30 33 27 I/O Address Latch Enable: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. PSEN 29 32 26 O Program Store Enable: The read strobe to external program memory. When the device is executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. EA 31 35 29 I External Access Enable: If during a RESET, EA is held at TTL, level HIGH, the CPU executes out of the internal program memory ROM provided the Program Counter is less than 4096. If during a RESET, EA is held a TTL LOW level, the CPU executes out of external program memory. EA is not allowed to float. XTAL1 19 21 15 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. XTAL2 18 20 14 O Crystal 2: Output from the inverting oscillator amplifier. P0.0–0.7 1998 Jul 03 NAME AND FUNCTION 5 Philips Semiconductors Product specification CMOS single-chip 8-bit microcontroller with on-chip EEPROM Table 1. SYMBOL 8XC851 Special Function Registers DESCRIPTION DIRECT BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION ADDRESS MSB LSB ACC* Accumulator E0H B* B register F0H DPTR: DPH DPL 80C851/83C851 Data pointer (2 bytes): High byte Low byte E7 E6 E5 E4 E3 E2 E1 RESET VALUE E0 00H 00H F7 F6 F5 F4 F3 F2 F1 F0 EF EE ED EC EB EA E9 E8 83H 82H 00H 00H EADRH# EEPROM addr reg-high F3H 80H EADRL# EEPROM addr reg-low F2H 00H ECNTRL# EEPROM control reg F6H EDAT# EEPROM data register F4H xxH ETIM# EEPROM timer register F5H 08H IP* Interrupt priority B8H IFE EEINT EWP – ECNTR L3 ECNTR L2 ECNTR L1 ECNTR 00H L0 BF BE BD BC BB BA B9 B8 – – – PS PT1 PX1 PT0 PX0 AF AE AD AC AB AA A9 A8 xxx00000B IE* Interrupt enable A8H EA – – ES ET1 EX1 ET0 EX0 P0* Port 0 80H 87 86 85 84 83 82 81 80 0xx00000B P1* Port 1 90H 97 96 95 94 93 92 91 90 FFH P2* Port 2 A0H A7 A6 A5 A4 A3 A2 A1 A0 FFH P3* Port 3 B0H B7 B6 B5 B4 B3 B2 B1 B0 FFH PCON Power control 87H SMOD – – – GF1 GF0 PD IDL 0xxx0000B D7 D6 D5 D4 D3 D2 D1 D0 PSW* Program status word D0H CY AC F0 RS1 RS0 OV – P SBUF Serial data buffer 99H 9F 9E 9D 9C 9B 9A 99 98 SM0 SM1 SM2 REN TB8 RB8 TI RI FFH 00H xxxxxxxxB SCON* Serial port control 98H SP Stack pointer 81H 8F 8E 8D 8C 8B 8A 89 88 00H TCON* Timer/counter control 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00H TMOD Timer/counter mode 89H GATE C/T M1 M0 GATE C/T M1 M0 00H TH0 Timer 0 high byte 8CH 00H TH1 Timer 1 high byte 8DH 00H TL0 Timer 0 low byte 8AH 00H 07H TL1 Timer 1 low byte 8BH * SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs. 1998 Jul 03 00H 00H 6 Philips Semiconductors Product specification CMOS single-chip 8-bit microcontroller with on-chip EEPROM The ETIM register address is F5H. Table 2 contains the values which must be written to the ETIM register by software for various oscillator frequencies (the default value is 08H after RESET). EADRH register address is F3H. The EADRL register address is F2H. EEPROM Communications between the CPU and the EEPROM is accomplished via 5 special function registers; 2 address registers (high and low byte), 1 data register for read and write operations, 1 control register, and 1 timer register to adapt the erase/write time to the clock frequency. All registers can be read and written. Figure 1 shows a block diagram of the CPU, the EEPROM and the interface. Data Register (EDAT) This register is required for read and write operations and also for row/block erase. In write mode, its contents are written to the addressed byte (for “row erase” and “block erase” the contents are don’t care). The write pulse starts all operations, except read. In read mode, EDAT contains the data of the addressed byte. The EDAT register address is F4H. Register and Functional Description The general formula is: 2ms Write time: f [kHz] Value (decimal, XTAL1 2 to be rounded up) 512 10ms Write time: Value (decimal) Timer Register (ETIM) The timer register is required to adapt the erase/write time to the oscillator frequency. The user has to ensure that the erase or write (program) time is neither too short or too long. Address Register (EADRH, EADRL) The lower byte contains the address of one of the 256 bytes. The higher byte (EADRH) is for future extensions and for addressing the security bits (see Security Facilities). The Table 2. 80C851/83C851 f XTAL1 [kHz] 2 96 Control Register (ECNTRL) See Figure 2 for a description of this register. The ECNTRL register address is F6H. Values for the Timer Register (ETIM) VALUES FOR ETIM fXTAL1 2ms WRITE TIME 1.0MHz 2.0MHz 3.0MHz 4.0MHz 5.0MHz 6.0MHz 7.0MHz 8.0MHz 9.0MHz 10.0MHz 11.0MHz 12.0MHz 13.0MHz 14.0MHz 15.0MHz 16.0MHz 10ms WRITE TIME HEX DEC HEX DEC – 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E – 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 08 13 1D 28 32 3C 47 51 5C 66 71 7B 8 19 29 40 50 60 71 81 92 102 113 123 2C 4745 . . 24.0MHz INTERRUPT CONTROL LOGIC 8 SEQUENCER MATRIX POWER-DOWN IDLE EEPROM CLOCK GENERATOR RESET CLK ECNTRL COLUMN DECODER ETIM 3 5 ROW DECODER CPU 8 EDATA INTERNAL BUS Figure 1. EEPROM Interface Block Diagram 1998 Jul 03 7 3 EADRH 8 EADRL Philips Semiconductors Product specification CMOS single-chip 8-bit microcontroller with on-chip EEPROM 7 IFE 6 5 4 EEINT EWP –– Bit ECNTRL.7 Symbol IFE ECNTRL.6 ECNTRL.5 EEINT EWP ECNTRL.4 ECCTRL.3– ECNTRL.0 80C851/83C851 3 2 1 0 ECNTRL3 ECNTRL2 ECNTRL1 ECNTRL0 Function Active high EEPROM interrupt flag: set by the sequencer or by software; reset by software. When set and enabled, this flag forces an interrupt to the same vector as the serial port interrupt (see Interrupt section). EEPROM interrupt enable: set and reset by software (active high). Erase/write in progress flag: set and reset by the sequencer (active high). When EWP is set, access to the EEPROM is not possible. EWP cannot be set or reset by software. Reserved. See table below. Operation Byte mode Row erase Page write* Page erase/write* block erase ECNTRL.3 0 1 – – 1 ECNTRL.2 0 1 – – 0 ECNTRL.1 ECNTRL.0 0 0 – – 1 0 0 – – 0 *Future products. Byte mode: Normal EEPROM mode, default mode after reset. In this mode, data can be read and written to one byte at a time. Read mode: This is the default mode when byte mode is selected. This means that the contents of the addressed byte are available in the data register. Write mode: This mode is activated by writing to the data register. The address register must be loaded first. Since the old contents are read first (by default), this allows the sequencer to decide whether an erase/write or write cycle only (data = 00H) is required. Row erase: In this mode, the addressed row is cleared. The three LSBs of EADRL are not significant, i.e. the 8 bytes addressed by EADRL are cleared in the same time normally needed to clear one byte (tROWERASE = tE = tW). For the following write modes, only the write and not the erase/write cycle is required. For example, using the row erase mode, programming 8 bytes takes tTOTOAL = tE + 8 × tW compared to tTOTAL = 8 × tE + 8 × tW (tE = tERASE ⋅ tW = tWRITE). Page write: For future products. Page erase/write: For future products. Block erase: In this mode all 256 bytes are cleared. The byte containing the security bits is also cleared. tBLOCKERASE = tE. The contents of EADRH, EADRL and EDAT are insignificant. Program Sequences and Register Contents after Reset The contents of the EEPROM registers after a Reset are the default values: EADRH = 1xxxxxxxB (security bit address) EADRL = 00H (security bit address) ETIM = 08H (minimum erase time with the lowest permissible oscillator frequency) ECNTRL = 00H (Byte mode, read) EDAT = xxH (security bit) Initialize: MOV ETIM, .. MOV EADRH, .. Read: MOV EADRL, .. MOV .., EDAT Write: MOV EADRL, .. MOV EDAT, .. Erase row: MOV EADRL, .. Row address. 3LSBs don’t care MOV ECNTRL, #0CH Erase row mode MOV EDAT, .. (EDAT) don’t care Erase block: MOV ECNTRL, 0AH Erase block mode MOV EDAT, .. (EDAT) don’t care If the security bit is to be altered, the program generally starts as follows: MOV EADRH, #80H MOV EADRL, #00H Figure 2. 1998 Jul 03 Control Register (ECNTRL) 8 Philips Semiconductors Product specification CMOS single-chip 8-bit microcontroller with on-chip EEPROM Security Facilities EEPROM Protection The EEPROM is protected using four security bits which are contained in an extra EEPROM byte at address 8000H (EADRH/EADRL). They can be set or cleared by software. To activate the EEPROM protection, the program sequence in byte mode must be as follows: MOV MOV MOV EADRH, #80H EADRL, #00H EDAT, #FFH If two or more of these bits are reset, SB = 0, the security mode is disabled and the EEPROM is not protected. If three or four bits are set, SB = 1 and the EA mode differs from the internal access mode. In this case, access to the EEPROM is only possible in one mode regardless of how the external access mode is reached (by pulling 80C851/83C851 the EA pin low or by passing the 4K boundary). For SB = 1 and “external access” only, the “block erase” mode is enabled. The program sequence has to be as follows: MOV MOV MOV MOV mode to internal access within the MOVC cycle. EADRH, #80H (security byte address) EADRL, #00H (security byte address) ECNTRL, #0AH (block erase mode) EDAT, #xxH (start block erase) All 256 data bytes, the security bits, and SB will be cleared after completing this mode (EWP = 0). SB will also be affected in byte mode when writing to the security byte (not for SB = 1 and “external access”). Figure 3 illustrates the access to SB. ROM Code Protection Since the external access mode can only be selected by pulling the EA pin low during reset, it is not possible to read the internal program memory using the MOVC instruction while executing external program memory. Furthermore, it is not possible to change this EADRH RESET EADRL RESET Additionally, a mask-programmable ROM code protection facility is available. When the program memory passes the 4K boundary using both the internal and external ROMs, it is not possible to access the internal ROM from the external program memory if the mask-programmable ROM security bit is set. An access to the lower 4K bytes of program memory using the MOVC instruction is only possible while executing internal program memory. Also the verification mode (test-mode which writes the ROM contents to a port for comparison with a reference code) is not implemented for security reasons. A different test-mode is implemented for test purposes. This mode allows every bit to be tested. However, the internal code cannot be accessed via a port. EA 8 REGISTERS EADRH AND EADRL CONTAIN THE ADDRESS OF THE SECURITY BYTE EEPROM RESET EDATA n RESET SECURITY BYTE ADDRESS AND BLOCK ERASE FINISHED EAQ SECURITY BYTE ADDRESS AND BYTE MODE FINISHED L SB SB = 1 NO YES EXTERNAL ACCESS NO YES INHIBIT ‘READ DATA REGISTER’ INHIBIT ‘WRITE DATA REGISTER’ EXCEPT (ECNTRL) = BLOCK ERASE Figure 3. EEPROM Protection (Functional and Flowchart) 1998 Jul 03 9 Philips Semiconductors Product specification CMOS single-chip 8-bit microcontroller with on-chip EEPROM (i.e., the EWP bit has to be reset before activating the idle or power-down modes; otherwise EEPROM accesses will be aborted). OSCILLATOR CHARACTERISTICS XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier. The pins can be configured for use as an on-chip oscillator, as shown in the logic symbol, page 3. INTERRUPT SYSTEM IDLE MODE In idle mode, the CPU puts itself to sleep while all of the on-chip peripherals stay active. The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. The CPU contents, the on-chip RAM, and all of the special function registers remain intact during this mode. The idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset. To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. However, minimum and maximum high and low times specified in the data sheet must be observed. RESET A reset is accomplished by holding the RST pin high for at least two machine cycles (24 oscillator periods), while the oscillator is running. To insure a good power-up reset, the RST pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. At power-up, the voltage on VDD and RST must come up at the same time for a proper start-up. POWER-DOWN MODE In the power-down mode, the oscillator is stopped and the instruction to invoke power-down is the last instruction executed. Only the contents of the on-chip RAM and EEPROM are preserved. A hardware reset is the only way to terminate the power-down mode. The control bits for the reduced power modes are in the special function register PCON. Table 3 shows the state of the I/O ports during low current operating modes. Note: Before entering the idle or power-down modes, the user has to ensure that there is no EEPROM erase/write cycle in progress Table 3. 80C851/83C851 External events and the real-time-driven on-chip peripherals require service by the CPU asynchronous to the execution of any particular section of code. To tie the asynchronous activities of these functions to normal program execution, a multiple-source, two-priority-level, nested interrupt system is provided. Interrupt response latency is from 3µs to 7µs when using a 12MHz crystal. The S83C851 acknowledges interrupt requests from 7 sources as follows: – INT0 and INT1: externally via pins 12 and 13, respectively, – Timer 0 and timer 1: from the two internal counters, – Serial port: from the internal serial I/O port or EEPROM (1 vector). Each interrupt vectors to a separate location in program memory for its service program. Each source can be individually enabled (the EEPROM interrupt can only be enabled when the serial port interrupt is enabled) or disabled and can be programmed to a high or low priority level. All enabled sources can also be globally disabled or enabled. Both external interrupts can be programmed to be level-activated and are active low to allow “wire-ORing” of several interrupt sources to one input pin. Note: The serial port and EEPROM interrupt flags must be cleared by software; all other flags are cleared by hardware. External Pin Status During Idle and Power-Down Modes MODE PROGRAM MEMORY ALE PSEN PORT 0 PORT 1 PORT 2 PORT 3 Idle Internal 1 Idle External 1 1 Data 1 Float Data Data Data Data Address Data Power-down Internal 0 Power-down External 0 0 0 Data Data Data Data Float Data Data Data RATING UNIT Storage temperature range –65 to +150 °C Voltage on any other pin to VSS ABSOLUTE MAXIMUM RATINGS1, 2, 3 PARAMETER –0.5 to +6.5 V Input or output DC current on any single I/O pin ±5 mA Power dissipation (based on package heat transfer limitations, not device power consumption) 1.0 W NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. 1998 Jul 03 10 Philips Semiconductors Product specification CMOS single-chip 8-bit microcontroller with on-chip EEPROM 80C851/83C851 DC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C (VDD = 5V ±10%), –40°C to +85°C (VDD = 5V ±10%), or –40°C to +125°C (VDD = 5V ±10%), VSS = 0V SYMBOL TEST TYPE CONDITIONS LIMITS MIN MAX UNIT VIL Input low voltage, except EA 0 to +70°C –40 to +85°C –40 to +125°C –0.5 –0.5 –0.5 0.2VDD–0.1 0.2VDD–0.15 0.2VDD–0.25 V V V VIL1 Input low voltage to EA 0 to +70°C –40 to +85°C –40 to +125°C –0.5 –0.5 –0.5 0.2VDD–0.3 0.2VDD–0.35 0.2VDD–0.45 V V V VIH Input high voltage, except XTAL1, RST 0 to +70°C –40 to +85°C –40 to +125°C 0.2VDD+0.9 0.2VDD+1.0 0.2VDD+1.0 VDD+0.5 VDD+0.5 VDD+0.5 V V V VIH1 Input high voltage, XTAL1, RST 0 to +70°C –40 to +85°C –40 to +125°C 0.7VDD 0.7VDD+0.1 0.7VD+0.1 VDD+0.5 VDD+0.5 VDD+0.5 VOL Output low voltage, ports 1, 2, 3 6 IOL = 1.6mA4 0.45 V VOL1 Output low voltage, port 0, ALE, PSEN 6 IOL = 3.2mA4 0.45 V VOH Output high voltage, ports 1, 2, 3, ALE, PSEN IOH = –60µA, IOH = –25µA, IOH = –10µA 2.4 0.75VDD 0.9VDD V V V VOH1 Output high voltage, port 0 in external bus mode5 IOH = –800µA, IOH = –300µA, IOH = –80µA 2.4 0.75VDD 0.9VDD V V V IIL Logical 0 input current, ports 1, 2, 3 0 to +70°C –40 to +85°C –40 to +125°C VIN = 0.45V –50 –75 –75 µA µA µA ITL Logical 1-to-0 transition current, ports 1, 2, 3 0 to +70°C –40 to +85°C –40 to +125°C VIN = 2.0V –650 –750 –750 µA µA µA IL1 Input leakage current, port 0, EA 0.45V<Vi<VDD ±10 µA IDD Power supply current: Active mode @ 16MHz 1 Active mode @ 24MHz 1 Idle mode @ 16MHz 2 Idle mode @ 24MHz 2 Power down mode 3 19 29 3.7 5.6 50 mA mA mA mA µA 150 kΩ RRST PARAMETER PART See note 7 Internal reset pull-down resistor 50 CIO Pin capacitance f = 1MHz 10 pF NOTES: 1. The operating supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 5ns; VIL = VSS +0.5V; VIH = VDD – 0.5V; XTAL2 not connected; EA = RST = Port 0 = VDD. 2. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 5ns; VIL = VSS +0.5V; VIH = VDD – 0.5V; XTAL2 not connected; EA = Port 0 = VDD; RST = VSS. 3. The power-down current is measured with all output pins disconnected; XTAL2 not connected; EA = Port 0 = VDD; RST = XTAL1 = VSS. 4. Capacitive loading on Port 0 and Port 2 may cause spurious noise pulses to be superimposed on the LOW level output voltage of ALE, Port 1 and Port 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make a 1-to-0 transition during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE line may exceed 0.8V. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. 5. Capacitive loading on Port 0 and Port 2 may cause the HIGH level output voltage on ALE and PSEN to momentarily fall below the 0.9VDD specification when the address bits are stabilizing. 6. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per Port pin: 10mA Maximum IOL per 8-bit port – Port 0: 26mA Ports 1, 2, and 3: 15mA 71mA. Maximum total IOL for all output pins: If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 7. See Figures 11 through 14 for IDD test conditions. 1998 Jul 03 11 Philips Semiconductors Product specification CMOS single-chip 8-bit microcontroller with on-chip EEPROM 80C851/83C851 AC ELECTRICAL CHARACTERISTICS1, 2 16 MHz Version SYMBOL FIGURE PARAMETER 16MHz CLOCK VARIABLE CLOCK MIN MIN MAX UNIT 1.2 16 MHz MAX 1/tCLCL 4 Oscillator frequency tLHLL 4 ALE pulse width 85 2tCLCL–40 ns tAVLL 4 Address valid to ALE low 8 tCLCL–55 ns tLLAX 4 Address hold after ALE low 28 tCLCL–35 ns tLLIV 4 ALE low to valid instruction in tLLPL 4 ALE low to PSEN low 23 tCLCL–40 tPLPH 4 PSEN pulse width 143 3tCLCL–45 tPLIV 4 PSEN low to valid instruction in tPXIX 4 Input instruction hold after PSEN tPXIZ 4 Input instruction float after PSEN 38 tCLCL–25 ns tAVIV 4 Address to valid instruction in 208 5tCLCL–105 ns tPLAZ 4 PSEN low to address float 10 10 ns tRLRH 5 RD pulse width 275 6tCLCL–100 ns tWLWH 5 WR pulse width 275 6tCLCL–100 ns tRLDV 5 RD low to valid data in tRHDX 5 Data hold after RD tRHDZ 5 Data float after RD 55 2tCLCL–70 ns tLLDV 5 ALE low to valid data in 350 8tCLCL–150 ns tAVDV 5 Address to valid data in 398 9tCLCL–165 ns tLLWL 5, 6 ALE low to RD or WR low 138 3tCLCL+50 ns tAVWL 5, 6 Address valid to RD or WR low 120 4tCLCL–130 ns tQVWH 6 Data setup time before WR 288 7tCLCL–150 ns tQVWX 6 Data valid to WR transition 3 tCLCL–60 ns tWHQX 6 Data hold after WR 13 tCLCL–50 tRLAZ 5 RD low to address float tWHLH 5, 6 150 4tCLCL–100 83 0 ns ns ns 3tCLCL–105 0 ns ns Data Memory 148 0 5tCLCL–165 0 238 3tCLCL–50 0 RD or WR high to ALE high 23 103 tCLCL–40 ns ns ns 0 ns tCLCL+40 ns External Clock tCHCX 8 High time 20 20 tCLCX 8 Low time 20 20 ns tCLCH 8 Rise time 20 20 ns tCHCL 8 Fall time 20 20 ns ns Erase/write timer constant3 tE/W Erase/write cycle time 4 20 4 20 ms tE Erase time 2 10 2 10 ms tW Write time 2 10 2 10 tS Data retention time4 10 10 years NE/W Erase/write cycles5 10,000 10,000 cycles ms NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. The power-off fall-time of VDD must be less than 1ms to prevent an overwrite pulse from being generated in the EEPROM which can cause spurious parasitic writing to EEPROM cells. If the VDD power-off full-time is greater than 1ms, a power-off reset signal should be generated to prevent this condition from occurring. 4. Test condition: Tamb = +55°C. 5. Number of erase/write cycles for each EEPROM byte. 1998 Jul 03 12 Philips Semiconductors Product specification CMOS single-chip 8-bit microcontroller with on-chip EEPROM 80C851/83C851 AC ELECTRICAL CHARACTERISTICS1, 2 24 MHz Version SYMBOL FIGURE PARAMETER 24MHz CLOCK VARIABLE CLOCK MIN MIN MAX UNIT 3.5 24 MHz MAX 1/tCLCL 4 Oscillator frequency tLHLL 4 ALE pulse width 43 2tCLCL–40 ns tAVLL 4 Address valid to ALE low 17 tCLCL–25 ns tLLAX 4 Address hold after ALE low 17 tCLCL–25 ns tLLIV 4 ALE low to valid instruction in tLLPL 4 ALE low to PSEN low 17 tCLCL–25 tPLPH 4 PSEN pulse width 80 3tCLCL–45 tPLIV 4 PSEN low to valid instruction in tPXIX 4 Input instruction hold after PSEN tPXIZ 4 Input instruction float after PSEN 17 tCLCL–25 ns tAVIV 4 Address to valid instruction in 128 5tCLCL–80 ns tPLAZ 4 PSEN low to address float 10 10 ns tRLRH 5 RD pulse width 150 6tCLCL–100 ns tWLWH 5 WR pulse width 150 6tCLCL–100 ns tRLDV 5 RD low to valid data in tRHDX 5 Data hold after RD tRHDZ 5 Data float after RD 55 2tCLCL–28 ns tLLDV 5 ALE low to valid data in 183 8tCLCL–150 ns tAVDV 5 Address to valid data in 210 9tCLCL–165 ns tLLWL 5, 6 ALE low to RD or WR low 75 3tCLCL+50 ns tAVWL 5, 6 Address valid to RD or WR low 92 4tCLCL–75 ns tQVWH 6 Data setup time before WR 162 7tCLCL–130 ns tQVWX 6 Data valid to WR transition 12 tCLCL–30 ns tWHQX 6 Data hold after WR 17 tCLCL–25 tRLAZ 5 RD low to address float tWHLH 5, 6 102 4tCLCL–65 65 0 ns ns ns 3tCLCL–60 0 ns ns Data Memory 118 0 5tCLCL–90 0 175 3tCLCL–50 0 RD or WR high to ALE high 17 67 tCLCL–25 ns ns ns 0 ns tCLCL+25 ns External Clock tCHCX 8 High time 17 17 tCLCX 8 Low time 17 17 ns tCLCH 8 Rise time 5 20 ns tCHCL 8 Fall time 5 20 ns ns Erase/write timer constant3 tE/W Erase/write cycle time 4 20 4 20 ms tE Erase time 2 10 2 10 ms tW Write time 2 10 2 10 tS Data retention time4 10 10 years NE/W Erase/write cycles5 10,000 10,000 cycles ms NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. The power-off fall-time of VDD must be less than 1ms to prevent an overwrite pulse from being generated in the EEPROM which can cause spurious parasitic writing to EEPROM cells. If the VDD power-off full-time is greater than 1ms, a power-off reset signal should be generated to prevent this condition from occurring. 4. Test condition: Tamb = +55°C. 5. Number of erase/write cycles for each EEPROM byte. 1998 Jul 03 13 Philips Semiconductors Product specification CMOS single-chip 8-bit microcontroller with on-chip EEPROM 80C851/83C851 L – Logic level low, or ALE P – PSEN Q – Output data R – RD signal t – Time V – Valid W – WR signal X – No longer a valid logic level Z – Float Examples: tAVLL = Time for address valid to ALE low. tLLPL = Time for ALE low to PSEN low. EXPLANATION OF THE AC SYMBOLS Each timing symbol has five characters. The first character is always ‘t’ (= time). The other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. The designations are: A – Address C – Clock D – Input data H – Logic level high I – Instruction (program memory contents) tLHLL ALE tAVLL tLLPL tPLPH tLLIV tPLIV PSEN tLLAX tPXIZ tPLAZ tPXIX INSTR IN A0–A7 PORT 0 A0–A7 tAVIV PORT 2 A8–A15 A8–A15 Figure 4. External Program Memory Read Cycle ALE tWHLH PSEN tLLDV tLLWL tRLRH RD tAVLL tLLAX tRLAZ PORT 0 tRHDZ tRLDV tRHDX A0–A7 FROM RI OR DPL DATA IN A0–A7 FROM PCL tAVWL tAVDV PORT 2 P2.0–P2.7 OR A8–A15 FROM DPH Figure 5. External Data Memory Read Cycle 1998 Jul 03 14 A8–A15 FROM PCH INSTR IN Philips Semiconductors Product specification CMOS single-chip 8-bit microcontroller with on-chip EEPROM 80C851/83C851 ALE tWHLH PSEN tWLWH tLLWL WR tAW tLLAX tAVLL A0–A7 FROM RI OR DPL PORT 0 tWHQX tQVWX tQVWH DATA OUT A0–A7 FROM PCL INSTR IN tAVWL PORT 2 P2.0–P2.7 OR A8–A15 FROM DPH A8–A15 FROM PCH Figure 6. External Data Memory Write Cycle ONE MACHINE CYCLE S1 P1 P2 S2 P1 P2 S3 P1 ONE MACHINE CYCLE S4 P2 P1 S5 P2 P1 P2 S6 P1 P2 S1 P1 P2 S2 P1 P2 S3 P1 P2 S4 P1 P2 S5 P1 P2 S6 P1 P2 XTAL1 INPUT ALE PSEN RD WR EXTERNAL PROGRAM MEMORY FETCH BUS PORT 0 DATA ADDRESS FLOAT FLOAT DATA PORT 2 (EXTERNAL) PORT OUTPUT FLOAT ADDRESS FLOAT DATA ADDRESS FLOAT FLOAT DATA ADDRESS FLOAT ADDRESS TRANSITIONS OLD DATA NEW DATA PORT INPUT SAMPLING TIME OF I/O PORT PINS DURING INPUT (INCLUDING INT0 AND INT1) SERIAL PORT (SHIFT CLOCK) Figure 7. Instruction Timing 1998 Jul 03 15 FLOAT Philips Semiconductors Product specification CMOS single-chip 8-bit microcontroller with on-chip EEPROM Table 4. 80C851/83C851 External Clock Drive XTAL1 VARIABLE CLOCK f = 1.2 – 16MHz SYMBOL PARAMETER VARIABLE CLOCK f = 3.5 – 24MHz MIN MAX MIN MAX UNIT tCLCL Oscillator clock period 63 833 42 286 ns tHIGH HIGH time 20 tCLCL – tLOW 17 tCLCL – tLOW ns tLOW LOW time 20 tCLCL – tHIGH 17 tCLCL – tHIGH ns tr Rise time – 20 – 5 ns tf Fall time – 20 – 5 ns tCY Cycle time1 0.75 10 0.5 3.43 s NOTE: 1. tCY = 12 tCLCL. VDD–0.5 0.45V 2.4V 2.0V 0.7VDD 0.2VDD–0.1 tCHCL tCHCX tCLCH tCLCX 0.8V 0.45V NOTE: AC inputs during testing are driven at 2.4V for a logic ‘1’ and 0.45V for a logic ‘0’. Timing measurements are made at 2.0V min for a logic ‘1’ and 0.8V for a logic ‘0’. tCLCL Figure 8. External Clock Drive Figure 9. AC Testing Input/Output VLOAD+0.1V TIMING REFERENCE POINTS VLOAD VLOAD–0.1V VOH–0.1V VOL+0.1V NOTE: For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs, and begins to float when a 100mV change from the loaded VOH/VOL level occurs. IOH/IOL ≥ ± 20mA. Figure 10. Float Waveform 1998 Jul 03 16 Philips Semiconductors Product specification CMOS single-chip 8-bit microcontroller with on-chip EEPROM 80C851/83C851 VDD VDD IDD IDD VDD VDD VDD VDD RST VDD RST P0 P0 EA EA (NC) XTAL2 (NC) XTAL2 CLOCK SIGNAL XTAL1 CLOCK SIGNAL XTAL1 VSS VSS Figure 11. IDD Test Condition, Active Mode All other pins are disconnected Figure 12. IDD Test Condition, Idle Mode All other pins are disconnected VDD IDD VDD RST VDD–0.5 0.5V tCHCL P0 tCHCX tCLCH tCLCX VDD EA (NC) tCLCL XTAL2 XTAL1 VSS Figure 13. Clock Signal Waveform for IDD Tests in Active and Idle Modes tCLCH = tCHCL = 5ns 1998 Jul 03 Figure 14. IDD Test Condition, Power Down Mode All other pins are disconnected. VDD = 2V to 5.5V 17 Philips Semiconductors Product specification CMOS single-chip 8-bit microcontroller with on-chip EEPROM DIP40: plastic dual in-line package; 40 leads (600 mil) 1998 Jul 03 18 80C851/83C851 SOT129-1 Philips Semiconductors Product specification CMOS single-chip 8-bit microcontroller with on-chip EEPROM PLCC44: plastic leaded chip carrier; 44 leads 1998 Jul 03 80C851/83C851 SOT187-2 19 Philips Semiconductors Product specification CMOS single-chip 8-bit microcontroller with on-chip EEPROM 80C851/83C851 QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm 1998 Jul 03 20 SOT307-2 Philips Semiconductors Product specification CMOS single-chip 8-bit microcontroller with on-chip EEPROM NOTES 1998 Jul 03 21 80C851/83C851 Philips Semiconductors Product specification CMOS single-chip 8-bit microcontroller with on-chip EEPROM 80C851/83C851 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Date of release: 09-98 Document order number: 1998 Jul 03 22 9397 750 04368