PD- 95146
IRFB4710PbF
IRFS4710PbF
IRFSL4710PbF
HEXFET® Power MOSFET
Applications
l High frequency DC-DC converters
l Motor Control
l Uninterrutible Power Supplies
l Lead-Free
Benefits
l Low Gate-to-Drain Charge to Reduce
Switching Losses
l Fully Characterized Capacitance Including
Effective COSS to Simplify Design, (See
App. Note AN1001)
l Fully Characterized Avalanche Voltage
and Current
VDSS
100V
RDS(on) max
ID
0.014Ω
75A
D2Pak
IRFS4710
TO-220AB
IRFB4710
TO-262
IRFSL4710
Absolute Maximum Ratings
Parameter
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TA = 25°C
PD @TC = 25°C
VGS
dv/dt
TJ
TSTG
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
Power Dissipation
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Mounting torqe, 6-32 or M3 screw
Max.
Units
75
53
300
3.8
200
1.4
± 20
8.2
-55 to + 175
A
W
W/°C
V
V/ns
°C
300 (1.6mm from case )
10 lbf•in (1.1N•m)
Thermal Resistance
Parameter
RθJC
RθCS
RθJA
RθJA
Notes
Junction-to-Case
Case-to-Sink, Flat, Greased Surface
Junction-to-Ambient
Junction-to-Ambient
through
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Typ.
Max.
–––
0.50
–––
–––
0.74
–––
62
40
Units
°C/W
are on page 11
1
04/22/04
IRFB/IRFS/IRFL4710PbF
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Drain-to-Source Breakdown Voltage
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient
RDS(on)
Static Drain-to-Source On-Resistance
VGS(th)
Gate Threshold Voltage
V(BR)DSS
IDSS
Drain-to-Source Leakage Current
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Min.
100
–––
–––
3.5
–––
–––
–––
–––
Typ.
–––
0.11
0.011
–––
–––
–––
–––
–––
Max. Units
Conditions
–––
V
VGS = 0V, ID = 250µA
––– V/°C Reference to 25°C, ID = 1mA
0.014
Ω
VGS = 10V, ID = 45A
5.5
V
VDS = VGS, ID = 250µA
1.0
VDS = 95V, VGS = 0V
µA
250
VDS = 80V, VGS = 0V, TJ = 150°C
100
VGS = 20V
nA
-100
VGS = -20V
Dynamic @ TJ = 25°C (unless otherwise specified)
gfs
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Coss
Coss
Coss eff.
Parameter
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
Output Capacitance
Effective Output Capacitance
Min.
35
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Typ.
–––
110
43
40
35
130
41
38
6160
440
250
1580
280
430
Max. Units
Conditions
–––
S
VDS = 50V, ID = 45A
170
ID = 45A
–––
nC
VDS = 50V
–––
VGS = 10V,
–––
VDD = 50V
–––
ID = 45A
ns
–––
R G = 4.5Ω
–––
VGS = 10V
–––
VGS = 0V
–––
VDS = 25V
–––
pF
ƒ = 1.0MHz
–––
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
–––
VGS = 0V, VDS = 80V, ƒ = 1.0MHz
–––
VGS = 0V, VDS = 0V to 80V
Avalanche Characteristics
Parameter
EAS
IAR
EAR
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Typ.
Max.
Units
–––
–––
–––
190
45
20
mJ
A
mJ
Diode Characteristics
IS
ISM
VSD
trr
Qrr
ton
2
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
75
––– –––
showing the
A
G
integral reverse
––– ––– 300
S
p-n junction diode.
––– ––– 1.3
V
TJ = 25°C, IS = 45A, VGS = 0V
––– 74 110
ns
TJ = 25°C, IF = 45A
––– 180 260
nC
di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
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IRFB/IRFS/IRFL4710PbF
1000
1000
VGS
15V
12V
10V
8.0V
7.5V
7.0V
6.5V
BOTTOM 6.0V
100
100
10
1
6.0V
0.1
20µs PULSE WIDTH
T = 25 C
°
J
0.01
0.1
1
10
100
10
TJ = 25 ° C
1
V DS = 50V
20µs PULSE WIDTH
10.0
VGS , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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R DS(on) , Drain-to-Source On Resistance
(Normalized)
I D , Drain-to-Source Current (A)
TJ = 175 ° C
9.0
1
10
100
Fig 2. Typical Output Characteristics
3.0
8.0
°
J
VDS , Drain-to-Source Voltage (V)
1000
7.0
20µs PULSE WIDTH
T = 175 C
1
0.1
Fig 1. Typical Output Characteristics
0.1
6.0
6.0V
10
VDS , Drain-to-Source Voltage (V)
100
VGS
15V
12V
10V
8.0V
7.5V
7.0V
6.5V
BOTTOM 6.0V
TOP
I D , Drain-to-Source Current (A)
I D , Drain-to-Source Current (A)
TOP
ID = 75A
2.5
2.0
1.5
1.0
0.5
0.0
-60 -40 -20
VGS = 10V
0
20 40 60 80 100 120 140 160 180
TJ , Junction Temperature ( °C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRFB/IRFS/IRFL4710PbF
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
C, Capacitance(pF)
8000
Coss = Cds + Cgd
Ciss
6000
4000
2000
Coss
VGS , Gate-to-Source Voltage (V)
20
10000
ID = 45A
16
12
8
4
FOR TEST CIRCUIT
SEE FIGURE 13
Crss
0
1
10
0
100
0
40
1000
ID , Drain-to-Source Current (A)
ISD , Reverse Drain Current (A)
1000
100
TJ = 175 ° C
10
TJ = 25 ° C
0.1
0.0
V GS = 0 V
0.4
0.8
1.2
VSD ,Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
120
160
200
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
1
80
QG , Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)
4
VDS = 80V
VDS = 50V
VDS = 20V
1.6
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100
100µsec
10
1msec
1
0.1
Tc = 25°C
Tj = 175°C
Single Pulse
1
10msec
10
100
1000
VDS , Drain-toSource Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRFB/IRFS/IRFL4710PbF
80
VDS
VGS
I D , Drain Current (A)
D.U.T.
RG
60
RD
+
-VDD
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
40
Fig 10a. Switching Time Test Circuit
20
VDS
90%
0
25
50
75
100
125
150
175
TC , Case Temperature ( ° C)
10%
VGS
Fig 9. Maximum Drain Current Vs.
Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
Thermal Response (Z thJC )
1
D = 0.50
0.20
0.1
0.10
P DM
0.05
0.02
0.01
0.01
0.00001
SINGLE PULSE
(THERMAL RESPONSE)
t1
t2
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRFB/IRFS/IRFL4710PbF
D R IV E R
L
VD S
D .U .T
RG
+
- VD D
IA S
2V0GS
V
tp
A
0 .0 1 Ω
Fig 12a. Unclamped Inductive Test Circuit
V (B R )D SS
tp
EAS , Single Pulse Avalanche Energy (mJ)
350
1 5V
TOP
300
BOTTOM
250
ID
18A
32A
45A
200
150
100
50
0
25
50
75
100
125
150
175
Starting TJ , Junction Temperature ( °C)
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
IAS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
QG
10 V
50KΩ
12V
QGS
.2µF
.3µF
QGD
D.U.T.
VG
+
V
- DS
VGS
3mA
Charge
Fig 13a. Basic Gate Charge Waveform
6
IG
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
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IRFB/IRFS/IRFL4710PbF
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
-
-
+
RG
•
•
•
•
Driver Gate Drive
P.W.
+
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
Period
D=
-
VDD
P.W.
Period
VGS=10V
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFET® Power MOSFETs
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7
IRFB/IRFS/IRFL4710PbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
2 .8 7 (.1 1 3 )
2 .6 2 (.1 0 3 )
1 0 .5 4 (.4 1 5 )
1 0 .2 9 (.4 0 5 )
-B -
3 .7 8 (.1 4 9 )
3 .5 4 (.1 3 9 )
4 .6 9 (.1 8 5 )
4 .2 0 (.1 6 5 )
-A -
1 .3 2 (.0 5 2 )
1 .2 2 (.0 4 8 )
6 .4 7 (.2 5 5 )
6 .1 0 (.2 4 0 )
4
1 5 .24 ( .6 0 0 )
1 4 .84 ( .5 8 4 )
LEAD ASSIGNMENTS
1 .1 5 (.0 4 5 )
M IN
1
2
3
4- DRAIN
1 4 .0 9 (.5 5 5 )
1 3 .4 7 (.5 3 0 )
1 .4 0 (.0 5 5 )
1 .1 5 (.0 4 5 )
4- COLLECTOR
4 .0 6 ( .1 6 0 )
3 .5 5 ( .1 4 0 )
3X
3X
L E A D A S S IG N M E N T S
IGBTs, CoPACK
1 - GATE
2
D
R
A
IN
1- GATE
1- GATE
3 - S O U R C E 2- COLLECTOR
2- DRAIN
3- EMITTER
3- SOURCE
4 - D R A IN
HEXFET
0 .9 3 (.0 3 7 )
0 .6 9 (.0 2 7 )
0 .3 6 (.0 1 4 )
3X
M
B A M
0 .5 5 (.0 2 2 )
0 .4 6 (.0 1 8 )
2 .9 2 (.1 1 5 )
2 .6 4 (.1 0 4 )
2 .5 4 (.1 0 0 )
2X
N O TE S :
1 D IM E N S IO N IN G & T O L E R A N C IN G P E R A N S I Y 1 4 .5 M , 1 9 8 2 .
3 O U TL IN E C O N F O R M S TO J E D E C O U T L IN E TO -2 2 0 A B .
2 C O N T R O L L IN G D IM E N S IO N : IN C H
4 H E A T S IN K & L E A D M E A S U R E M E N TS D O NO T IN C L U D E B U R R S .
TO-220AB Part Marking Information
E XAMPL E : T HIS IS AN IR F1010
LOT CODE 1789
AS S E MB LE D ON WW 19, 1997
IN T HE AS S E MBL Y L INE "C"
Note: "P" in assembly line
position indicates "Lead-Free"
INT E RNAT IONAL
RE CT IF IE R
L OGO
AS S E MB LY
LOT CODE
8
PAR T NU MB E R
DAT E CODE
YE AR 7 = 1997
WE E K 19
L INE C
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IRFB/IRFS/IRFL4710PbF
D2Pak Package Outline
Dimensions are shown in millimeters (inches)
D2Pak Part Marking Information (Lead-Free)
T H I S IS AN IR F 53 0S WIT H
L OT COD E 80 24
AS S E MB L E D ON WW 0 2, 20 00
IN T H E AS S E MB L Y L INE "L "
IN T E R N AT ION AL
R E CT IF IE R
L OGO
N ote: "P " in as s embly line
pos ition indicates "L ead-F ree"
P AR T N U MB E R
F 53 0S
AS S E MB L Y
L OT COD E
D AT E COD E
YE AR 0 = 2 00 0
WE E K 02
L IN E L
OR
IN T E R N AT ION AL
R E CT IF IE R
L OGO
AS S E MB L Y
L OT COD E
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P AR T N U MB E R
F 530 S
D AT E COD E
P = D E S IGN AT E S L E AD -F R E E
P R OD U CT (OP T ION AL )
Y E AR 0 = 2000
WE E K 02
A = AS S E MB L Y S IT E COD E
9
IRFB/IRFS/IRFL4710PbF
TO-262 Package Outline
TO-262 Part Marking Information
E XAMPL E : T H IS IS AN IR L 3103L
L OT CODE 1789
AS S E MB L E D ON WW 19, 1997
IN T H E AS S E MB L Y L INE "C"
Note: "P " in as s embly line
pos ition indicates "L ead-F ree"
INT E R NAT IONAL
R E CT IF IE R
L OGO
AS S E MB L Y
L OT CODE
PAR T NU MB E R
DAT E CODE
YE AR 7 = 1997
WE E K 19
L INE C
OR
INT E R NAT IONAL
R E CT IF IE R
L OGO
AS S E MB L Y
L OT CODE
10
PAR T NU MB E R
DAT E CODE
P = DE S IGNAT E S L E AD-F R E E
PR ODU CT (OPT IONAL )
YE AR 7 = 1997
WE E K 19
A = AS S E MB L Y S IT E CODE
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IRFB/IRFS/IRFL4710PbF
D2Pak Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR R
1 .60 (.0 6 3 )
1 .50 (.0 5 9 )
1 .6 0 (.0 6 3 )
1 .5 0 (.0 5 9 )
4 .10 (.16 1 )
3 .90 (.15 3 )
F E E D D I R E C T IO N
1 1 .6 0 (.4 5 7 )
1 1 .4 0 (.4 4 9 )
1 .8 5 (.07 3 )
1 .6 5 (.06 5 )
0 .3 6 8 (.0 1 4 5 )
0 .3 4 2 (.0 1 3 5 )
1 5 .4 2 (.6 0 9 )
1 5 .2 2 (.6 0 1 )
2 4 .3 0 (.9 5 7 )
2 3 .9 0 (.9 4 1 )
TR L
1 .7 5 (. 0 6 9 )
1 .2 5 (. 0 4 9 )
1 0 .9 0 (.4 2 9 )
1 0 .7 0 (.4 2 1 )
4 .7 2 (.1 3 6 )
4 .5 2 (.1 7 8 )
1 6 .1 0 ( .6 3 4 )
1 5 .9 0 ( .6 2 6 )
F E E D D IR E C T I O N
1 3 .5 0 (.5 3 2 )
1 2 .8 0 (.5 0 4 )
2 7 .40 (1 .0 7 9)
2 3 .90 (.9 4 1 )
4
330.00
(14.173)
M AX .
6 0 .0 0 (2 .3 6 2)
M IN .
N O TES :
1 . C O M F O R M S T O E IA- 4 1 8.
2 . C O N T R O L L IN G D IM E N S IO N : M ILL IM E T E R .
3 . D IM E N S IO N M E A S U R E D @ H U B .
4 . IN C L U D E S F L A N G E D IS T O R T IO N @ O U T E R E D G E .
26.40 (1.039)
24.40 (.961)
3
3 0 .4 0 (1 .19 7 )
M AX.
4
Notes:
Repetitive rating; pulse width limited by
Pulse width ≤ 400µs; duty cycle ≤ 2%.
Starting TJ = 25°C, L = 190µH
Coss eff. is a fixed capacitance that gives the same charging time
max. junction temperature.
RG = 25Ω, IAS = 45A, VGS = 10V
as Coss while VDS is rising from 0 to 80% VDSS
ISD ≤ 45A, di/dt ≤ 420A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C
This is only applied to TO-220AB package
This is applied to D2Pak, when mounted on 1" square PCB ( FR-4 or G-10 Material ).
For recommended footprint and soldering techniques refer to application note #AN-994.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.04/04
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11
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/