INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT4075 Triple 3-input OR gate Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification Triple 3-input OR gate 74HC/HCT4075 FEATURES GENERAL DESCRIPTION • Output capability: standard The 74HC/HCT4075 are high-speed Si-gate CMOS devices and are pin compatible with the “4075” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. • ICC category: SSI The 74HC/HCT4075 provide the 3-input OR function. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC tPHL/ tPLH propagation delay nA, nB, nC to nY CI CPD CL = 15 pF; VCC = 5 V 8 10 ns input capacitance 3.5 3.5 pF power dissipation capacitance per gate notes 1 and 2 28 32 pF Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. December 1990 HCT 2 Philips Semiconductors Product specification Triple 3-input OR gate 74HC/HCT4075 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 3, 1, 11 1A to 3A data inputs 4, 2, 12 1B to 3B data inputs 5, 8, 13 1C to 3C data inputs 6, 9, 10 1Y to 3Y data outputs 7 GND ground (0 V) 14 VCC positive supply voltage Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. FUNCTION TABLE INPUTS OUTPUT nA nB nC nY L H X X L X H X L X X H L H H H Notes 1. H = HIGH voltage level L = LOW voltage level X = don’t care Fig.4 Functional diagram. December 1990 Fig.5 Logic diagram (one gate). 3 Philips Semiconductors Product specification Triple 3-input OR gate 74HC/HCT4075 DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: SSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 −40 to +85 −40 to +125 UNIT V WAVEFORMS CC (V) min. typ. max. min. max. min. max. tPHL/ tPLH propagation delay nA, nB, nC to nY 28 10 8 100 20 17 125 25 21 150 30 26 ns 2.0 4.5 6.0 Fig.6 tTHL/ tTLH output transition time 19 7 6 75 15 13 95 19 16 110 22 19 ns 2.0 4.5 6.0 Fig.6 December 1990 4 Philips Semiconductors Product specification Triple 3-input OR gate 74HC/HCT4075 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: SSI Note to HCT types The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD COEFFICIENT nA, nB, nC 1.50 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HCT SYMBOL PARAMETER +25 −40 to +85 −40 to +125 UNIT V WAVEFORMS CC (V) min. typ. max. min. max. min. max. tPHL/ tPLH propagation delay nA, nB, nC to nY 12 24 30 36 ns 4.5 Fig.6 tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Fig.6 AC WAVEFORMS (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the input (nA, nB, nC) to output (nY) propagation delays and the output transition times. PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. December 1990 5