PHILIPS 74HCT297

INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT297
Digital phase-locked-loop filter
Product specification
File under Integrated Circuits, IC06
September 1993
Philips Semiconductors
Product specification
Digital phase-locked-loop filter
74HC/HCT297
components. The accuracy of the digital
phase-locked-loop (DPLL) is not affected by VCC and
temperature variations but depends solely on accuracies
of the K-clock, I/D-clock and loop propagation delays.
FEATURES
• Digital design avoids analog compensation errors
• Easily cascadable for higher order loops
• Useful frequency range:
The phase detector generates an error signal waveform
that, at zero phase error, is a 50% duty factor square wave.
At the limits of linear operation, the phase detector output
will be either HIGH or LOW all of the time depending on the
direction of the phase error (φIN − φOUT). Within these limits
the phase detector output varies linearly with the input
phase error according to the gain kd, which is expressed in
terms of phase detector output per cycle or phase error.
The phase detector output can be defined to vary between
± 1 according to the relation:
– DC to 55 MHz typical (K-clock)
– DC to 35 MHz typical (I/D-clock)
• Dynamically variable bandwidth
• Very narrow bandwidth attainable
• Power-on reset
• Output capability: standard/bus driver
• ICC category: MSI
% HIGH ˙˙– % LOW
phase detector output = ------------------------------------------------ .
100
GENERAL DESCRIPTION
The 74HC/HCT297 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The output of the phase detector will be kdφe, where the
phase error φe = φIN − φOUT.
EXCLUSIVE-OR phase detectors (XORPD) and
edge-controlled phase detectors (ECPD) are commonly
used digital types. The ECPD is more complex than the
XORPD logic function but can be described generally as a
circuit that changes states on one of the transitions of its
inputs. The gain (kd) for an XORPD is 4 because its output
remains HIGH (XORPDOUT = 1) for a phase error of 1/4
cycle.
Similarly, kd for the ECPD is 2 since its output remains
HIGH for a phase error of 1/2 cycle. The type of phase
detector will determine the zero-phase-error point, i.e., the
phase separation of the phase detector inputs for a
φe defined to be zero. For the basic DPLL system of
Fig.6 φe = 0 when the phase detector output is a square
wave.
The 74HC/HCT297 are designed to provide a simple,
cost-effective solution to high-accuracy, digital,
phase-locked-loop applications. These devices contain all
the necessary circuits, with the exception of the
divide-by-n counter, to build first order
phase-locked-loops.
Both EXCLUSIVE-OR (XORPD) and edge-controlled
(ECPD) phase detectors are provided for maximum
flexibility. The input signals for the EXCLUSIVE-OR phase
detector must have a 50% duty factor to obtain the
maximum lock-range.
Proper partitioning of the loop function, with many of the
building blocks external to the package, makes it easy for
the designer to incorporate ripple cancellation (see Fig.7)
or to cascade to higher order phase-locked-loops.
The XORPD inputs are 1/4 cycle out-of-phase for zero
phase error. For the ECPD, φe = 0 when the inputs are 1/2
cycle out-of-phase.
The length of the up/down K-counter is digitally
programmable according to the K-counter function table.
With, A, B, C and D all LOW, the K-counter is disabled.
With A HIGH and B, C and D LOW, the K-counter is only
three stages long, which widens the bandwidth or capture
range and shortens the lock time of the loop. When A, B,
C and D are all programmed HIGH, the K-counter
becomes seventeen stages long, which narrows the
bandwidth or capture range and lengthens the lock time.
Real-time control of loop bandwidth by manipulating the A
to D inputs can maximize the overall performance of the
digital phase-locked loop.
The phase detector output controls the up/down input to
the K-counter. The counter is clocked by input frequency
Mfc, which is a multiple M of the loop centre frequency fc.
When the K-counter recycles up, it generates a carry
pulse. Recycling while counting down generates a borrow
pulse. If the carry and the borrow outputs are conceptually
combined into one output that is positive for a carry and
negative for a borrow, and if the K-counter is considered as
a frequency divider with the ratio Mfc/K, the output of the
K-counter will equal the input frequency multiplied by the
division ratio. Thus the output from the K-counter is
(kdφeMfc) / K.
The “297” can perform the classic first-order
phase-locked-loop function without using analog
September 1993
2
Philips Semiconductors
Product specification
Digital phase-locked-loop filter
74HC/HCT297
The carry and borrow pulses go to the
increment/decrement (I/D) circuit which, in the absence of
any carry or borrow pulses has an output that is 1/2 of the
input clock (I/DCP). The input clock is just a multiple, 2N, of
the loop centre frequency. In response to a carry or borrow
pulse, the I/D circuit will either add or delete a pulse at
I/DOUT. Thus the output of the I/D circuit will be
Nfc + (kd∅eMfc)/2K.
The output of the N-counter (or the output of the
phase-locked-loop) is thus: fo = fc + (kdφeMfc)/2KN.
If this result is compared to the equation for a first-order
analog phase-locked-loop, the digital equivalent of the
gain of the VCO is just Mfc/2KN or fc/K for M = 2N.
Thus the simple first-order phase-locked-loop with an
adjustable K-counter is the equivalent of an analog
phase-locked-loop with a programmable VCO gain.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
tPHL/ tPLH
fmax
PARAMETER
CONDITIONS
UNIT
HC
HCT
I/DCP to I/DOUT
15
18
ns
φA1, φB to XORPDOUT
13
13
ns
φB, φA2 to ECPDOUT
19
19
ns
KCP
63
68
MHz
I/DCP
41
40
MHz
3.5
3.5
pF
18
19
pF
propagation delay
CL = 15 pF; VCC = 5 V
maximum clock frequency
CI
input capacitance
CPD
power dissipation capacitance per package
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
September 1993
3
Philips Semiconductors
Product specification
Digital phase-locked-loop filter
74HC/HCT297
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
2, 1, 15, 14
A, B, C, D
modulo control inputs
3
ENCTR
K-counter enable input
4
KCP
K-counter clock input (LOW-to-HIGH, edge-triggered)
5
I/DCP
increment/decrement clock input (HIGH-to-LOW, edge-triggered)
6
D/U
down/up control
7
I/DOUT
increment/decrement bus output
8
GND
ground (0 V)
9, 10, 13
φA1, φB, φA2
phase inputs
11
XORPDOUT
EXCLUSIVE-OR phase detector output
12
ECPDOUT
edge-controlled phase detector output
16
VCC
positive supply voltage
Fig.1 Pin configuration.
September 1993
Fig.2 Logic symbol.
4
Fig.3 IEC logic symbol.
Philips Semiconductors
Product specification
Digital phase-locked-loop filter
74HC/HCT297
Fig.4 Functional diagram.
K-COUNTER (DIGITAL CONTROL) FUNCTION TABLE
D
C
B
A
MODULO (K)
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
inhibited
23
24
25
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
H
26
27
28
29
H
H
H
H
L
L
L
L
L
L
H
H
L
H
L
H
210
211
212
213
H
H
H
H
H
H
H
H
L
L
H
H
L
H
L
H
214
215
216
217
September 1993
EXCLUSIVE-OR PHASE DETECTOR FUNCTION
TABLE
φA1
φB
XORPDOUT
L
L
H
H
L
H
L
H
L
H
H
L
EDGE-CONTROLLED PHASE DETECTOR TABLE
φA2
H or L
↓
H or L
↑
φB
↓
H or L
↑
H or L
Notes
1. H = HIGH voltage level
L = LOW voltage level
↓ = HIGH-to-LOW transition
↑ = LOW-to-HIGH transition
5
ECPDOUT
H
L
no change
no change
Philips Semiconductors
Product specification
Digital phase-locked-loop filter
74HC/HCT297
Fig.5 Logic diagram.
September 1993
6
Philips Semiconductors
Product specification
Digital phase-locked-loop filter
74HC/HCT297
Fig.6 DPLL using EXCLUSIVE-OR phase detection.
Fig.7 DPLL using both phase detectors in a ripple-cancellation scheme.
September 1993
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Philips Semiconductors
Product specification
Digital phase-locked-loop filter
74HC/HCT297
Fig.8 Timing diagram: I/DOUT in-lock condition.
Fig.9 Timing diagram: edge-controlled phase comparator waveforms.
Fig.10 Timing diagram: EXCLUSIVE-OR phase detector waveforms.
September 1993
8
Philips Semiconductors
Product specification
Digital phase-locked-loop filter
74HC/HCT297
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard/bus driver
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
min.
+25
−40 to +85
typ.
max. min. max.
−40 to +125
min.
UNIT V
WAVEFORMS
CC
(V)
max.
tPHL/ tPLH
propagation delay
I/DCP to I/DOUT
50
18
14
175
35
30
220
44
37
265
53
45
ns
2.0
4.5
6.0
Fig.11
tPHL/ tPLH
propagation delay
φA1, φB
to XORPDOUT
44
16
13
160
32
27
200
40
34
240
48
41
ns
2.0
4.5
6.0
Fig.12
tPHL/ tPLH
propagation delay
φB, φA2
to ECPDOUT
61
22
18
220
44
37
275
55
47
330
66
56
ns
2.0
4.5
6.0
Fig.13
tTHL/ tTLH
output transition time:
bus driver output;
I/DOUT (pin 7)
14
5
4
60
12
10
75
15
13
90
18
15
ns
2.0
4.5
6.0
Fig.11
tTHL/ tTLH
output transition time:
standard outputs;
XORPDOUT, ECPDOUT
(pins 11, 12)
19
7
6
75
15
13
95
19
16
110
22
19
ns
2.0
4.5
6.0
Fig.12 and 13
tW
clock pulse width
KCP
80
16
14
22
8
6
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.14
tW
clock pulse width
I/DCP
100
20
17
28
10
8
125
25
21
150
30
26
ns
2.0
4.5
6.0
Fig.11
tsu
set-up time
D/U, ENCTR to KCP
120
24
20
33
12
10
150
30
26
180
36
31
ns
2.0
4.5
6.0
Fig.14
th
hold time
D/U, ENCTR to KCP
0
0
0
−19
−7
−6
0
0
0
0
0
0
ns
2.0
4.5
6.0
Fig.14
fmax
maximum clock pulse
frequency KCP
6.0
30
35
19
57
68
4.8
24
28
4.0
20
24
MHz
2.0
4.5
6.0
Fig.14
fmax
maximum clock pulse
frequency I/DCP
4.0
20
24
12
37
44
3.2
16
19
2.6
13
15
MHz
2.0
4.5
6.0
Fig.11
September 1993
9
Philips Semiconductors
Product specification
Digital phase-locked-loop filter
74HC/HCT297
To determine ∆ICC per input, multiply this value by the unit
load coefficient shown in the table below.
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard/bus driver
ICC category: MSI
INPUT
UNIT LOAD COEFFICIENT
ENCTR, D/U
0.3
Note to HCT types
A, B, C, D, KCP, φA2
0.6
The value of additional quiescent supply current (∆ICC) for
a unit load of 1 is given in the family specifications.
I/DCP, φA1, φB
1.5
AC CHARACTERISTICS FOR 74HCT
GND = 0 V, tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
min.
+25
−40 to +85
typ.
max. min. max.
−40 to +125
min.
UNIT V
WAVEFORMS
CC
(V)
max.
tPHL/ tPLH
propagation delay
I/DCP to I/DOUT
21
35
44
53
ns
4.5
Fig.11
tPHL/ tPLH
propagation delay
φA1, φB to XORPDOUT
16
32
40
48
ns
4.5
Fig.12
tPHL/ tPLH
propagation delay
φB, φA2 to ECPDOUT
22
44
55
66
ns
4.5
Fig.13
tTHL/ tTLH
output transition time
bus driver output
I/DOUT (pin 7)
5
12
15
18
ns
4.5
Fig.11
tTHL/ tTLH
output transition time
standard outputs
XORPDOUT, ECPDOUT
(pins 11, 12)
7
15
19
22
ns
4.5
Figs 12 and 13
tW
clock pulse width
KCP
16
8
20
24
ns
4.5
Fig.14
tW
clock pulse width
I/DCP
25
13
31
38
ns
4.5
Fig.11
tsu
set-up time
D/U, ENCTR to KCP
24
13
30
36
ns
4.5
Fig.14
th
hold time
D/U, ENCTR to KCP
0
−8
0
0
ns
4.5
Fig.14
fmax
maximum clock pulse
frequency KCP
30
62
24
20
MHz
4.5
Fig.14
fmax
maximum clock pulse
frequency I/DCP
20
36
16
13
MHz
4.5
Fig.11
September 1993
10
Philips Semiconductors
Product specification
Digital phase-locked-loop filter
74HC/HCT297
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.11 Waveforms showing the clock (I/DCP) to output (I/DOUT) propagation delays, the clock pulse width, output
transition times and maximum clock pulse frequency.
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.12 Waveforms showing the phase input (φB, φA1) to output (XORPDOUT) propagation delays and output
transition times.
September 1993
11
Philips Semiconductors
Product specification
Digital phase-locked-loop filter
74HC/HCT297
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.13 Waveforms showing the phase input (φB, φA2) to output (ECPDOUT) propagation delays and output
transition times.
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.14 Waveforms showing the clock (KCP) pulse width and the maximum clock pulse frequency, and the input
(D/U, ENCTR) to clock (KCP) set-up and hold times.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
September 1993
12