INTEGRATED CIRCUITS DATA SHEET UDA1361TS 96 kHz sampling 24-bit stereo audio ADC Product specification File under Integrated Circuits, IC01 2001 Jan 17 Philips Semiconductors Product specification 96 kHz sampling 24-bit stereo audio ADC UDA1361TS FEATURES General • Low power consumption • 256, 384, 512 and 768fs system clock • 2.4 to 3.6 V power supply • Supports sampling frequency of 5 to 110 kHz • Small package size (SSOP16) • Integrated high-pass filter to cancel DC offset GENERAL DESCRIPTION • Power-down mode The UDA1361TS is a single chip stereo Analog-to-Digital Converter (ADC) employing bitstream conversion techniques. The low power consumption and low voltage requirements make the device eminently suitable for use in low-voltage low-power portable digital audio equipment which incorporates recording functions. • Supports 2 V (RMS) input signals • Easy application • Master or slave operation. Multiple format output interface • I2S-bus and MSB-justified format compatible The UDA1361TS supports the I2S-bus data format and the MSB-justified data format with word lengths of up to 24 bits. • Up to 24 significant bits serial output. Advanced audio configuration • Stereo single-ended input configuration • High linearity, dynamic range and low distortion. ORDERING INFORMATION TYPE NUMBER UDA1361TS 2001 Jan 17 PACKAGE NAME DESCRIPTION VERSION SSOP16 plastic shrink small outline package; 16 leads; body width 4.4 mm SOT369-1 2 Philips Semiconductors Product specification 96 kHz sampling 24-bit stereo audio ADC UDA1361TS QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDDA analog supply voltage VDDD digital supply voltage IDDA analog supply current IDDD Tamb digital supply current 2.4 3.0 3.6 V 2.4 3.0 3.6 V operating mode − 10.5 − mA Power-down mode − 0.5 − mA operating mode − 3.5 − mA Power-down mode − 0.45 − mA −40 − +85 °C at 0 dB(FS) equivalent − 1.1 − V at −1 dB(FS) signal output − 1.0 − V at −1 dB − −88 −83 dB at −60 dB; A-weighted − −40 −34 dB at −1 dB − −85 −80 dB at −60 dB; A-weighted − −40 −37 dB fs = 48 kHz − 100 − dB fs = 96 kHz − 100 − dB − 100 − dB fs = 48 kHz fs = 48 kHz ambient temperature Analog Vi(rms) (THD + N)/S input voltage (RMS value) total harmonic distortion-plus-noise to signal ratio fs = 48 kHz fs = 96 kHz S/N αcs 2001 Jan 17 signal-to-noise ratio Vi = 0 V; A-weighted channel separation 3 Philips Semiconductors Product specification 96 kHz sampling 24-bit stereo audio ADC UDA1361TS BLOCK DIAGRAM handbook, full pagewidth VDDA VSSA VRP VRN Vref 16 15 5 4 2 SYSCLK 8 9 10 UDA1361TS VINL ADC Σ∆ 14 DATAO BCK WS VSSD 1 DECIMATION FILTER VINR VDDD CLOCK CONTROL 7 MSSEL PWON 3 ADC Σ∆ 13 11 DIGITAL INTERFACE 12 6 DC-CANCELLATION FILTER SFOR MGT451 Fig.1 Block diagram. PINNING SYMBOL PIN DESCRIPTION VINL 1 left channel input Vref 2 reference voltage VINR 3 right channel input VRN 4 negative reference voltage VRP 5 positive reference voltage SFOR 6 data format selection input PWON 7 power control input SYSCLK 8 system clock 256, 384, 512 or 768fs VDDD 9 digital supply voltage VSSD 10 digital ground BCK 11 bit clock input/output WS 12 word select input/output DATAO 13 data output MSSEL 14 master/slave select VSSA 15 analog ground VDDA 16 analog supply voltage 2001 Jan 17 handbook, halfpage VINL 1 16 VDDA Vref 2 15 VSSA VINR 3 14 MSSEL VRN 4 13 DATAO UDA1361TS VRP 5 12 WS SFOR 6 11 BCK 10 VSSD PWON 7 SYSCLK 8 9 VDDD MGT452 Fig.2 Pin configuration. 4 Philips Semiconductors Product specification 96 kHz sampling 24-bit stereo audio ADC UDA1361TS Table 1 FUNCTIONAL DESCRIPTION System clock Application modes using input gain stage INPUT GAIN SWITCH MAXIMUM INPUT VOLTAGE (RMS) Present 0 dB 2V Present 0 dB 1V Absent 0 dB 1V Absent 6 dB 0.5 V RESISTOR (12 kΩ) The UDA1361TS accommodates master and slave modes. The system devices must provide the system clock regardless of master or slave mode. In the master mode a system clock frequency of 256fs is required. In the slave mode a system frequency of 256, 384, 512 or 768fs is automatically detected (for a system clock of 768fs the sampling frequency must be limited to 55 kHz). The system clock must be locked in frequency to the digital interface input signals. Multiple format output interface The serial interface provides the following data output formats in both master and slave modes (see Figs 3, 4 and 5). Input level The overall system gain is proportional to VDDA, or more accurately the potential difference between the reference voltages VVRP and VVRN. The −1 dB input level at which THD + N/S is specified corresponds to −1 dB(FS) digital output (relative to the full-scale swing). With an input gain switch, the input level can be calculated as follows: • I2S-bus with data word length of up to 24 bits • MSB-justified serial format with data word length of up to 24 bits. The master mode drives pins WS (word select; 1fs) and BCK (bit clock; 64fs). WS and BCK are received in slave mode. V VRP – V VRN at 0 dB gain: V i ( – 1 dB ) = --------------------------------- = V (RMS) 3 Table 2 V VRP – V VRN at 6 dB gain: V i ( – 1 dB ) = --------------------------------- = V (RMS) 2×3 Master/slave select MSSEL In applications where a 2 V (RMS) input signal is used, a 12 kΩ resistor must be connected in series with the input of the ADC. This forms a voltage divider together with the internal ADC resistor and ensures that only 1 V (RMS) maximum is input to the IC. Table 3 Using this application for a 2 V (RMS) input signal, the gain switch must be set to 0 dB. When a 1 V (RMS) input signal is input to the ADC in the same application the gain switch must be set to 6 dB. L slave mode H master mode M (reserved for digital test) Select data format SFOR An overview of the maximum input voltage allowed against the presence of an external resistor and the setting of the gain switch is given in Table . The power supply voltage is assumed to be 3 V. MASTER/SLAVE SELECT DATA FORMAT L I2S-bus H MSB-justified data format M (reserved for analog test) data format Decimation filter The decimation from 64fs is performed in two stages. The first stage realizes a 4th-order sinx/x characteristic. This filter decreases the sample rate by 8. The second stage, a FIR filter, consists of 3 half-band filters, each decimating by a factor of 2. 2001 Jan 17 5 Philips Semiconductors Product specification 96 kHz sampling 24-bit stereo audio ADC Table 4 Decimation filter characteristic ITEM CONDITION Pass-band ripple 0 to 0.45fS Mute On recovery from Power-down, the serial data output DATAO is held LOW until valid data is available from the decimation filter. This time tracks with the sampling frequency: VALUE (dB) ±0.01 Pass-band droop 0.45fS −0.2 Stop band >0.55 fS −70 Dynamic range 0 to 0.45 fS >135 12288 t = ---------------- , t = 256 ms when fs = 48 kHz. fs DC cancellation filter Power-down mode/input voltage control A IIR high-pass filter is provided to remove unwanted DC components. The filter characteristics are given in Table 5. Table 5 The PWON pin can control the power saving together with the optional gain switch for 2 or 1 V (RMS) input. The UDA1361TS supports 2 V (RMS) input using a series resistor of 12 kΩ. For the definition of the pin settings for 1 or 2 V (RMS) mode, it is assumed that this resistor is present as a default component. DC cancellation filter characteristic ITEM UDA1361TS CONDITION VALUE (dB) Pass-band ripple − none Pass-band gain − 0 Droop at 0.00045fS −0.031 Attenuation at DC at 0.00000036fS >40 Dynamic range 0 to 0.45fS Table 6 Power-down/input voltage control PWON >135 POWER-DOWN OR GAIN L Power-down mode M 0 dB gain H 6 dB gain Serial interface formats LEFT handbook, full pagewidth WS 1 2 3 RIGHT ≥8 1 2 LSB MSB 3 ≥8 BCK DATA MSB B2 B2 LSB MSB INPUT FORMAT I2S-BUS WS RIGHT LEFT 1 2 3 ≥8 1 2 3 ≥8 BCK DATA MSB B2 LSB MSB B2 MSB-JUSTIFIED FORMAT Fig.3 Serial interface formats. 2001 Jan 17 6 LSB MSB B2 MGT453 Philips Semiconductors Product specification 96 kHz sampling 24-bit stereo audio ADC UDA1361TS LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT − 4.0 V maximum crystal temperature − 150 °C Tstg storage temperature −65 +125 °C Tamb ambient temperature −40 +85 °C Ves electrostatic handling voltage VDD supply voltage Txtal(max) note 1 HBM; note 2 −3000 +3000 V MM; note 2 −300 +300 V Notes 1. All supply connections must be made to the same power supply. 2. ESD behaviour is tested in accordance with JEDEC II standard: a) Human Body Model (HBM); equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor. b) Machine Model (MM); equivalent to discharging a 200 pF capacitor through a 0.75 µH series inductor. THERMAL CHARACTERISTICS SYMBOL R(th j-a) PARAMETER CONDITIONS VALUE UNIT 130 K/W thermal resistance from junction to ambient in free air DC CHARACTERISTICS VDDD = VDDA = 3 V; Tamb = 25 °C; all voltages referenced to ground (pins 10 and 15); unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDDA analog supply voltage 2.4 3.0 3.6 V VDDD digital supply voltage 2.4 3.0 3.6 V IDDA analog supply current fs = 48 kHz operating mode − 10.5 − mA Power-down mode − 0.5 − mA fs = 96 kHz IDDD digital supply current operating mode − 10.5 − mA Power-down mode − 0.5 − mA fs = 48 kHz operating mode − 3.5 − mA Power-down mode − 0.45 − mA operating mode − 7.0 − mA Power-down mode − 0.65 − mA fs = 96 kHz 2001 Jan 17 7 Philips Semiconductors Product specification 96 kHz sampling 24-bit stereo audio ADC SYMBOL PARAMETER UDA1361TS CONDITIONS MIN. TYP. MAX. UNIT Digital input pin (SYSCLK) VIH HIGH-level input voltage 2.0 − 5.5 V VIL LOW-level input voltage −0.5 − +0.8 V |ILI| input leakage current − − 1 µA Ci input capacitance − − 10 pF Digital 3-level input pins (PWON, SFOR, MSSEL) VIH HIGH-level input voltage 0.9VDD − VDD + 0.5 V VIM MIDDLE-level input voltage 0.4VDD − 0.6VDD V VIL LOW-level input voltage −0.5 − +0.4 V Digital input/output pins (BCK, WS) VIH HIGH-level input voltage 2.0 − 5.5 V VIL LOW-level input voltage −0.5 − +0.8 V |ILI| input leakage current − − 1 µA Ci input capacitance − − 10 pF VOH HIGH-level output voltage IOH = −2 mA 0.85VDDD − − V VOL LOW-level output voltage IOL = 2 mA − − 0.4 V Digital output pin (DATAO) VOH HIGH-level output voltage IOH = −2 mA 0.85VDDD − − V VOL LOW-level output voltage IOL = 2 mA − − 0.4 V with respect to VSSA Analog Vref reference voltage 0.45VDDA 0.5VDDA 0.55VDDA V RI input resistance − 12 − kΩ CI input capacitance − 20 − pF Note 1. All power supply connections must be connected to the same external power supply unit. 2001 Jan 17 8 Philips Semiconductors Product specification 96 kHz sampling 24-bit stereo audio ADC UDA1361TS AC CHARACTERISTICS (ANALOG) VDDD = VDDA = 3 V; fi = 1 kHz; Tamb = 25 °C; all voltages referenced to ground (pins 10 and 15); unless otherwise specified. SYMBOL Vi(rms) PARAMETER input voltage (RMS value) ∆Vi unbalance between channels (THD + N)/S total harmonic distortion-plus-noise to signal ratio CONDITIONS TYP. MAX. UNIT at 0 dB(FS) equivalent 1.1 − V at −1 dB(FS) signal output 1.0 − V <0.1 0.4 dB at −1 dB −88 −83 dB at −60 dB; A-weighted −40 −34 dB at −1 dB −85 −80 dB at −60 dB; A-weighted −40 −37 dB fs = 48 kHz 100 − dB fs = 96 kHz 100 − dB 100 − dB 30 − dB fs = 48 kHz fs = 96 kHz S/N signal-to-noise ratio αcs channel separation PSRR power supply rejection ratio 2001 Jan 17 Vi = 0 V; A-weighted fripple = 1 kHz; Vripple = 30 mV (p-p) 9 Philips Semiconductors Product specification 96 kHz sampling 24-bit stereo audio ADC UDA1361TS AC CHARACTERISTICS (DIGITAL) VDDD = VDDA = 2.4 to 3.6 V; Tamb = −40 to +85 °C; all voltages referenced to ground (pins 10 and 15); unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT System clock timing Tsys system clock cycle fsys = 256fs 35 88 780 ns fsys = 384fs 23 59 520 ns fsys = 512fs 17 44 390 ns fsys = 768fs 17 30 260 ns tCWL LOW-level system clock pulse width 0.40Tsys − 0.60Tsys ns tCWH HIGH-level system clock pulse width 0.40Tsys − 0.60Tsys ns 64fs 64fs Hz − − 64fs Hz Serial data timing Tcy(CLK)(bit) bit clock period 64fs 1 f cy = -------- ; master mode T cy 1 f cy = -------- ; slave mode T cy tBCKH bit clock HIGH time 50 − − ns tBCKL bit clock LOW time 50 − − ns tr rise time − − 20 ns tf fall time − − 20 ns td(o)(D)(BCK) data output delay time (from BCK falling edge) − − 40 ns td(o)(D)(WS) data output delay time (from WS edge) − − 40 ns th(o)(D) data output hold time 0 − − ns tr(WS) word select rise time − − 20 ns tf(WS) word select fall time − − 20 ns fWS word select period 1 1 1 fs td(WS)(BCK) word select delay from BCK master mode −40 − +40 ns tsu(WS) word select set-up time slave mode 20 − − ns th(WS) word select hold time slave mode 10 − − ns 2001 Jan 17 MSB-justified format 10 Philips Semiconductors Product specification 96 kHz sampling 24-bit stereo audio ADC UDA1361TS handbook, full pagewidth WS tr t BCKH t d(WS)(BCK) tf BCK t BCKL t d(o)(D)(BCK) t h(o)(D) Tcy(CLK)(bit) DATAO MGT454 Fig.4 Serial interface master mode timing. handbook, full pagewidth WS tr t BCKH t h(WS) tf t su(WS) BCK t BCKL Tcy(CLK)(bit) t d(o)(D)(WS) t d(o)(D)(BCK) t h(o)(D) DATAO MGT455 Fig.5 Serial interface slave mode timing. 2001 Jan 17 11 Philips Semiconductors Product specification 96 kHz sampling 24-bit stereo audio ADC UDA1361TS APPLICATION INFORMATION The application information illustrated in Fig.6, is an optimum application environment. Simplification is possible at the cost of some performance degradation. handbook, full pagewidth C11 1 X5 47 µF (16 V) 1N (63 V) C6 47 µF (16 V) 2 C3 47 µF (16 V) VDDA C10 100 nF (63 V) 15 C7 100 nF (63 V) VDDD R7 47 kΩ C12 X3-2 47 µF (16 V) 1N (63 V) R6 47 kΩ 4 C4 47 µF (16 V) R1 220 Ω X3-1 14 3 X6 VDDA R3 1Ω 16 C8 100 nF (63 V) X3-3 13 X1-1 X1-2 UDA1361TS X1-3 X1-4 5 12 X1-5 X1-6 VDDD X4-1 X2-1 X4-3 11 X1-9 R13 47 kΩ X1-10 R4 47 kΩ 7 X2-2 X2-3 X1-8 6 X4-2 VDDD X1-7 R12 47 kΩ 10 C5 47 µF (16 V) R5 47 kΩ SYSCLK 8 C9 100 nF (63 V) 9 R10 47 Ω R2 1Ω L1 BLM32A07 VD R11 47 Ω L2 BLM32A07 C1 100 µF MGU297 (16 V) VDDD VDDA C2 100 µF (16 V) The capacitors at the input of the ADC can be reduced. It should be noted that the cut-off frequency of the capacitor with the 12 kW input resistance of the ADC will also change. Fig.6 Application diagram. 2001 Jan 17 12 Philips Semiconductors Product specification 96 kHz sampling 24-bit stereo audio ADC UDA1361TS PACKAGE OUTLINE SSOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm D SOT369-1 E A X c y HE v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 8 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 1.5 0.15 0.00 1.4 1.2 0.25 0.32 0.20 0.25 0.13 5.30 5.10 4.5 4.3 0.65 6.6 6.2 1.0 0.75 0.45 0.65 0.45 0.2 0.13 0.1 0.48 0.18 10 0o Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT369-1 2001 Jan 17 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 99-12-27 MO-152 13 o Philips Semiconductors Product specification 96 kHz sampling 24-bit stereo audio ADC • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: 2001 Jan 17 UDA1361TS 14 Philips Semiconductors Product specification 96 kHz sampling 24-bit stereo audio ADC UDA1361TS Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, LFBGA, SQFP, TFBGA not suitable suitable(2) HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not PLCC(3), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO REFLOW(1) suitable suitable suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2001 Jan 17 15 Philips Semiconductors Product specification 96 kHz sampling 24-bit stereo audio ADC UDA1361TS DATA SHEET STATUS DATA SHEET STATUS PRODUCT STATUS DEFINITIONS (1) Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Note 1. Please consult the most recently issued data sheet before initiating or completing a design. DEFINITIONS DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2001 Jan 17 16 Philips Semiconductors Product specification 96 kHz sampling 24-bit stereo audio ADC NOTES 2001 Jan 17 17 UDA1361TS Philips Semiconductors Product specification 96 kHz sampling 24-bit stereo audio ADC NOTES 2001 Jan 17 18 UDA1361TS Philips Semiconductors Product specification 96 kHz sampling 24-bit stereo audio ADC NOTES 2001 Jan 17 19 UDA1361TS Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 753503/01/pp20 Date of release: 2001 Jan 17 Document order number: 9397 750 07157