PHILIPS TDA4671

INTEGRATED CIRCUITS
DATA SHEET
TDA4671
Picture Signal Improvement (PSI)
circuit
Product specification
Supersedes data of June 1993
File under Integrated Circuits, IC02
1996 Dec 11
Philips Semiconductors
Product specification
Picture Signal Improvement (PSI) circuit
TDA4671
FEATURES
• Luminance signal delay from 20 to 1100 ns (minimum
step 45 ns)
• Luminance signal peaking with symmetrical overshoots
selectable
• Selectable 2.6 or 5 MHz peaking centre frequency and
degree of peaking (−3, 0, +3 and +6 dB)
GENERAL DESCRIPTION
• Selectable noise reduction by coring
The TDA4671 delays the luminance signal and improves
colour-difference signal transients. The luminance signal
can also be improved by peaking and noise reduction
(coring).
• Handles negative as well as positive colour-difference
signals
• Selectable Colour Transient Improvement (CTI) to
decrease the colour-difference signal transient times to
those of the high frequency luminance signals
• Selectable 5 or 12 V sandcastle input voltage
• All controls selected via the I2C-bus
• Timing pulse generation for clamping and delay time
control synchronized by sandcastle pulse
• Automatic luminance signal delay correction using a
control loop
• Luminance and colour-difference input signal clamping
with coupling capacitor
• 4.5 to 8.8 V supply voltage range
• Minimum of external components.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
VP
supply voltage (pins 1 and 5)
4.5
IP(tot)
total supply current
31
41
52
mA
td(Y)
Y signal delay time
20
−
1130
ns
Vi(VBS)(p-p)
composite Y input signal (peak-to-peak value,
pin 16)
−
450
640
mV
Vi(CD)(p-p)
colour-difference input signal
(peak-to-peak value)
±(R − Y) on pin 3
−
1.05
1.48
V
±(R − Y) on pin 7
−
1.33
1.88
V
5
8.8
V
GY
gain of Y channel
−
−1
−
dB
GCD
gain of colour-difference channel
−
0
−
dB
Tamb
operating ambient temperature
0
−
70
°C
ORDERING INFORMATION
TYPE
NUMBER
TDA4671
1996 Dec 11
PACKAGE
NAME
DIP18
DESCRIPTION
plastic dual in-line package; 18 leads (300 mil)
2
VERSION
SOT102-1
1996 Dec 11
3
100 nF
100 nF
100 nF
10 nF
−(B − Y)
10 nF
−(R − Y)
Y
7
3
14
13
16
17
Vref
450
ns
Vref
Vref
BLACK LEVEL
CLAMP
BK
BLACK LEVEL
CLAMP
Vref
180
ns
BLACK
LEVEL
CLAMP
DIFFERENTIATOR
180
ns
2
90
ns
Y delay
Vref
8
HIGH-PASS
FILTER
90
ns
100
ns
CTI
on/off
18
VT
100
ns
90
ns
analog switch
VP2 = 5 to 8 V
5
comparator
I2C-BUS
TDA4671
+1
−0.5
−0.5
+
I2C-BUS
storage
capacitors
+
Y
100
nF
6 −(B − Y)
4 −(R − Y)
12
11
MED746
I2C-BUS
PEAKING
CORING
Vref
100 nF
15
Vref
GENERATION
CORING
degree of
peaking
analog switch
2.6 MHz
5 MHz
2.6 MHz
5 MHz
peaking
frequency
BLACK
LEVEL
CLAMP
coring
on/off
1
VP1 = 5 to 8 V
Picture Signal Improvement (PSI) circuit
Fig.1 Block diagram.
FULL-WAVE
RECTIFIER
45
ns
10
SCL
I2C-BUS RECEIVER
9
SDA
sandcastle
5 V/12 V
control signal
FULL-WAVE
RECTIFIER
DELAY TIME
CONTROL
I2C-BUS
Vref
DIFFERENTIATOR
BK, H + V
BLACK LEVEL
CLAMP
BK
SANDCASTLE PULSE
DETECTOR
100 nF
handbook, full pagewidth
sandcastle
pulse
Philips Semiconductors
Product specification
TDA4671
BLOCK DIAGRAM
Philips Semiconductors
Product specification
Picture Signal Improvement (PSI) circuit
TDA4671
PINNING
SYMBOL
PIN
DESCRIPTION
VP1
1
positive supply voltage 1
CDL
2
capacitor of delay time control
Vi(R − Y)
3
±(R − Y) colour-difference input signal
Vo(R − Y)
4
±(R − Y) colour-difference output
signal
VP2
5
positive supply voltage 2
Vo(B − Y)
6
±(B − Y) colour-difference output
signal
Vi(B − Y)
7
±(B − Y) colour-difference input signal
GND2
8
ground 2 (0 V)
SDA
9
I2C-bus serial data input/output
SCL
10
I2C-bus serial clock input
CCOR
11
coring capacitor
VoY
12
delayed luminance output signal
CCLP1
13
black level clamping capacitor 1
CCLP2
14
black level clamping capacitor 2
Cref
15
capacitor of reference voltage
ViY
16
luminance input signal
SAND
17
sandcastle pulse input
GND1
18
ground 1 (0 V)
1996 Dec 11
handbook, halfpage
VP1 1
18 GND1
CDL 2
17 SAND
Vi(R − Y) 3
16 ViY
Vo(R − Y) 4
15 Cref
VP2 5
TDA4671
14 CCLP2
13 CCLP1
Vo(B − Y) 6
Vi(B − Y) 7
12 VoY
11 CCOR
GND2 8
10 SCL
SDA 9
MED747
Fig.2 Pin configuration.
4
Philips Semiconductors
Product specification
Picture Signal Improvement (PSI) circuit
The output buffer stage ensures a low-ohmic VBS output
signal on pin 12 (<160 Ω). The gain of the luminance
signal path from pin 16 to pin 12 is unity.
FUNCTIONAL DESCRIPTION
The TDA4671 contains luminance signal processing and
colour-difference signal processing. The luminance signal
section comprises a variable, integrated luminance delay
line with luminance signal peaking and a noise reduction
by coring.
An oscillation signal of the delay time control loop is
present on output pin 12 instead of the VBS signal. It is
present during the vertical blanking interval of the burst key
pulses in lines 16 (330) to 18 (332). This sync should not
be applied for synchronization.
The colour-difference section consists of a transient
improvement circuit to decrease the rise and fall times of
the colour-difference signal transients. All functions and
parameters are controlled via the I2C-bus.
Colour-difference signal paths
The colour-difference input signals (on pins 3 and 7) are
clamped to a reference voltage.
Y-signal path
Each colour-difference signal is fed to a transient detector
and to an analog signal switch with an attached voltage
storage stage.
The video and blanking signal is AC-coupled to the input
pin 16. Its black porch is clamped to a DC reference
voltage to ensure the correct operating range of the
luminance delay stage.
The transient detectors consist of differentiators and
full-wave rectifiers. The output voltages of both transient
detectors are added and then compared. The comparator
controls both following analog signal switches
simultaneously.
The luminance delay line consists of all-pass filter sections
with delay times of 45, 90, 100, 180 and 450 ns
(see Fig.1). The luminance signal delay is controlled via
the I2C-bus in steps of 45 ns in the range of 20 to 1100 ns,
this ensures that the maximum delay difference between
the luminance and colour-difference signals is ±22.5 ns.
The analog signal switches are in open position at a
certain value of transient time; the held value (held by
capacitors) is then applied to the outputs. The switches
close to rapidly accept the actual signal levels at the end
of these transients. The improved transient time is
approximately 100 ns long independent of the input
transient time.
An automatic luminance delay time adjustment in an
internal control loop (with the horizontal frequency as a
reference) is used to correct changes in the delay time,
due to component tolerances. The control loop is
automatically enabled between the burst key pulses of
lines 16 (330) and 17 (331) during the vertical blanking
interval. The control voltage is stored in capacitor CDL
connected to pin 2.
Colour-difference paths are independent of the input
signal polarity and have a nominal unity gain.
The CTI functions are switched on and off via the I2C-bus.
The peaking section is using a transversal filter circuit with
selectable centre frequencies of 2.6 and 5.0 MHz.
It provides selectable degrees of peaking of −3, 0, +3 and
+6 dB and noise reduction by coring, which attenuates the
high-frequency noise introduced by peaking.
1996 Dec 11
TDA4671
5
Philips Semiconductors
Product specification
Picture Signal Improvement (PSI) circuit
TDA4671
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134). VP1 and VP2 as well as GND1 and GND2
connected together.
SYMBOL
PARAMETER
VP1
supply voltage (pin 1)
VP2
Ptot
CONDITIONS
MIN.
MAX.
UNIT
0
8.8
V
supply voltage (pin 5)
0
8.8
V
total power dissipation
0
0.97
W
Tstg
storage temperature
−25
+150
°C
Tamb
operating ambient temperature
0
70
°C
VESD
electrostatic handling
−
+300
V
−
−500
V
−
±500
V
note 1
for pins 9 and 10
for other pins
Note
1. Equivalent to discharging a 200 pF capacitor through a 0 Ω series resistor.
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
PARAMETER
VALUE
UNIT
82
K/W
thermal resistance from junction to ambient in free air
CHARACTERISTICS
VP1 = VP2 = 5 V; nominal video amplitude VVB = 315 mV; tH = 64 µs; tBK = 4 µs (burst key); Tamb = 25 °C and
measurements taken in Fig.4; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VP1
supply voltage (pin 1)
4.5
5
8.8
V
VP2
supply voltage (pin 5)
4.5
5
8.8
V
IP(tot)
total supply current
31
41
52
mA
Vi(Y)(p-p)
VBS input signal on pin 16
(peak-to-peak value)
−
450
640
mV
V16
black level clamping voltage
−
3.1
−
V
I16
input current
during clamping
±95
−
±190
µA
outside clamping
−
−
±0.1
µA
R16
input resistance
outside clamping
5
−
−
MΩ
C16
input capacitance
−
3
10
pF
Y-signal path
I2C-bus
td(Y)(max)
maximum Y delay time
set via
td(Y)(min)
minimum Y delay time
set via I2C-bus
1996 Dec 11
6
1070
1100
1130
ns
−
20
−
ns
Philips Semiconductors
Product specification
Picture Signal Improvement (PSI) circuit
SYMBOL
∆ td(Y)
PARAMETER
CONDITIONS
minimum delay step
set via
group delay time difference
delay time difference between Y
and colour-difference signals
I2C-bus
TDA4671
MIN.
TYP.
MAX.
UNIT
40
45
50
ns
f = 0.5 to 5 MHz;
maximum delay
−
0
±25
ns
Y delay;
CTI and peaking off
70
100
130
ns
185
215
245
ns
td(peak)
minimum delay time for peaking
GY
VBS signal gain measured on
output pin 12 (composite signal,
peak-to-peak value)
Vo/Vi; f = 500 kHz;
maximum delay
−2
−1
0
dB
I12
output current (emitter-follower with
constant current source)
source current
−1
−
−
mA
sink current
0.4
−
−
mA
−
−
160
Ω
f = 0.5 to 3 MHz
−2
−1
0
dB
f = 0.5 to 5 MHz
−4
−3
−1
dB
R12
output resistance
fres
frequency response for
LIN
signal linearity for
maximum delay
αmin/αmax;
video contents of 315 mV (p-p)
VVBS = 450 mV (p-p)
0.85
−
−
−
video contents of 450 mV (p-p)
VVBS = 640 mV (p-p)
0.60
−
−
−
fC1; LCF-bit = 0
4.5
5
5.5
MHz
fC2; LCF-bit = 1
2.3
2.6
2.9
MHz
−
−3
−
dB
−
0
−
dB
−
+3
−
dB
−
+6
−
dB
−
20
−
%
Luminance peaking, selected via I2C-bus
fpeak
Vpeak
peaking frequency
peaking amplitude for grade of
peaking (fC amplitude over 0.5 MHz
amplitude)
selectable values
limitation of peaking (positive
amplitude of correction signal
referred to 315 mV)
Vn(rms)
noise voltage on pin 12
(RMS value)
without peaking;
f = 0 to 5 MHz
−
−
1
mV
COR
coring of peaking
(coring part referred to 315 mV)
COR-bit = 1
−
20
−
%
1996 Dec 11
7
Philips Semiconductors
Product specification
Picture Signal Improvement (PSI) circuit
SYMBOL
PARAMETER
CONDITIONS
TDA4671
MIN.
TYP.
MAX.
UNIT
Colour-difference paths measured with transient times tr = tf = 1 µs; tp H ≥ 1 µs; Vi = 1.33 V (p-p) on
pins 3 and 7 and with burst key pulse tBK = 4 µs
Vi(CD)(p-p)
±(R − Y) input signal
(peak-to-peak value; pin 3)
75% colour bar
−
1.05
1.48
V
±(B − Y) input signal
(peak-to-peak value; pin 7)
75% colour bar
−
1.33
1.88
V
input transient sensitivity
V3,7/δt
V3,7
internal clamping voltage level
I3,7
input current
C3,7
input capacitance
V4,6
DC output voltage
∆V4,6
output offset voltage
0.22
−
−
V/µs
−
2.45
−
V
outside clamping
−
−
±1
µA
during clamping
±100
−
±190
µA
−
6
12
pF
−
2
−
V
−
−
±5
mV
during and after storage time −
RS ≤ 300 Ω; note 1
−
±18
mV
Vspike
spurious spike signals on pins 4
and 6
RS ≤ 300 Ω; note 1
−
−
±30
mV
I4,6
output current (emitter-follower with
constant current source)
source current
−1
−
−
mA
sink current
0.4
−
−
mA
−
−
100
Ω
−1
0
+1
dB
−
0
±0.3
dB
R4,6
output resistance
Gv
signal gain in each path
∆Gv
gain difference −(R − Y)/−(B − Y)
LIN
signal linearity for
∆Vo
Vo/Vi
αmin/αmax;
nominal signal
Vi = 1.33 V (p-p)
0.90
−
−
−
+3 dB signal
Vi = 1.88 V (p-p)
0.65
−
−
−
−1.5
−
−
dB
signal reduction at higher frequency signal with tp H = 50 ns;
(output signal ratio Vi/Vo)
tr = tf = 1 µs
Sandcastle pulse, input voltage selectable via I2C-bus
V17
R17
input voltage threshold for H and V
sync
SC5-bit = 0 (12 V)
1.1
1.5
1.9
V
input voltage threshold for burst
SC5-bit = 0 (12 V)
5.5
6.5
7.5
V
input voltage threshold for H and V
sync
SC5-bit = 1 (5 V)
1.1
1.5
1.9
V
input voltage threshold for burst
SC5-bit = 1 (5 V)
3.0
3.5
4.0
V
input resistance
+12 V input level
30
40
50
kΩ
+5 V input level
15
20
25
kΩ
C17
input capacitance
−
4
8
pF
tBK
burst key pulse width
3.0
4.0
4.6
µs
td
leading edge delay for clamping
pulse
−
1
−
µs
np
number of required burst key pulses note 2
vertical blanking interval
4
−
31
−
1996 Dec 11
referred to tBK
8
Philips Semiconductors
Product specification
Picture Signal Improvement (PSI) circuit
SYMBOL
PARAMETER
TDA4671
CONDITIONS
MIN.
TYP.
MAX.
UNIT
I2C-bus control, SDA and SCL
VIH
HIGH level input voltage on pins 9
and 10
3
VIL
LOW level input voltage
0
I9,10
input current
−
Vo(ACK)
output voltage at acknowledge on
pin 9
Io(ACK) = 3 mA
−
Io(ACK)
output current at acknowledge on
pin 9
sink current
3
−
5
V
−
1.5
V
−
±10
µA
−
0.4
V
−
−
mA
Notes
1. Crosstalk on output, measured in the unused channel when the other channel is provided with a nominal input signal
(CTI active).
2. A number of more than 31 burst key pulses repeats the counter cycle of delay time control.
I2C-BUS FORMAT
S(1)
SLAVE ADDRESS(2)
ACK(3)
SUBADDRESS(4)
ACK(3)
DATA(5)
P(6)
Notes
1. S = START condition.
2. SLAVE ADDRESS = 1000 100X.
3. ACK = acknowledge, generated by the slave.
4. SUBADDRESS = subaddress byte, see Table 1.
5. DATA = data byte, see Table 1.
6. P = STOP condition.
7. X = read/write control bit.
X = 0, order to write (the circuit is slave receiver).
X = 1, order to read (the circuit is slave transmitter).
If more than 1 byte of DATA is transmitted, then auto-increment of the subaddress is performed.
Table 1
I2C-bus transmission; see Table 2
DATA
FUNCTION
Y delay/CTI/SC
SUBADDRESS
00010000
Peaking and coring 00010001
1996 Dec 11
D7
D6
D5
D4
D3
D2
D1
D0
0
SC5
CTI
DL4
DL3
DL2
DL1
DL0
COR
PEAK
LCF
0
0
0
9
PCON1 PCON0
Philips Semiconductors
Product specification
Picture Signal Improvement (PSI) circuit
Table 2
TDA4671
Function of the bits
DATA
LOGIC 1
LOGIC 0
45 ns
0 ns
DL1
90 ns
0 ns
DL2
180 ns
0 ns
DL3
180 ns
0 ns
DL4
450 ns
0 ns
active
inactive
DL0
FUNCTION
set delay in luminance channel
CTI
set colour transient improvement
SC5
select sandcastle pulse voltage
+5 V
+12 V
LCF
set peaking frequency response
2.6 MHz
5.0 MHz
PEAK
set peaking delay
active
inactive
COR
set coring control
active
PCONx
set peaking amplification
Table 3
Peaking amplification
PCON1
PCON0
GRADE OF PEAKING
(dB)
0
0
−3
0
1
0
1
0
+3
1
1
+6
Remarks to the subaddress bytes
Subaddresses 00H to 0FH are reserved for colour decoders and RGB processors.
Subaddresses 10 and 11 only are acknowledged.
General call address is not acknowledged.
Power-on-reset: D7 to D1 bits of data bytes are set to logic 0, D0 bit is set to logic 1.
1996 Dec 11
inactive
see Table 3
10
1996 Dec 11
VP
GND
1
18
11
3
CD input
2
CDL
all input
and output
pins without
pins 9 and 10
16
+
Y input
17
+
+
+
4
7
CD input
6
CD output
Fig.3 Internal circuit.
VP
5
+
+
+
13
CCLP
GND
8
+
+
+
SDA
9
10
MED749
+
11
12
SCL
CCOR
Y output
Picture Signal Improvement (PSI) circuit
CD output
14
15
TDA4671
CCLP
Cref
handbook, full pagewidth
SC
Philips Semiconductors
Product specification
TDA4671
INTERNAL CIRCUITRY
Philips Semiconductors
Product specification
Picture Signal Improvement (PSI) circuit
TDA4671
TEST AND APPLICATION INFORMATION
handbook, full pagewidth
SDA
I2C-bus
SCL
CCOR
0.1 µF
(VBS)
VoY
CCLP1
0.1 µF
CCLP2
SDA
10
9
11
8
12
7
13
14
6
TDA4671
5
GND2
Vi(B − Y)
10 nF
Vo(B − Y)
VP2
0.1 µF
Cref
15
4
16
3
0.1 µF
(VBS)
sandcastle
pulse input
ViY
0.1 µF
SAND
2
17
GND1
1
18
Vo(R − Y)
Vi(R − Y)
10 nF
CDL
VP1
0.1 µF
+5 V
47 µF
15 Ω
MED748
VB
Fig.4 Test and application circuit.
1996 Dec 11
12
Philips Semiconductors
Product specification
Picture Signal Improvement (PSI) circuit
TDA4671
PACKAGE OUTLINE
DIP18: plastic dual in-line package; 18 leads (300 mil)
SOT102-1
ME
seating plane
D
A2
A
A1
L
c
e
Z
w M
b1
(e 1)
b
b2
MH
10
18
pin 1 index
E
1
9
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
b2
c
D (1)
E (1)
e
e1
L
ME
MH
w
Z (1)
max.
mm
4.7
0.51
3.7
1.40
1.14
0.53
0.38
1.40
1.14
0.32
0.23
21.8
21.4
6.48
6.20
2.54
7.62
3.9
3.4
8.25
7.80
9.5
8.3
0.254
0.85
inches
0.19
0.020
0.15
0.055
0.044
0.021
0.015
0.055
0.044
0.013
0.009
0.86
0.84
0.26
0.24
0.10
0.30
0.15
0.13
0.32
0.31
0.37
0.33
0.01
0.033
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
93-10-14
95-01-23
SOT102-1
1996 Dec 11
EUROPEAN
PROJECTION
13
Philips Semiconductors
Product specification
Picture Signal Improvement (PSI) circuit
TDA4671
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
Repairing soldered joints
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
Soldering by dipping or by wave
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1996 Dec 11
14
Philips Semiconductors
Product specification
Picture Signal Improvement (PSI) circuit
NOTES
1996 Dec 11
15
TDA4671
Philips Semiconductors – a worldwide company
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Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1996
SCA52
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
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Printed in The Netherlands
537021/1200/03/pp16
Date of release: 1996 Dec 11
Document order number:
9397 750 01472