PHILIPS TDA9177

INTEGRATED CIRCUITS
DATA SHEET
TDA9177
YUV transient improvement
processor
Product specification
Supersedes data of 1996 Jun 28
File under Integrated Circuits, IC02
1997 Dec 01
Philips Semiconductors
Product specification
YUV transient improvement processor
TDA9177
FEATURES
• Can be used in 1fH and 2fH applications
• Luminance step improvement
• Line width control
• Smart peaking for detail enhancement
• Embedded feature reduction facility for smart noise
control
In combination with the TDA9170, it builds a high
performance and intelligent picture improvement solution.
• Compensating chrominance delay
The sharpness processor provides 1D luminance step
improvement and detail enhancement by smart peaking,
suitable for both 1fH and 2fH applications. The TDA9177
can be used as a cost effective alternative to (but also in
combination with) Scan Velocity Modulation (SVM).
• YUV interface
• Two additional pins for access to 6-bit ADC and I2C-bus
• Versatile I2C-bus and pin control for user adjustments.
An on-board 6-bit Analog-to-Digital Converter (ADC) can
be used for interfacing two analog, low frequency voltage
signals to the I2C-bus.
GENERAL DESCRIPTION
The TDA9177 is an I2C-bus controlled sharpness
improvement IC with additional inputs for 6-bit
analog-to-digital conversion to facilitate additional
parameter measurement (e.g. ambient light control).
It should preferably be used in front of an RGB video signal
processor with YUV interface.
The supply voltage is 8 V. The TDA9177 is mounted in a
24-pin SDIP envelope.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
VCC
supply voltage
Vi(Y)
luminance input voltage
CONDITIONS
MIN.
TYP.
MAX.
UNIT
7.2
8.0
8.8
V
AMS = LOW
−
0.315
0.42
V
AMS = HIGH
−
1.0
1.33
V
1.9
V
Vi(UV)
UV input voltage
−
−
VFS(ADC)
full scale ADC input voltage
−
0.5Vref −
V
Vref
reference voltage
3.90
4.05
V
4.20
ORDERING INFORMATION
TYPE
NUMBER
TDA9177
1997 Dec 01
PACKAGE
NAME
SDIP24
DESCRIPTION
plastic shrink dual in-line package; 24 leads (400 mil)
2
VERSION
SOT234-1
Philips Semiconductors
Product specification
YUV transient improvement processor
TDA9177
BLOCK DIAGRAM
handbook, full pagewidth
AMS
14
CFS
FHS
8
17
SDA SCL
13
ADR
12
ADEXT1 ADEXT2
6
3
10
22
STEEP
LWC
4
2
COR
PEAK
SANDCASTLE
input
PIN-TO-I2C-BUS
INTERFACE
TDA9177
I2C-BUS
CONTROLLER
6-BIT
ADC
11
line width
1
STEP
IMPROVEMENT
PROCESSOR
SANDCASTLE
DETECTOR
contour filter
selection
5
YIN
BLACK
INSERTION
CLAMP
20
YOUT
SMART
SHARPNESS
CONTROLLER
CONTOUR
PROCESSOR
CLAMPS
DELAY
steepness coring peaking
15
SNC
amplitude
selection
DELAY
7
UIN
DELAY
18
9
IPTAT
16
VIN
UOUT
VOUT
Fig.1 Block diagram.
1997 Dec 01
3
24
Rext
line frequency
selection
BANDGAP
21
VCC
19
GND
23
Vref
MBH229
Philips Semiconductors
Product specification
YUV transient improvement processor
TDA9177
PINNING
SYMBOL
PIN
DESCRIPTION
SANDCASTLE
1
sandcastle input
COR
2
coring level input
ADEXT1
3
ADC input 1
LWC
4
line width control input
YIN
5
luminance input
ADR
6
I2C-bus
UIN
7
colour U input
CFS
8
contour filter select input
VIN
9
colour V input
ADEXT2
10
ADC input 2
PEAK
11
peaking amplitude input
SCL
12
serial clock input (I2C-bus)
UIN
7
18 UOUT
SDA
13
serial data input/output
(I2C-bus)
CFS
8
17 FHS
VIN
9
16 VOUT
AMS
14
amplitude select input
SNC
15
smart noise control input
VOUT
16
colour V output
FHS
17
line frequency select input
UOUT
18
colour U output
GND
19
system ground
YOUT
20
luminance output
VCC
21
supply voltage
STEEP
22
steepness control input
Vref
23
reference voltage output
Rext
24
resistor reference
1997 Dec 01
handbook, halfpage
address input
SANDCASTLE
1
24 Rext
COR
2
23 Vref
ADEXT1
3
22 STEEP
LWC
4
21 VCC
YIN
5
20 YOUT
ADR
6
19 GND
TDA9177
ADEXT2 10
15 SNC
PEAK 11
14 AMS
SCL 12
13 SDA
MBH228
Fig.2 Pin configuration.
4
Philips Semiconductors
Product specification
YUV transient improvement processor
for horizontal geometry because of the gamma or
blooming of the spot of the CRT.
FUNCTIONAL DESCRIPTION
Y-input selection and amplification
THE CONTOUR PROCESSOR
The dynamic range of the luminance input amplifier and
output amplifier can be switched between 0.315 V and
1.0 V typically (excluding sync), either externally
(pin AMS) or by I2C-bus (bit AMS of the control register).
Amplitudes outside the corresponding maximum specified
range will be clipped smoothly. The sync part is processed
transparently to the output, independently of the feature
settings. The input is clamped during the HIGH period of
the CLP, defined by the sandcastle reference, and should
be DC-decoupled with an external capacitor. During the
clamp pulse, an artificial black level is inserted in the input
signal to correctly preset the internal circuitry.
The contour processor comprises two contour generators
with different frequency characteristics. The contour
generator generates a second-order derivative of the
incoming luminance signal and is used both as a decision
signal for the step improvement processor and as a
luminance correction signal for the smart sharpness
controller. In the smart sharpness controller, this
correction signal is added to the proper delayed original
luminance input signal, making up the peaking signal for
detail enhancement. The peaking path is allowed to select
either the narrow- or wide-peaked contour generators
either externally (pin 8, CFS) or by I2C-bus (bit CFS in the
control register). The step improvement circuitry always
selects the wide-peaked contour filter.
The input amplifier drives a delay line of four delay
sections, which form the core of the sharpness
improvement processor.
The contour generators utilize 3 taps (narrow band) or
5 taps (broad band) of the embedded luminance delay
lines. Figures 11 and 12 illustrate the normalized
frequency transfer of both the narrow and wide contour
filters.
Sharpness improvement processor
The sharpness improvement processor increases the
slope of large luminance transients of vertical objects and
enhances transients of details in natural scenes by contour
correction. It comprises three main processing units, these
being the step improvement processor, the contour
processor and the smart sharpness controller.
SMART SHARPNESS CONTROLLER
The smart sharpness controller (see Fig.10) is a fader
circuit that fades between peaked luminance and
step-improved luminance, defined by the output of a step
discriminating device known as the step detector. It also
contains a variable coring level stage.
STEP IMPROVEMENT PROCESSOR
The step improvement processor (see Fig.9) comprises
two main functions:
1. the MINMAX generator
The step detector behaves like a band-pass filter, so both
amplitude of the step and its slope add to the detection
criterion. The smart sharpness controller has four user
controls:
2. the MINMAX fader.
The MINMAX generator utilizes 5 taps of an embedded
luminance delay line to calculate the minimum and
maximum envelope of all signals momentarily stored in the
delay line. The MINMAX fader chooses between the
minimum and maximum envelopes, depending on the
polarity of a decision signal derived from the contour
processor. Figures 4, 5 and 6 show some waveforms of
the step improvement processor and illustrate that fast
transients result with this algorithm. The MINMAX
generator also outputs a signal that represents the
momentary envelope of the luminance input signal.
This envelope information is used by the smart sharpness
controller.
1. Steepness control
2. Peaking control
3. Coring level control
4. Smart Noise control.
Control settings can be performed either by the I2C-bus or
externally by pin, depending on the status of the I2C-bus
bit STB.
The steepness setting controls the amount of steepness in
the edge-correction processing path. The peaking setting
controls the amount of contour correction for proper detail
enhancement.
Limited line width control (also called aperture control) can
be performed externally (pin 4, LWC) or by I2C-bus
(LW-DAC). Line width control can be used to compensate
1997 Dec 01
TDA9177
5
Philips Semiconductors
Product specification
YUV transient improvement processor
The envelope signal generated by the step improvement
processor modulates the peaking setting in order to
reduce the amount of peaking for large sine excursions
see Figs 7 and 8.
TDA9177
I2C-bus
At power up, the bit STB (standby) in the control register is
reset, to leave control to the pins. However, the I2C-bus is
at standby and responds if properly addressed. By setting
STB to logic 1, the control of all features is instead left to
the I2C-bus registers. The PDD bit (Power Down Detected)
in the status register is set each time an interruption of the
supply power occurs and is reset only by reading the
status register. A 3-bit identification code can also be read
from the status register, which can be used to
automatically configure the application by software.
The coring setting controls the coring level in the peaking
path for rejection of high-frequency noise. All three
settings facilitate reduction of the impact of the sharpness
features, e.g. for noisy luminance signals.
An external noise detector and a user-preferred noise
algorithm are needed to make a fully automatic I2C-bus
controlled smart sharpness control.
The input control registers can be written sequentially by
the I2C-bus by the embedded automatic subaddress
increment feature or by addressing it directly. The output
control functions cannot be addressed separately.
Reading out the output control functions always starts at
subaddress 00 and all subsequent words are read out by
the automatic subaddress increment procedure. The I2C
address is 40H if pin 6 (ADR) is connected to ground and
E0H if pin 6 (ADR) is connected to pin 23 (Vref).
An on-board, hard-wired smart sharpness algorithm can
be executed by driving pin SNC with the output of an
external noise detector. This pin, however, is active both in
I2C-bus and pin mode. Figures 13 and 14 illustrate the
impact of the noise control voltage at pin SNC on the user
settings.
Figure 15 shows the relationship between the feature
settings STEEP, COR, PEAK, LWC and their
corresponding pin voltages.
I2C-bus specification
Chrominance compensation
Slave address
The chrominance delay lines compensate for the delay of
the luminance signal in the step improvement processor,
to ensure a correct colour fit. No delay compensation will
be performed in the chrominance path for line-width
corrections in the luminance path.
A6
A5
A4
A3
A2
A1
A0
R/W
ADR
1
ADR
0
0
0
0
X
Auto-increment mode available for subaddresses.
Successive approximation ADC
Pins ADEXT1 and ADEXT2 are connected to a 6-bit
successive approximation ADC, via a multiplexer.
The multiplexer toggles between the inputs with each field.
For each field flyback, a conversion is started for either of
the two inputs and the result is stored in the corresponding
bus register, ADEXT1 or ADEXT2.
In this way, any analog, slowly varying signal can be given
access to the I2C-bus. If a register access conflict occurs,
the data of that register is made invalid by setting the flag
bit DV (Data Valid) to zero.
1997 Dec 01
6
Philips Semiconductors
Product specification
YUV transient improvement processor
TDA9177
Control functions
DATA BYTE
FUNCTIONS
TYPE
SUBADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
Inputs
Control
REG
00
X
X
X
X
CFS
FHS
AMS
STB
Peaking
DAC
01
X
X
PK5
PK4
PK3
PK2
PK1
PK0
Steepness
DAC
02
X
X
SP5
SP4
SP3
SP2
SP1
SP0
Coring
DAC
03
X
X
CR5
CR4
CR3
CR2
CR1
CR0
Line width
DAC
04
X
X
LW5
LW4
LW3
LW2
LW1
LW0
Status
REG
00
0
0
0
0
ID2
ID1
ID0
PDD
ADEXT1 (output)
REG
01
0
DV
AD5
AD4
AD3
AD2
AD1
AD0
ADEXT2 (output)
REG
02
0
DV
AD5
AD4
AD3
AD2
AD1
AD0
Outputs
INPUT SIGNALS
Table 1
Table 6
Address selection
ADR
PK5 to PK0
FUNCTION
0
I2C address is 40H
1
I2C address is E0H
Table 2
FUNCTION
0
pin mode
1
I2C-bus
mode
0
0.315 V luminance
1
1.0 V luminance
1
2fH
Table 5
Contour filter selection
CFS
FUNCTION
0
narrow contour filter
1
wide contour filter
1997 Dec 01
FUNCTION
0%
111111
100%
Coring level
FUNCTION
000000
0%
111111
100%
Line width correction
LW5 to LW0
FUNCTION
1fH
Steepness correction
000000
Table 9
Line frequency selection
0
100%
CR5 to CR0
FUNCTION
FHS
111111
Table 8
Amplitude selection
Table 4
0%
SP5 to SP0
STB
AMS
FUNCTION
000000
Table 7
Standby
Table 3
Peaking amplitude
7
FUNCTION
000000
0%
111111
100%
Philips Semiconductors
Product specification
YUV transient improvement processor
OUTPUT SIGNALS
TDA9177
Table 12 Data valid of ADC registers
Table 10 Power Down Detection (PDD)
DV
FUNCTION
PDD
FUNCTION
0
0
no power down detected since last read
action
data not valid because of possible
register access collision
1
data valid
1
power down detected
Table 13 Bits AD5 to AD0
Table 11 Identification
(version number or derivative type)
ID2 to ID0
000
AD5 to AD0
FUNCTION
FUNCTION
000000B
0V
111111B
0.5Vref
TDA9177/N1
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VCC
supply voltage
−0.5
+8.8
Vi
input voltage on any input
−0.5
VCC + 0.5 V
Vo
output voltage of any output
−0.5
VCC + 0.5 V
Tstg
storage temperature
−55
+150
°C
Tamb
operating ambient temperature
−10
+70
°C
V
QUALITY SPECIFICATION
Quality level in accordance with “SNW-FQ-611 part E”.
All pins are protected against ESD by means of internal clamping diodes. The protection circuit meets the specification:
Human body model (100 pF, 1500 Ω): All pins >3000 V.
Machine model (200 pF, 0 Ω): All pins >300 V.
Latch-up:
At an ambient temperature of 70 °C, all pins meet the specification:
Itrigger > 100 mA or Vpin > 1.5VCC(max)
Itrigger < −100 mA or Vpin < −0.5VCC(max)
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
1997 Dec 01
PARAMETER
thermal resistance from junction to ambient in free air
8
VALUE
UNIT
<59
K/W
Philips Semiconductors
Product specification
YUV transient improvement processor
TDA9177
CHARACTERISTICS
VCC = 8 V; Rref = 10 kΩ ±2%; Tamb = 25 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
MAIN SUPPLY VCC (PIN 21)
VCC
supply voltage
ICC
supply current
7.2
8.0
8.8
V
1fH mode
−
40
−
mA
2fH mode
−
45
−
mA
REFERENCE SUPPLY Vref (PIN 23)
Vref
reference supply voltage
3.90
4.05
4.20
V
IL(max)
maximum load current
1.0
−
−
mA
RESISTOR REFERENCE Rext (PIN 24)
VRref
resistor supply voltage
−
2
−
V
Rref
resistor value
−
10
−
kΩ
AMS = LOW
−
0.315
0.42
V
AMS = HIGH
−
1.0
1.33
V
−
4.0
−
V
−
−
0.1
µA
Luminance input/output selection
LUMINANCE INPUT YIN (PIN 5)
Vi(Y)
luminance input voltage
Vi(Yclamp)
luminance input voltage level during
clamping
Iib(Y)
luminance input bias current
no clamp
LUMINANCE INPUT VOLTAGE RANGE SELECTION AMS (PIN 14); note 1
VAMSL
input voltage for low luminance range
−
−
0.5
V
VAMSH
input voltage for high luminance range
3.5
−
5.5
V
1997 Dec 01
9
Philips Semiconductors
Product specification
YUV transient improvement processor
SYMBOL
PARAMETER
TDA9177
CONDITIONS
MIN.
TYP.
MAX.
UNIT
LUMINANCE OUTPUT YOUT (PIN 20)
Vo(Y) (p-p)
luminance output voltage, peak-to-peak
Vo(Yclamp)
luminance output voltage during
clamping
S/N(Y)
luminance output signal-to-noise ratio
BY
luminance bandwidth
AMS = LOW
−
0.315
−
V
AMS = HIGH
−
1.0
−
V
AMS = LOW
−
2.35
−
V
AMS = HIGH
−
2
−
V
52
−
−
dB
1fH mode (−1 dB);
transparent; note 2
5
−
−
MHz
2fH mode (−1 dB);
transparent; note 2
10
−
−
MHz
Ebl
black level error
transparent; note 3
−
0
1.0
%
EG(n)
nominal gain error
transparent
−
0
5
%
Rout
output resistance
−
−
150
Ω
Iob
output bias current
1.3
−
−
mA
1fH mode; note 4
−
20
−
ns
2fH mode; note 4
−
20
−
ns
2 MHz
−
33
−
%
Step improvement
GENERAL
tr(min)
minimum rise time 10% to 90%
LINE WIDTH CONTROL
δ(min)
minimum duty factor
δ(max)
maximum duty factor
2 MHz
−
67
−
%
tsd(max)
maximum step displacement
1fH mode
−
140
−
ns
2fH mode
−
70
−
ns
LINE-WIDTH CONTROL LWC (PIN 4); note 1
Vi(min)
input voltage for minimum line width
−
−
37.5
%Vref
Vi(max)
input voltage for maximum line width
87.5
−
137.5
%Vref
Ibias
input bias current
−
0.5
−
µA
1fH
−
3.57
−
MHz
2fH
−
7.14
−
MHz
1fH
−
4.14
−
MHz
2fH
−
8.28
−
MHz
note 5
−
12
−
dB
Contour processing
CONTOUR FILTER NARROW-PEAKED
fpc
peaking centre frequency
CONTOUR FILTER WIDE-PEAKED
fpc1
Qmax
peaking centre frequency
maximum contour amplitude at centre
frequency
1997 Dec 01
10
Philips Semiconductors
Product specification
YUV transient improvement processor
SYMBOL
PARAMETER
TDA9177
CONDITIONS
MIN.
TYP.
MAX.
UNIT
CONTOUR FILTER SELECTION CFS (PIN 8); note 1
Vi(ncf)
input voltage for narrow contour filter
−
−
0.5
V
Vi(wcf)
input voltage for wide contour filter
3.5
−
5.5
V
1fH
−
2.13
−
MHz
2fH
−
4.26
−
MHz
Smart sharpness controller
STEP DETECTOR
fdc
detection centre frequency
CORING
QsmcL
minimum coring level
note 6
−
0
−
%
QsmcH
maximum coring level
note 6
−
22
−
%
CORING LEVEL CONTROL COR (PIN 2); note 1
Vi(min)
input voltage for minimum coring
−
−
37.5
%Vref
Vi(max)
input voltage for maximum coring
87.5
−
137.5
%Vref
Ibias
input bias current
−
−
0.5
µA
PEAKING LEVEL CONTROL PEAK (PIN 11); note 1
Vi(min)
input voltage for minimum peaking
−
−
37.5
%Vref
Vi(max)
input voltage for maximum peaking
87.5
−
137.5
%Vref
Ibias
input bias current
−
−
0.5
µA
−
−
37.5
%Vref
STEEPNESS LEVEL CONTROL STEEP (PIN 22); note 1
Vi(min)
input voltage for minimum steepness
Vi(max)
input voltage for maximum steepness
87.5
−
137.5
%Vref
Ibias
input bias current
−
−
0.5
µA
SMART NOISE CONTROL SNC (PIN 15)
Vnfr
level for no feature reduction
−
0.0
−
V
Vcfr
level for complete feature reduction
−
Vref
−
V
Ibias
input bias current
−
−
1.0
µA
1fH mode
−
175
−
ns
2fH mode
−
108
−
ns
1fH mode; note 7
−
0
10
ns
2fH mode; note 7
−
0
5
ns
Overall group delay performance for luminance
td
delay time from input to output
tde
delay error contour correction
tde1
delay error step correction
1fH mode; note 7
−
0
10
ns
tde2
delay error step correction
2fH mode
−
0
5
ns
1997 Dec 01
11
Philips Semiconductors
Product specification
YUV transient improvement processor
SYMBOL
PARAMETER
TDA9177
CONDITIONS
MIN.
TYP.
MAX.
UNIT
DELAY TIME SELECTION FHS (PIN 17); note 1
Vi1fH
input voltage for 1fH
−
−
0.5
V
Vi2fH
input voltage for 2fH
3.5
−
5.5
V
1.9
−
−
V
Colour difference processing
COLOUR DIFFERENCE INPUTS UIN AND VIN (PINS 7 AND 9)
ViUIN(p-p)
input voltage range UIN, peak-to-peak
ViVIN(p-p)
input voltage range VIN, peak-to-peak
Ibias
input bias current UIN, VIN
Vcl
voltage level during clamping
no clamp
1.9
−
−
V
−
−
0.1
µA
−
4.0
−
V
V
COLOUR DIFFERENCE OUTPUTS UOUT AND, VOUT (PINS 18 AND 16)
Vo(cl)
output voltage level during clamping
−
3.2
−
G
gain
−
1.0
−
Eoff
offset error
transparent
−
0
1
%
EG
gain error
transparent
−
0
5
%
EG(UV)
UV gain tracking error
transparent
−
0
1
%
B
bandwidth
1fH
7
−
−
MHz
2fH
7
−
−
MHz
1fH
−
175
−
ns
2fH
td
delay time
−
108
−
ns
Rout
output resistance
−
−
150
Ω
Iob
output bias current
0.5
−
−
mA
−
2.0
−
V
Successive Approximation ADC
ADEXT1 AND ADEXT2 (PINS 3 AND 10)
VFS
full scale input voltage range
Iib
input bias current
−
−
1
µA
data path
−
6
−
bit
DLE
differential linearity error
−
−
1
LSB
ILE
integral linearity error
−
−
1
LSB
fcon
conversion frequency
each channel
−
0.5fV
−
Hz
Qadt
conversion time (video lines)
each channel
−
8
−
lines
1997 Dec 01
with respect to GND
12
Philips Semiconductors
Product specification
YUV transient improvement processor
SYMBOL
PARAMETER
TDA9177
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Timing
SANDCASTLE INPUT SANDCASTLE (PIN 1)
Vscbn
detection level for blank
no clamping
1.25
1.5
1.75
V
Vscbc
detection level for blank
with clamping and w.r.t. top
level sandcastle pulse
−
−0.6
−
V
tscnV
input blanking width for no V-sync
−
−
15
µs
tscV
input blanking width for V-sync
35
−
−
µs
Vbkvar
ripple on sandcastle burst key level
−
−
0.4
V
1fH
−
0
10
ns
2fH
−
0
5
ns
Overall output group delay performance
tdm(YUV)
delay of matching YUV
Notes
1. This selection is only valid when the standby bit STB is not set.
2. In transparent mode i.e. no step improvement and no peaking, the bandwidth of the luminance path for which the
group delay is constant is 7 MHz in 1fH mode and 14 MHz in 2fH mode. However, as the circuit uses all-pass filters,
ringing on the output signal may occur if the bandwidth of the input signal is larger than 7 MHz in 1fH mode or 14 MHz
in 2fH mode. As the step improvement circuit adds harmonics to the luminance signal, the bandwidth of the output
signal is much larger than 14 MHz.
3. The black level error that may occur will mainly be caused by inaccuracies in the internal clamping circuit. This
internal clamping circuit is activated during 70% of the duration of the burst key pulse on the sandcastle signal.
Integration of the ‘ramp shaped’ black level error during the full duration of the burst key pulse will reduce the black
level error to less than 1%.
4. Peaking set to minimum. Input signal is a sine wave with the nominal peak-to-peak amplitude corresponding to the
selected input range.
5. The contour signal cannot be measured separately from the luminance input signal. The contour signal is also
processed by the smart noise controller. The frequency transfer in the peaking mode of the luminance signal can be
derived from the frequency transfer of the selected contour signal, taking into account the summation of the contour
signal and the luminance input signal. The frequency transfer is most easily measured by sine excitation with a
relatively small signal amplitude of 10% of the selected dynamic range of the luminance input, to avoid interaction
with the step detector.
6. The coring level refers to the internally selected contour signal. It is dependent on the contour filter selected and is
specified for the corresponding peaking centre frequency. The coring level can not be measured explicitly at the
luminance output from a big step or sine excitation, because of its interaction with the step detector.
7. Contour correction and step improvement delays are internal delays and cannot be measured in a straightforward
way. Contour correction delay mismatch results in asymmetrical ‘ears’ with respect to the centre of the transient.
Step improvement correction delay mismatch affects the symmetry of the line width control.
1997 Dec 01
13
Philips Semiconductors
Product specification
YUV transient improvement processor
Figures 3 to 8 show the excitation and response of the
TDA9177 sharpness improvement processor.
The excitation shown in Fig.3 is a 2T-pulse, followed by a
step function. Because the TDA9177 can handle both 1fH
and 2fH signals, figures illustrating both situations could
have been provided. However, as the difference between
these two modes (with respect to the TDA9177) is that the
time scale of a 2fH response diagram is half that of a 1fH
response diagram under equal conditions, only the 1fH
figures are shown.
Figures 5 and 6 show that the width of the signal
processed by the step improvement processor can be
modified by the Line Width Control pin LWC (or DACLW).
Figure 7 shows that the contour processor does not affect
large transients, but works exclusively on small signals,
e.g. details in a video signal.
Figure 8 shows the combination of smart peaking and the
step improvement processor; small signals will be affected
by the contour processor, while large transients will be
modified by the step improvement processor.
Figure 4 shows that the step improvement processor does
not affect small amplitudes. Large transients, however,
acquire steeper edges.
1997 Dec 01
TDA9177
14
Philips Semiconductors
Product specification
YUV transient improvement processor
MBH230
1000
input
signal
(mV)
800
TDA9177
MBH231
1000
Vo
(mV)
handbook, halfpage
handbook, halfpage
(1)
800
(1)
600
600
400
400
(2)
200
(2)
200
0
0
0
0.5
1.0
1.5 t (µs)
0
2.0
1.0
1.5 t (µs)
2.0
(1) 90% of nominal amplitude.
(2) 30% of nominal amplitude.
(1) 90% of nominal amplitude.
(2) 30% of nominal amplitude.
Fig.4
Response signals for maximum step
improvement, no peaking and nominal line
width.
Fig.3 Excitation signals: 90% and 30% of nominal
amplitude 2T-pulse and step function.
MBH232
1000
Vo
(mV)
0.5
MBH233
1000
Vo
(mV)
handbook, halfpage
handbook, halfpage
(1)
800
800
600
600
400
400
200
(1)
200
(2)
(2)
0
0
0
0.5
1.0
1.5 t (µs)
2.0
0
0.5
(1) 90% of nominal amplitude.
(1) 90% of nominal amplitude.
(2) 30% of nominal amplitude.
(2) 30% of nominal amplitude.
Fig.5
Fig.6
Response signals for maximum step
improvement, no peaking and minimum line
width.
1997 Dec 01
15
1.0
1.5 t (µs)
2.0
Response signals for maximum step
improvement, no peaking and maximum
line width.
Philips Semiconductors
Product specification
YUV transient improvement processor
MBH234
1400
MBH235
1400
handbook, halfpage
handbook, halfpage
Vo
(mV)
Vo
(mV)
1000
1000
(1)
(1)
600
600
(2)
200
−200
TDA9177
−200
0
(2)
200
0.5
1.0
1.5 t (µs)
2.0
0
Fig.8
1.5 t (µs)
line width
control
handbook, full pagewidth
MINMAX
SELECTOR
YIN
2.0
Response signals for maximum step
improvement, nominal line width, maximum
peaking and 0% coring.
Response signals for no step improvement,
maximum peaking and 0% coring.
DELAY
CLAMPS
FADER
MINMAX
Yenvelope
MBH236
Fig.9 Block diagram of the step improvement processor.
1997 Dec 01
1.0
(1) 90% of nominal amplitude.
(2) 30% of nominal amplitude.
(1) 90% of nominal amplitude.
(2) 30% of nominal amplitude.
Fig.7
0.5
16
YSTEP
Philips Semiconductors
Product specification
YUV transient improvement processor
TDA9177
handbook, full pagewidth
STEP
DETECTOR
delay cells
coring control
Yenvelope
Ycontour
CORING
Yc
FADER
YSTEP
YSTEP
peaking steepness
control
control
MBH237
smart
noise
Fig.10 Block diagram of the smart sharpness controller.
MBH238
100
handbook, full pagewidth
contour
(%)
80
60
40
(1)
(2)
20
0
104
105
106
(1) 1fH mode.
(2) 2fH mode.
Fig.11 Frequency transfers narrow contour filter.
1997 Dec 01
17
107
f (Hz)
108
Philips Semiconductors
Product specification
YUV transient improvement processor
TDA9177
MBH239
100
handbook, full pagewidth
contour
(%)
80
60
40
(1)
(2)
20
0
104
105
106
107
f (Hz)
(1) 1fH mode.
(2) 2fH mode.
Fig.12 Frequency transfers wide contour filter.
MBH240
100
handbook, halfpage
(%)
75
50
25
0
0
25
50
75
Vref (%)
100
Fig.13 Relative decrease of steepness level as a function of voltage at pin SNC starting from four different
steepness level presets.
1997 Dec 01
18
108
Philips Semiconductors
Product specification
YUV transient improvement processor
TDA9177
MBH241
100
handbook, halfpage
(%)
80
60
40
20
0
0
25
50
75
Vref (%)
100
Fig.14 Relative increase of coring level as a function of voltage at pin SNC starting from four different coring level
presets.
MBH242
100
handbook, halfpage
transfer
(%)
50
0
37.5
50.0
62.5
75
Vref (%)
87.5
Fig.15 Feature setting control as a function of the pin voltage for peaking, coring, steepness and line width.
1997 Dec 01
19
Philips Semiconductors
Product specification
YUV transient improvement processor
TDA9177
INTERNAL CIRCUITRY
handbook, halfpage
handbook, halfpage
275 Ω
275 Ω
1
COR
2
SANDCASTLE
MBH245
MBH244
Fig.16 Simplified circuit diagram pin 1.
Fig.17 Simplified circuit diagram pin 2.
handbook, halfpage
handbook, halfpage
275 Ω
275 Ω
ADEXT1
LWC
100 kΩ
4
3
MBH247
MBH246
Fig.18 Simplified circuit diagram pin 3.
Fig.19 Simplified circuit diagram pin 4.
handbook, halfpage
handbook, halfpage
275 Ω
275 Ω
YIN
ADR
5
MBH249
MBH248
Fig.20 Simplified circuit diagram pin 5.
1997 Dec 01
6
Fig.21 Simplified circuit diagram pin 6.
20
Philips Semiconductors
Product specification
YUV transient improvement processor
handbook, halfpage
TDA9177
handbook, halfpage
275 Ω
275 Ω
CFS
275 Ω
UIN 7
900 Ω
8
1 MΩ
MBH251
MBH250
Fig.22 Simplified circuit diagram pin 7.
Fig.23 Simplified circuit diagram pin 8.
handbook, halfpage
handbook, halfpage
275 Ω
275 Ω
275 Ω
VIN 9
MBH252
100 kΩ
MBH253
Fig.24 Simplified circuit diagram pin 9.
Fig.25 Simplified circuit diagram pin 10.
ndbook, halfpage
handbook, halfpage
275 Ω
PEAK
900 Ω
ADEXT2 10
275 Ω
11
SCL 12
MBH254
MBH255
Fig.26 Simplified circuit diagram pin 11.
1997 Dec 01
Fig.27 Simplified circuit diagram pin 12.
21
Philips Semiconductors
Product specification
YUV transient improvement processor
TDA9177
handbook, halfpage
handbook, halfpage
275 Ω
275 Ω
AMS
SDA 13
900 Ω
14
1 MΩ
MBH257
MBH256
Fig.28 Simplified circuit diagram pin 13.
Fig.29 Simplified circuit diagram pin 14.
handbook, halfpage
handbook, halfpage
275 Ω
100 Ω
SNC 15
16 VOUT
0.5 mA
MBH258
MBH259
Fig.30 Simplified circuit diagram pin 15.
Fig.31 Simplified circuit diagram pin 16.
handbook, halfpage
handbook, halfpage
275 Ω
FHS
900 Ω
100 Ω
17
18 UOUT
1 MΩ
0.5 mA
MBH261
MBH260
Fig.32 Simplified circuit diagram pin 17.
1997 Dec 01
Fig.33 Simplified circuit diagram pin 18.
22
Philips Semiconductors
Product specification
YUV transient improvement processor
TDA9177
handbook, halfpage
handbook, halfpage
GND
100 Ω
19
20 YOUT
MBH262
0.5 mA
MBH263
Fig.34 Simplified circuit diagram pin 19.
Fig.35 Simplified circuit diagram pin 20.
handbook, halfpage
handbook, halfpage
275 Ω
STEEP
VCC
22
21
MBH264
MBH265
Fig.36 Simplified circuit diagram pin 21.
Fig.37 Simplified circuit diagram pin 22.
handbook, halfpage
handbook, halfpage
100 Ω
100 Ω
100 Ω
23 Vref
24 Rext
21 kΩ
MBH266
MBH267
Fig.38 Simplified circuit diagram pin 23.
1997 Dec 01
Fig.39 Simplified circuit diagram pin 24.
23
Philips Semiconductors
Product specification
YUV transient improvement processor
Whenever I2C-bus control is not feasible, the embedded
smart sharpness algorithm can be executed by driving pin
SNC with the output of a noise detector. In this concept,
additional post-processing of the noise detector output can
easily be realized with external components.
APPLICATION INFORMATION
To benefit optimally from its picture-sharpening
capabilities, the TDA9177 should be positioned as the last
part of the YUV-chain.
Feature reduction as a function of the noise contents of the
picture can easily be realized in hardware by using a Noise
Detector. Smart Noise Control (SNC) can be tailor-made
for each application, by means of controlling the peaking
and the steepness values by software (I2C-bus control).
YOUT
handbook, full pagewidth
TDA9177
Figure 40 shows an application example in which the
TDA9177 is bus controlled, with the I2C-bus address at
40H. Furthermore, the Smart Noise Control pin (SNC;
pin 15) is not used in the example shown.
UOUT
VOUT
8V
100
µF
100
nF
0V
10
kΩ
24
23
22
21
20
19
18
17
16
15
14
13
8
9
10
11
12
TDA9177
1
2
3
4
5
6
7
100
nF
sandcastle
YIN
10
nF
UIN
10
nF
VIN
100
Ω
SCL
100
Ω
SDA
MBH243
Fig.40 Application diagram.
1997 Dec 01
24
Philips Semiconductors
Product specification
YUV transient improvement processor
TDA9177
PACKAGE OUTLINE
SDIP24: plastic shrink dual in-line package; 24 leads (400 mil)
SOT234-1
ME
seating plane
D
A2
A
A1
L
c
e
Z
b1
(e 1)
w M
MH
b
13
24
pin 1 index
E
1
12
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
c
D (1)
E (1)
e
e1
L
ME
MH
w
Z (1)
max.
mm
4.7
0.51
3.8
1.3
0.8
0.53
0.40
0.32
0.23
22.3
21.4
9.1
8.7
1.778
10.16
3.2
2.8
10.7
10.2
12.2
10.5
0.18
1.6
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
92-11-17
95-02-04
SOT234-1
1997 Dec 01
EUROPEAN
PROJECTION
25
Philips Semiconductors
Product specification
YUV transient improvement processor
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
Repairing soldered joints
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
Soldering by dipping or by wave
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
1997 Dec 01
TDA9177
26
Philips Semiconductors
Product specification
YUV transient improvement processor
TDA9177
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1997 Dec 01
27
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For all other countries apply to: Philips Semiconductors,
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P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1997
SCA56
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
547047/1200/02/pp28
Date of release: 1997 Dec 01
Document order number:
9397 750 03053