INTEGRATED CIRCUITS 83C748/87C748 80C51 8-bit microcontroller family 2K/64 OTP/ROM, low pin count Preliminary specification Supersedes data of 1998 Apr 23 IC20 Data Handbook 1999 Apr 15 Philips Semiconductors Preliminary specification 80C51 8-bit microcontroller family 2K/64 OTP/ROM, low pin count 83C748/87C748 DESCRIPTION PIN CONFIGURATIONS The Philips 83C748/87C748 offers the advantages of the 80C51 architecture in a small package and at low cost. The 8XC748 Microcontroller is fabricated with Philips high-density CMOS technology. Philips epitaxial substrate minimizes CMOS latch-up sensitivity. P3.4/A4 1 24 VCC P3.3/A3 2 23 P3.5/A5 P3.2/A2/A10 3 22 P3.6/A6 P3.1/A1/A9 4 The 8XC748 contains a 2k × 8 ROM (83C748) EPROM (87C748), a 64 × 8 RAM, 19 I/O lines, a 16-bit auto-reload counter/timer, a four-source, fixed-priority level interrupt structure, and an on-chip oscillator. P3.0/A0/A8 5 P0.2/VPP 6 FEATURES • 80C51 based architecture • Small package sizes 21 P3.7/A7 PLASTIC DUAL IN-LINE AND SHRINK SMALL OUTLINE PACKAGE 20 P1.7/T0/D7 19 P1.6/INT1/D6 18 P1.5/INT0/D5 P0.1/OE–PGM 7 P0.0/ASEL 8 17 P1.4/D4 RST 9 16 P1.3/D3 – 24-pin DIP (300 mil “skinny DIP”) – 24-pin Shrink Small Outline Package (SSOP) X2 10 15 P1.2/D2 X1 11 14 P1.1/D1 VSS 12 13 P1.0/D0 – 28-pin PLCC • 87C748 available in erasable quartz lid or one-time programmable 4 plastic packages 1 26 5 • Wide oscillator frequency range: –3.5 to 16MHz • Low power consumption: 25 PLASTIC LEADED CHIP CARRIER 11 19 – Normal operation: less than 11mA @ 5V, 12MHz 12 – Idle mode – Power-down mode Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 • 2k × 8 ROM (83C748) 2k × 8 EPROM (87C748) • 64 × 8 RAM • 16-bit auto reloadable counter/timer • 10-bit fixed-rate timer • Boolean processor • CMOS and TTL compatible • Well suited for logic replacement, consumer and industrial Function P3.4/A4 P3.3/A3 P3.2/A2/A10 P3.1/A1/A9 NC* P3.0/A0/A8 P0.2/VPP P0.1/OE-PGM P0.0/ASEL NC* RST X2 X1 VSS 18 Pin 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Function P1.0/D0 P1.1/D1 P1.2/D2 P1.3/D3 P1.4/D4 P1.5/INT0/D5 NC* NC* P1.6/INT1/D6 P1.7/T0/D7 P3.7/A7 P3.6/A6 P3.5/A5 VCC SU00295A * NO INTERNAL CONNECTION applications • LED drive outputs ORDERING INFORMATION ROM P83C748EBP N EPROM1 TEMPERATURE RANGE °C AND PACKAGE FREQUENCY MHz DRAWING NUMBER 0 to +70, Plastic Dual In-line Package 3.5 to 16 SOT222-1 P87C748EBP N OTP P83C748EBA A P87C748EBA A OTP 0 to +70, Plastic Leaded Chip Carrier 3.5 to 16 SOT261-3 P83C748EBD DB P87C748EBD DB OTP 0 to +70, Shrink Small Outline Package 3.5 to 16 SOT340-1 NOTE: 1. OTP = One Time Programmable EPROM. 1999 Apr 15 2 Philips Semiconductors Preliminary specification 80C51 8-bit microcontroller family 2K/64 OTP/ROM, low pin count 83C748/87C748 BLOCK DIAGRAM P0.0–P0.2 PORT 0 DRIVERS VCC VSS RAM ADDR REGISTER PORT 0 LATCH RAM B REGISTER ROM/ EPROM STACK POINTER ACC PROGRAM ADDRESS REGISTER TMP1 TMP2 ALU PCON TCON BUFFER IE PSW TH0 TL0 RTH RTL INTERRUPT AND TIMER BLOCKS PC INCREMENTER RST TIMING AND CONTROL INSTRUCTION REGISTER PROGRAM COUNTER PD DPTR PORT 1 LATCH PORT 3 LATCH PORT 1 DRIVERS PORT 3 DRIVERS P1.0–P1.7 P3.0–P3.7 OSCILLATOR X1 X2 SU00296 1999 Apr 15 3 Philips Semiconductors Preliminary specification 80C51 8-bit microcontroller family 2K/64 OTP/ROM, low pin count 83C748/87C748 PIN DESCRIPTIONS PIN NO. DIP/ SSOP LCC TYPE VSS 12 14 I Circuit Ground Potential VCC 24 28 I Supply voltage during normal, idle, and power-down operation. P0.0–P0.2 8–6 9–7 I/O MNEMONIC NAME AND FUNCTION Port 0: Port 0 is a 3-bit open-drain, bidirectional port. Port 0 pins that have 1s written to them float, and in that state can be used as high-impedance inputs. These pins are driven low if the port register bit is written with a 0. The state of the pin can always be read from the port register by the program. P0.0 and P0.1 are open drain bidirectional I/O pins. While these differ from “standard TTL” characteristics, they are close enough for the pins to still be used as general-purpose I/O. Port 0 also provides alternate functions for programming the EPROM memory as follows: VPP (P0.2) – Programming voltage input. (See Note 1). OE/PGM (P0.1) – Input which specifies verify mode (output enable) or the program mode. OE/PGM = 1 output enabled (verify mode). OE/PGM = 0 program mode. ASEL (P0.0) – Input which indicates which bits of the EPROM address are applied to port 3. ASEL = 0 low address byte available on port 3. ASEL = 1 high address byte available on port 3 (only the three least significant bits are used). 6 7 7 8 N/A I 8 9 I 13–20 15–20, 23, 24 I/O 18 19 20 20 23 24 I I I 5–1, 23–21 6, 4–1, 27–25 I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also functions as the address input for the EPROM memory location to be programmed (or verified). The 11-bit address is multiplexed into this port as specified by P0.0/ASEL. RST 9 11 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on RESET using only an external capacitor to VCC. After the device is reset, a 10-bit serial sequence, sent LSB first, applied to RESET, places the device in the programming state allowing programming address, data and VPP to be applied for programming or verification purposes. The RESET serial sequence must be synchronized with the X1 input. X1 11 13 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. X1 also serves as the clock to strobe in a serial bit stream into RESET to place the device in the programming state. P1.0–P1.7 P3.0–P3.7 Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 1 serves to output the addressed EPROM contents in the verify mode and accepts as inputs the value to program into the selected address during the program mode. Port 1 also serves the special function features of the 80C51 family as listed below: INT0 (P1.5): External interrupt. INT1 (P1.6): External interrupt. T0 (P1.7): Timer 0 external input. X2 10 12 O Crystal 2: Output from the inverting oscillator amplifier. NOTE: 1. When P0.2 is at or close to 0 volts, it may affect the internal ROM operation. It is recommended that P0.2 be tied to VCC via a small pull-up (e.g. 2k). ABSOLUTE MAXIMUM RATINGS1, 2 PARAMETER RATING UNIT Storage temperature range –65 to +150 °C Voltage from VCC to VSS –0.5 to +6.5 V –0.5 to VCC + 0.5 V Voltage from any pin to VSS (except VPP) Power dissipation 1.0 W Voltage on VPP pin to VSS 0 to +13.0 V Maximum IOL per I/O pin 10 mA NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 1999 Apr 15 4 Philips Semiconductors Preliminary specification 80C51 8-bit microcontroller family 2K/64 OTP/ROM, low pin count 83C748/87C748 DC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C, VCC = 5V ±10%, VSS = 0V1 SYMBOL PARAMETER VIL VIH VIH1 Input low voltage Input high voltage, except X1, RST Input high voltage, X1, RST VIL1 VIH2 P0.2 Input low voltage Input high voltage VOL VOL1 Output low voltage, ports 1 and 3 Output low voltage, port 0.2 IOL = 1.6mA2 IOL = 3.2mA2 VOH Output high voltage, ports 1 and 3 IOH = –60µA IOH = –25µA IOH = –10µA C Port 0.0 and 0.1 – Drivers Output low voltage Driver, receiver combined: Capacitance IIL ITL ILI Logical 0 input current, ports 1 and 3 Logical 1 to 0 transition current, ports 1 and 33 Input leakage current, port 0 RRST Internal pull-down resistor VOL2 LIMITS TEST CONDITIONS UNIT MIN MAX –0.5 0.2VCC+0.9 0.7VCC 0.2VDD–0.1 VCC+0.5 VCC+0.5 V V V –0.5 0.7VCC 0.3VCC VCC+0.5 V V 0.45 0.45 V V 2.4 0.75VCC 0.9VCC IOL = 3mA (over VCC range) VIN = 0.45V VIN = 2V (0 to 70°C) 0.45 < VIN < VCC 25 V V V 0.4 V 10 pF –50 –650 ±10 µA µA µA 175 kΩ Test freq = 1MHz, Tamb = 25°C 10 pF 50 µA 13.0 V 50 mA CIO Pin capacitance IPD Power-down current4 VCC = 2 to VCC max VPP VPP program voltage (for 87C748 only) VSS = 0V VCC = 5V±10% Tamb = 21°C to 27°C IPP Program current (for 87C748 only) ICC Supply current (see Figure 2) VPP = 13.0V 12.5 NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. 2. Under steady state (non-transient) conditions, IOL must be externally limited as follows: 10mA Maximum IOL per port pin: Maximum IOL per 8-bit port: 26mA 67mA Maximum total IOL for all outputs: If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 3. Pins of ports 1 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2V. 4. Power-down ICC is measured with all output pins disconnected; port 0 = VCC; X2, X1 n.c.; RST = VSS. 5. Active ICC is measured with all output pins disconnected; X1 driven with tCLCH, tCHCL = 5ns, VIL = VSS + 0.5V, VIH = VCC – 0.5V; X2 n.c.; RST = port 0 = VCC. ICC will be slightly higher if a crystal oscillator is used. 6. Idle ICC is measured with all output pins disconnected; X1 driven with tCLCH, tCHCL = 5ns, VIL = VSS + 0.5V, VIH = VCC – 0.5V; X2 n.c.; port 0 = VCC; RST = VSS. 1999 Apr 15 5 Philips Semiconductors Preliminary specification 80C51 8-bit microcontroller family 2K/64 OTP/ROM, low pin count 83C748/87C748 AC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C, VCC = 5V ±10%, VSS = 0V1, 2 16MHz CLOCK SYMBOL 1/tCLCL PARAMETER MIN MAX Oscillator frequency: VARIABLE CLOCK MIN MAX UNIT 3.5 3.5 12 16 MHz MHz External Clock (Figure 1) tCHCX High time 20 20 ns tCLCX Low time 20 tCLCH Rise time 20 20 ns tCHCL Fall time 20 20 ns 20 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. 2. Load capacitance for ports = 80pF. EXPLANATION OF THE AC SYMBOLS L Q T V X Z Each timing symbol has five characters. The first character is always ‘t’ (= time). The other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. The designations are: C – Clock D – Input data H – Logic level high – – – – – – Logic level low Output data Time Valid No longer a valid logic level Float tCLCX VCC –0.5 0.2 VCC + 0.9 0.2 VCC – 0.1 tCHCX 0.45V tCLCH tCHCL tCLCL SU00297 Figure 1. External Clock Drive ROM CODE SUBMISSION When submitting ROM code for the 83C748, the following must be specified: 1. 2k byte user ROM data ADDRESS CONTENT BIT(S) COMMENT 0000H to 07FFH DATA 7:0 User ROM Data 1999 Apr 15 6 Philips Semiconductors Preliminary specification 80C51 8-bit microcontroller family 2K/64 OTP/ROM, low pin count 83C748/87C748 MAX ACTIVE ICC5 22 20 18 16 14 ICC (mA) TYP ACTIVE ICC5 12 10 8 6 MAX IDLE ICC6 4 2 TYP IDLE ICC6 4MHz 8MHz 12MHz 16MHz FREQ SU00298 Figure 2. ICC vs. FREQ Maximum ICC values taken at VCC max and worst case temperature. Typical ICC values taken at VCC = 5.0V and 25°C. Notes 5 and 6 refer to DC Electrical Characteristics. idle mode is activated. The CPU contents, the on-chip RAM, and all of the special function registers remain intact during this mode. The idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset. OSCILLATOR CHARACTERISTICS X1 and X2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator. To drive the device from an external clock source, X1 should be driven while X2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. However, minimum and maximum high and low times specified in the data sheet must be observed. POWER-DOWN MODE In the power-down mode, the oscillator is stopped and the instruction to invoke power-down is the last instruction executed. Only the contents of the on-chip RAM are preserved. A hardware reset is the only way to terminate the power-down mode. the control bits for the reduced power modes are in the special function register PCON. RESET A reset is accomplished by holding the RST pin high for at least two machine cycles (24 oscillator periods), while the oscillator is running. To insure a good power-up reset, the RST pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. At power-up, the voltage on VCC and RST must come up at the same time for a proper start-up. Table 1. MODE IDLE MODE Idle Power-down In idle mode, the CPU puts itself to sleep while all of the on-chip peripherals stay active. The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the 1999 Apr 15 7 External Pin Status During Idle and Power-Down Modes Port 0 Port 1 Port 2 Data Data Data Data Data Data Philips Semiconductors Preliminary specification 80C51 8-bit microcontroller family 2K/64 OTP/ROM, low pin count 83C748/87C748 DIFFERENCES BETWEEN THE 8XC748 AND THE 80C51 Interrupt Subsystem – Fixed Priority The IP register and the 2-level interrupt system of the 80C51 are eliminated. Simultaneous interrupt conditions are resolved by a single-level, fixed priority as follows: Memory Organization The central processing unit (CPU) manipulates operands in two address spaces as shown in Figure 3. The part’s internal memory space consists of 2k bytes of program memory, and 64 bytes of data RAM overlapped with the 128-byte special function register area. The differences from the 80C51 are in RAM size (64 bytes vs. 128 bytes), in external RAM access (not available on the 83C748), in internal ROM size (2k bytes vs. 4k bytes), and in external program memory expansion (not available on the 83C748). The 128-byte special function register (SFR) space is accessed as on the 80C51 with some of the registers having been changed to reflect changes in the 83C748 peripheral functions. The stack may be located anywhere in internal RAM by loading the 8-bit stack pointer (SP). It should be noted that stack depth is limited to 64 bytes, the amount of available RAM. A reset loads the stack pointer with 07 (which is pre-incremented on a PUSH instruction). Highest priority: Lowest priority: Pin INT0 Counter/timer flag 0 Pin INT1 Timer I Special Function Register – Interrupt Subsystem Because the interrupt structure is single level on the 83C748, there is no need for the IP SFR, so it is not used. Special Function Register – Serial Communications The 8XC748 contains many of the special function registers (SFR) that are found on the 80C51. Due to the different peripheral features on the 8XC748, there are several additional SFRs. Since the UART found on 80C51 has been removed, the UART SFRs SCON and SBUF have also been removed. Program Memory On the 8XC748, program memory is 2048 bytes long and is not externally expandable, so the 80C51 instructions MOVX, LJMP, and LCALL are not implemented. The only fixed locations in program memory are the addresses at which execution is taken up in response to reset and interrupts, which are as follows: Program Memory Event Address Reset 000 External INT0 003 Counter/timer 0 00B External INT1 013 Timer I 01B I/O Port Latches (P0, P1, P3) The port latches function the same as those on the 80C51. Since there is no port 2 on the 83C748, the P2 latch is not used. Port 0 on the 83C748 has only 3 bits, so only 3 bits of the P0 SFR have a useful function. Data Pointer (DPTR) The data pointer (DPTR) consists of a high byte (DPH) and a low byte (DPL). In the 80C51 this register allows the access of external data memory using the MOVX instruction. Since the 83C748 does not support MOVX or external memory accesses, this register is generally used as a 16-bit offset pointer of the accumulator in a MOVC instruction. DPTR may also be manipulated as two independent 8-bit registers. Counter/Timer Subsystem The 8XC748 has one counter/timer called timer/counter 0. Its operation is similar to mode 2 operation on the 80C51, but is extended to 16 bits with 16 bits of autoload. The controls for this counter are centralized in a single register called TCON. (FFH) 255 Timer I is available for use as a fixed 10-bit time-base, or as a watchdog. Special Function Registers Counter Timer – Special Function Register The counter/timer has only one mode of operation, so the TMOD SFR is not used. There is also only one counter/timer, so there is no need for the TL1 and TH1 SFRs found on the 80C51. These have been replaced on the 8XC748 by RTL and RTH, the counter/timer reload registers. Table 2 shows the special function registers, their locations, and reset values. (80H) 128 (3FH) 63 Internal Data RAM (00H) 0 SU00299 Figure 3. Memory Map 1999 Apr 15 8 Philips Semiconductors Preliminary specification 80C51 8-bit microcontroller family 2K/64 OTP/ROM, low pin count Table 2. 83C748/87C748 8XC748 Special Function Registers SYMBOL DESCRIPTION DIRECT BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION ADDRESS MSB LSB RESET VALUE ACC* Accumulator E0H E7 E6 E5 E4 E3 E2 E1 E0 00H B* B register F0H F7 F6 F5 F4 F3 F2 F1 F0 00H DPTR: Data pointer (2 bytes) High byte Low byte 83H 82H DPH DPL 00H 00H AF AE AD AC AB AA A9 A8 EX1 ET0 EX0 IE*# Interrupt enable ABH EA – – – ETI 82 81 80 P0*# Port 0 80H – – – – – – – – 97 96 95 94 93 92 91 90 00H xxxxx111B P1* Port 1 90H T0 INT1 INT0 – – – – – FFH P3* Port 3 B0H B7 B6 B5 B4 B3 B2 B1 B0 FFH PCON# Power control 87H – – – – – – PD IDL xxxxxx00B D7 D6 D5 D4 D3 D2 D1 D0 PSW* Program status word D0H CY AC F0 RS1 RS0 OV – P SP Stack pointer 81H 8F 8E 8D 8C 8B 8A 89 88 GATE C/T TF TR IE0 IT0 IE1 IT1 TCON*# Timer/counter control 88H TL# TH# Timer low byte Timer high byte 8AH 8CH TICON*# Timer I control RTL# Timer low reload 07H DF DE DD DC DB DA D9 D8 D8H/RD – WR – – 0 TIRUN – – – – – CLRTI TIRUN – – – – 8BH 0000xx00B 00H 00H Timer/Counter The 8XC748 has two timers: a 16-bit timer/counter and a 10-bit fixed-rate timer. The 16-bit timer/counter’s operation is similar to mode 2 operation on the 80C51, but is extended to 16 bits. The timer/counter is clocked by either 1/12 the oscillator frequency or by transitions on the T0 pin. The C/T pin in special function register TCON selects between these two modes. When the TCON TR bit is set, the timer/counter is enabled. Register pair TH and TL are incremented by the clock source. When the register pair overflows, the register pair is reloaded with the values in registers RTH and RTL. The value in the reload registers is left unchanged. See the 83C748 counter/timer block diagram in Figure 4. The TF bit in special function register TCON is set on counter overflow and, if the interrupt is enabled, will generate an interrupt. I/O Port Structure The 8XC748 has two 8-bit ports (ports 1 and 3) and one 3-bit port (port 0). All three ports on the 8XC748 are bidirectional. Each consists of a latch (special function register P0, P1, P3), an output driver, and an input buffer. Three port 1 pins and two port 0 pins are multifunctional. In addition to being port pins, these pins serve the function of special features as follows: Alternate Function INT0 (external interrupt 0 input) INT1 (external interrupt 1 input) T0 (timer 0 external input) Ports 1 and 3 are identical in structure to the same ports on the 80C51. The structure of port 0 on the 8XC748 is similar to that of the 80C51 but does not include address/data input and output circuitry. As on the 80C51, ports 1 and 3 are quasi-bidirectional while port 0 is bidirectional with no internal pullups. 1999 Apr 15 00H 00H 00H RTH# Timer high reload 8DH * SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs. Port Pin P1.5 P1.6 P1.7 00H 9 Philips Semiconductors Preliminary specification 80C51 8-bit microcontroller family 2K/64 OTP/ROM, low pin count 83C748/87C748 TCON Register MSB GATE GATE C/T TF TR IE0 IT0 IE1 IT1 Interrupts The interrupt structure is a four-source, one-level interrupt system. Interrupt sources common to the 80C51 are the external interrupts (INT0, INT1) and the timer/counter interrupt (ET0). Timer I interrupt (ETI) is the other interrupt source. The interrupt sources are listed below in their order of polling sequence priority. LSB C/T TF TR IE0 IT0 IE1 IT1 1 – Timer/counter is enabled only when INT0 pin is high, and TR is 1. 0 – Timer/counter is enabled when TR is 1. 1 – Counter/timer operation from T0 pin. 0 – Timer operation from internal clock. 1 – Set on overflow of TH. 0 – Cleared when processor vectors to interrupt routine and by reset. 1 – Timer/counter enabled. 0 – Timer/counter disabled. 1 – Edge detected in INT0. 1 – INT0 is edge triggered. 0 – INT0 is level sensitive. 1 – Edge detected on INT1. 1 – INT1 is edge triggered. 0 – INT1 is level sensitive. Upon interrupt or reset the program counter is loaded with specific values for the appropriate interrupt service routine in program memory. These values are: Event Reset INT0 Counter/Timer 0 INT1 Timer I Priority Highest Lowest The interrupt enable register (IE) is used to individually enable or disable the four sources. Bit EA in the interrupt enable register can be used to globally enable or disable all interrupt sources. The interrupt enable register is described below. All other interrupt details are based on the 80C51 interrupt architecture. These flags are functionally identical to the corresponding 80C51 flags, except that there is only one timer on the 83C748 and the flags are therefore combined into one register. Interrupt Enable Register Note that the positions of the IE0/IT0 and IE1/IT1 bits are transposed from the positions used in the standard 80C51 TCON register. EA X X Symbol Position EA IE.7 Timer I Implementation Timer I is clocked once per machine cycle, which is the oscillator frequency divided by 12. The timer operation is enabled by setting the TIRUN bit (bit 4) in the I2CFG register. Writing a 0 into the TIRUN bit will stop and clear the timer. The timer is 10 bits wide, and when it reaches the terminal count of 1024, it carries out and sets the Timer I interrupt flag. An interrupt will occur if the Timer I interrupt is enabled by bit ETI (bit 4) of the Interrupt Enable (IE) register, and global interrupts are enabled by bit EA (bit 7) of the same IE register. The vector address for the Timer I interrupt is 1Bhex, and the interrupt service routine must start at this address. As with all 8051 family microcontrollers, only the Program Counter is pushed onto the stack upon interrupt (other registers that are used both by the interrupt service routine and elsewhere must be explicitly saved). The Timer I interrupt flag is cleared by setting the CKRTI bit (bit 5 of the I1CFG register. For more information, see application note AN427. OSC Program Memory Address 000 003 00B 013 01B – – – ETI IE.6 IE.5 IE.4 IE.3 EX1 IE.2 ET0 IE.1 EX0 IE.0 — ETI EX1 ET0 Function Disables all interrupts. If EA = 0, no interrupt will be acknowledged. If EA = 1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit Reserved Reserved Reserved Enables or disables the Timer I overflow interrupt. If ET1 = 0, the Timer I interrupt is disabled. Enables or disables external interrupt 1. If EX1 = 0, external interrupt 1 is disabled. Enables or disables the Timer 0 overflow interrupt. If ET0 = 0, theTimer 0 interrupt is disabled. Enables or disables external interrupt 0. If EX0 = 0, external interrupt 0 is disabled. ÷ 12 C/T = 0 TL TH TF Int. C/T = 1 T0 Pin TR Reload Gate RTL RTH INT0 Pin SU00300 Figure 4. 83C748 Counter/Timer Block Diagram 1999 Apr 15 10 EX0 Philips Semiconductors Preliminary specification 80C51 8-bit microcontroller family 2K/64 OTP/ROM, low pin count 83C748/87C748 the EPROM array is then placed on Port 1. This is followed by a series of programming pulses applied to the PGM/ pin (P0.1). These pulses are created by driving P0.1 low and then high. This pulse is repeated until a total of 25 programming pulses have occurred. At the conclusion of the last pulse, the PGM/ signal should remain high. 87C748 PROGRAMMING CONSIDERATIONS EPROM Characteristics The 87C748 is programmed by using a modified Quick-Pulse Programming algorithm similar to that used for devices such as the 87C451 and 87C51. It differs from these devices in that a serial data stream is used to place the 87C748 in the programming mode. The VPP signal may now be driven to the VOH level, placing the 87C748 in the verify mode. (Port 1 is now used as an output port). After four machine cycles (48 clock periods), the contents of the addressed location in the EPROM array will appear on Port 1. Figure 5 shows a block diagram of the programming configuration for the 87C748. Port pin P0.2 is used as the programming voltage supply input (VPP signal). Port pin P0.1 is used as the program (PGM/) signal. This pin is used for the 25 programming pulses. The next programming cycle may now be initiated by placing the address information at the inputs of the multiplexed buffers, driving the VPP pin to the VPP voltage level, providing the byte to be programmed to Port1 and issuing the 26 programming pulses on the PGM/ pin, bringing VPP back down to the VC level and verifying the byte. Port 3 is used as the address input for the byte to be programmed and accepts both the high and low components of the eleven bit address. Multiplexing of these address components is performed using the ASEL input. The user should drive the ASEL input high and then drive port 3 with the high order bits of the address. ASEL should remain high for at least 13 clock cycles. ASEL may then be driven low which latches the high order bits of the address internally. the high address should remain on port 3 for at least two clock cycles after ASEL is driven low. Port 3 may then be driven with the low byte of the address. The low address will be internally stable 13 clock cycles later. The address will remain stable provided that the low byte placed on port 3 is held stable and ASEL is kept low. Note: ASEL needs to be pulsed high only to change the high byte of the address. Programming Modes The 87C748 has four programming features incorporated within its EPROM array. These include the USER EPROM for storage of the application’s code, a 16-byte encryption key array and two security bits. Programming and verification of these four elements are selected by a combination of the serial data stream applied to the RESET pin and the voltage levels applied to port pins P0.1 and P0.2. The various combinations are shown in Table 3. Port 1 is used as a bidirectional data bus during programming and verify operations. During programming mode, it accepts the byte to be programmed. During verify mode, it provides the contents of the EPROM location specified by the address which has been supplied to Port 3. Table 3. Implementing Program/Verify Modes The XTAL1 pin is the oscillator input and receives the master system clock. This clock should be between 1.2 and 6MHz. The RESET pin is used to accept the serial data stream that places the 87C748 into various programming modes. This pattern consists of a 10-bit code with the LSB sent first. Each bit is synchronized to the clock input, X1. SERIAL CODE P0.1 (PGM/) P0.2 (VPP) Program user EPROM Verify user EPROM Program key EPROM Verify key EPROM Program security bit 1 Program security bit 2 Verify security bits 296H 296H 292H 292H 29AH 298H 29AH –* VIH –* VIH –* –* VIH VPP VIH VPP VIH VPP VPP VIH NOTE: * Pulsed from VIH to VIL and returned to VIH. Programming Operation Figures 6 and 7 show the timing diagrams for the program/verify cycle. RESET should initially be held high for at least two machine cycles. P0.1 (PGM/) and P0.2 (VPP) will be at VOH as a result of the RESET operation. At this point, these pins function as normal quasi-bidirectional I/O ports and the programming equipment may pull these lines low. However, prior to sending the 10-bit code on the RESET pin, the programming equipment should drive these pins high (VIH). The RESET pin may now be used as the serial data input for the data stream which places the 87C748 in the programming mode. Data bits are sampled during the clock high time and thus should only change during the time that the clock is low. Following transmission of the last data bit, the RESET pin should be held low. Encryption Key Table The 87C748 includes a 16-byte EPROM array that is programmable by the end user. The contents of this array can then be used to encrypt the program memory contents during a program memory verify operation. When a program memory verify operation is performed, the contents of the program memory location is XNOR’ed with one of the bytes in the 16-byte encryption table. The resulting data pattern is then provided to port 1 as the verify data. The encryption mechanism can be disable, in essence, by leaving the bytes in the encryption table in their erased state (FFH) since the XNOR product of a bit with a logical one will result in the original bit. The encryption bytes are mapped with the code memory in 16-byte groups. the first byte in code memory will be encrypted with the first byte in the encryption table; the second byte in code memory will be encrypted with the second byte in the encryption table and so forth up to and including the 16the byte. The encryption repeats in 16-byte groups; the 17th byte in the code memory will be encrypted with the first byte in the encryption table, and so forth. Next the address information for the location to be programmed is placed on port 3 and ASEL is used to perform the address multiplexing, as previously described. At this time, port 1 functions as an output. A high voltage VPP level is then applied to the VPP input (P0.2). (This sets Port 1 as an input port). The data to be programmed into 1999 Apr 15 OPERATION 11 Philips Semiconductors Preliminary specification 80C51 8-bit microcontroller family 2K/64 OTP/ROM, low pin count 83C748/87C748 Security bit 2, the verify inhibit bit, prevents verification of both the USER EPROM array and the encryption key arrays. The security bit levels may still be verified. Security Bits Two security bits, security bit 1 and security bit 2, are provided to limit access to the USER EPROM and encryption key arrays. Security bit 1 is the program inhibit bit, and once programmed performs the following functions: 1. Additional programming of the USER EPROM is inhibited. Programming and Verifying Security Bits Security bits are programmed employing the same techniques used to program the USER EPROM and KEY arrays using serial data streams and logic levels on port pins indicated in Table 3. When programming either security bit, it is not necessary to provide address or data information to the 87C748 on ports 1 and 3. 2. Additional programming of the encryption key is inhibited. 3. Verification of the encryption key is inhibited. 4. Verification of the USER EPROM and the security bit levels may still be performed. Verification occurs in a similar manner using the RESET serial stream shown in Table 3. Port 3 is not required to be driven and the results of the verify operation will appear on ports 1.6 and 1.7. (If the encryption key array is being used, this security bit should be programmed by the user to prevent unauthorized parties from reprogramming the encryption key to all logical zero bits. Such programming would provide data during a verify cycle that is the logical complement of the USER EPROM contents). Ports 1.7 contains the security bit 1 data and is a logical one if programmed and a logical zero if not programmed. Likewise, P1.6 contains the security bit 2 data and is a logical one if programmed and a logical zero if not programmed. EPROM PROGRAMMING AND VERIFICATION Tamb = 21°C to +27°C, VCC = 5V ±10%, VSS = 0V SYMBOL 1/tCLCL tAVGL 1 PARAMETER Oscillator/clock frequency Address setup to P0.1 (PROG–) low MIN MAX UNIT 1.2 6 MHz 10µs + 24tCLCL tGHAX Address hold after P0.1 (PROG–) high 48tCLCL tDVGL Data setup to P0.1 (PROG–) low 38tCLCL tGHDX Data hold after P0.1 (PROG–) high 36tCLCL tSHGL VPP setup to P0.1 (PROG–) low 10 µs tGHSL VPP hold after P0.1 (PROG–) 10 µs tGLGH P0.1 (PROG–) width 90 tAVQV2 VPP low (VCC) to data valid tGHGL P0.1 (PROG–) high to P0.1 (PROG–) low tMASEL ASEL high time 13tCLCL tHAHLD Address hold time 2tCLCL tHASET Address setup to ASEL 13tCLCL tADSTA Low address to valid data µs µs 10 48tCLCL NOTES: 1. Address should be valid at least 24tCLCL before the rising edge of P0.2 (VPP). 2. For a pure verify mode, i.e., no program mode in between, tAVQV is 14tCLCL maximum. 1999 Apr 15 110 48tCLCL 12 Philips Semiconductors Preliminary specification 80C51 8-bit microcontroller family 2K/64 OTP/ROM, low pin count 83C748/87C748 87C748 A0–A10 ADDRESS STROBE P3.0–P3.7 VCC P0.0/ASEL VSS PROGRAMMING PULSES P0.1 VPP/VIH VOLTAGE SOURCE P0.2 +5V P1.0–P1.7 DATA BUS XTAL1 CLK SOURCE RESET CONTROL LOGIC RESET SU00301 Figure 5. Programming Configuration XTAL1 MIN 2 MACHINE CYCLES RESET TEN BIT SERIAL CODE BIT 0 P0.2 UNDEFINED P0.1 UNDEFINED BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BIT 9 SU00302 Figure 6. Entry into Program/Verify Modes 12.75V P0.2 (VPP) 5V 5V tSHGL tGHSL 25 PULSES P0.1 (PGM) tGLGH tMASEL tGHGL 98µs MIN 10µs MIN tAVGL P0.0 (ASEL) tHASET PORT 3 tHAHLD HIGH ADDRESS LOW ADDRESS tADSTA PORT 1 INVALID DATA tDVGL VALID DATA tGHDX DATA TO BE PROGRAMMED VERIFY MODE PROGRAM MODE tAVQV INVALID DATA VALID DATA VERIFY MODE SU00303 Figure 7. Program/Verify Cycle 1999 Apr 15 13 Philips Semiconductors Preliminary specification 80C51 8-bit microcontroller family, 2K/64 OTP/ROM, low pin count 83C748/87C748 DIP24: plastic dual in-line package; 24 leads (300 mil) 1999 Apr 15 14 SOT222-1 Philips Semiconductors Preliminary specification 80C51 8-bit microcontroller family, 2K/64 OTP/ROM, low pin count 83C748/87C748 PLCC28: plastic leaded chip carrer; 28 leads; pedestal 1999 Apr 15 15 SOT261-3 Philips Semiconductors Preliminary specification 80C51 8-bit microcontroller family, 2K/64 OTP/ROM, low pin count 83C748/87C748 SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm 1999 Apr 15 16 SOT340-1 Philips Semiconductors Preliminary specification 80C51 8-bit microcontroller family, 2K/64 OTP/ROM, low pin count 83C748/87C748 NOTES 1999 Apr 15 17 Philips Semiconductors Preliminary specification 80C51 8-bit microcontroller family, 2K/64 OTP/ROM, low pin count 83C748/87C748 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1999 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Date of release: 04-99 Document order number: 1999 Apr 15 18 9397 750 05736