INTEGRATED CIRCUITS 74LV374 Octal D-type flip-flop; positive edge-trigger (3-State) Product specification Supersedes data of 1996 Feb IC24 Data Handbook 1997 Mar 20 Philips Semiconductors Product specification 74LV374 Octal D-type flip-flop; positive edge-trigger (3-State) FEATURES DESCRIPTION • Wide operating voltage: 1.0 to 5.5V • Optimized for Low Voltage applications: 1.0 to 3.6V • Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V • Typical VOLP (output ground bounce) 0.8V @ VCC = 3.3V, The 74LV374 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT374. The 74LV374 is an octal D-type flip–flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A clock (CP) and an output enable (OE) input are common to all flip-flops. Tamb = 25°C • Typical VOHV (output VOH undershoot) 2V @ VCC = 3.3V, The eight flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition. Tamb = 25°C • Common 3-State output enable input • Output capability: bus driver • ICC category: MSI When OE is LOW, the contents of the eight flip-flops is available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; tr =tf 2.5 ns SYMBOL PARAMETER CONDITIONS TYPICAL UNIT 14 ns CL = 15pF VCC = 3.3V tPHL/tPLH Propagation delay CP to Qn fmax Maximum clock frequency 77 MHz CI Input capacitance 3.5 pF CPD Power dissipation capacitance per flip-flop 25 pF Notes 1 and 2 NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD VCC2 x fi (CL VCC2 fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL VCC2 fo) = sum of the outputs. 2. The condition is VI = GND to VCC ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. # 20-Pin Plastic DIL –40°C to +125°C 74LV374 N 74LV374 N SOT146-1 20-Pin Plastic SO –40°C to +125°C 74LV374 D 74LV374 D SOT163-1 20-Pin Plastic SSOP Type II –40°C to +125°C 74LV374 DB 74LV374 DB SOT339-1 PIN DESCRIPTION PIN NUMBER 1 FUNCTION TABLE SYMBOL OE FUNCTION Q0 to Q7 3-State flip-flop outputs 3, 4, 7, 8, 13, 14, 17, 18 D0 to D7 Data inputs 10 GND Ground (0V) 11 CP Clock input (LOW-to-HIGH, edgetriggered) 20 VCC Positive supply voltage H h L l Z ↑ 1997 Mar 20 OE CP Load and read register L L ↑ ↑ Load register and disable outputs H H ↑ ↑ Output enable input (active-LOW) 2, 5, 6, 9, 12, 15, 16, 19 2 INPUTS OPERATING MODES OUTPUTS Dn INTERNAL FLIP-FLOPS l h L H L H l h L H Z Z = HIGH voltage level = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition = LOW voltage level = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition = High impedance OFF-state = LOW–to–HIGH clock transition Q0 to Q7 Philips Semiconductors Product specification 74LV374 Octal D-type flip-flop; positive edge-trigger (3-State) PIN CONFIGURATION LOGIC SYMBOL OE 1 20 VCC Q0 2 19 Q7 D0 3 18 D7 D1 4 17 D6 Q1 5 16 Q6 Q2 6 15 Q5 D2 7 D3 Q3 11 CP 3 D0 Q0 2 4 D1 Q1 5 7 D2 Q2 6 8 D3 Q3 9 14 D5 13 D4 Q4 12 8 13 D4 14 D5 Q5 15 9 12 Q4 17 D6 Q6 16 GND 10 11 CP 18 D7 Q7 19 OE SV00338 1 SV00339 LOGIC SYMBOL (IEEE/IEC) 11 FUNCTIONAL DIAGRAM C1 1 EN1 3 2 1D 4 5 7 6 3 D0 Q0 4 D1 Q1 5 7 D2 Q2 6 8 D3 Q3 9 Q4 12 FF1 to FF8 3-STATE OUTPUTS 2 8 9 13 D4 13 12 14 D5 Q5 15 14 15 17 D6 Q6 16 17 16 18 D7 Q7 19 18 19 11 CP 1 OE SV00340 SV00341 LOGIC DIAGRAM D0 D1 D Q D2 D CP Q D CP FF1 D3 Q D CP FF2 D4 Q D CP FF3 D5 Q D CP FF4 D6 Q D CP FF5 D7 Q D CP FF6 Q CP FF7 FF8 CP OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 SV00342 1997 Mar 20 3 Philips Semiconductors Product specification 74LV374 Octal D-type flip-flop; positive edge-trigger (3-State) ABSOLUTE MAXIMUM RATINGS1, 2 In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) PARAMETER SYMBOL VCC DC supply voltage ±IIK DC input diode current ±IOK ±IO ±IGND, ±ICC Tstg PTOT CONDITIONS RATING UNIT –0.5 to +7.0 V VI < –0.5 or VI > VCC + 0.5V 20 mA DC output diode current VO < –0.5 or VO > VCC + 0.5V 50 mA DC output source or sink current – standard outputs – bus driver outputs –0.5V < VO < VCC + 0.5V 25 35 mA 50 70 mA –65 to +150 °C DC VCC or GND current for types with –standard outputs –bus driver outputs Storage temperature range Power dissipation per package –plastic DIL –plastic mini-pack (SO) –plastic shrink mini-pack (SSOP and TSSOP) for temperature range: –40 to +125°C above +70°C derate linearly with 12mW/K above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K 750 500 400 mW NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER CONDITIONS MIN TYP. See Note1 DC supply voltage MAX UNIT 1.0 3.3 5.5 V VI Input voltage 0 – VCC V VO Output voltage 0 – VCC V +85 +125 °C 500 200 100 50 ns/V Tamb Operating ambient temperature range in free air tr, tf Input rise and fall times except for Schmitt-trigger inputs See DC and AC characteristics per device –40 –40 VCC = 1.0V to 2.0V VCC = 2.0V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V to 5.5V – – – – – – – NOTES: 1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V. 1997 Mar 20 4 Philips Semiconductors Product specification 74LV374 Octal D-type flip-flop; positive edge-trigger (3-State) DC CHARACTERISTICS FOR THE LV FAMILY Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS SYMBOL PARAMETER -40°C to +85°C TEST CONDITIONS MIN VIH VIL HIGH level Input voltage LOW level Input voltage TYP1 VOH VOH VOL VOL VOL II IOZ ICC ICC ∆ICC 0.9 0.9 1.4 1.4 VCC = 2.7 to 3.6V 2.0 2.0 VCC = 4.5 to 5.5V 0.7*VCC V 0.7*VCC 0.3 0.3 VCC = 2.0V 0.6 0.6 VCC = 2.7 to 3.6V 0.8 0.8 0.3*VCC 0.3*VCC V 1.2 VCC = 2.0V; VI = VIH or VIL; –IO = 100µA 1.8 2.0 1.8 VCC = 2.7V; VI = VIH or VIL; –IO = 100µA 2.5 2.7 2.5 VCC = 3.0V; VI = VIH or VIL; –IO = 100µA 2.8 3.0 2.8 VCC = 4.5V;VI = VIH or VIL; –IO = 100µA 4.3 4.5 4.3 HIGH level output voltage; g STANDARD outputs VCC = 3.0V;VI = VIH or VIL; –IO = 6mA 2.40 2.82 2.20 VCC = 4.5V;VI = VIH or VIL; –IO = 12mA 3.60 4.20 3.50 HIGH level output voltage; BUS driver outputs VCC = 3.0V;VI = VIH or VIL; –IO = 8mA 2.40 2.82 2.20 VCC = 4.5V;VI = VIH or VIL; –IO = 16mA 3.60 4.20 3.50 LOW level output voltage all outputs out uts voltage; UNIT MAX VCC = 1.2V V V V VCC = 1.2V; VI = VIH or VIL; IO = 100µA VCC = 2.0V; VI = VIH or VIL; IO = 100µA 0 0 0.2 0.2 VCC = 2.7V; VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VCC = 3.0V;VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VCC = 4.5V;VI = VIH or VIL; IO = 100µA 0 0.2 0.2 V LOW level output voltage; g STANDARD outputs VCC = 3.0V;VI = VIH or VIL; IO = 6mA 0.25 0.40 0.50 VCC = 4.5V;VI = VIH or VIL; IO = 12mA 0.35 0.55 0.65 LOW level output voltage; BUS driver outputs VCC = 3.0V;VI = VIH or VIL; IO = 8mA 0.20 0.40 0.50 VCC = 4.5V;VI = VIH or VIL; IO = 16mA 0.35 0.55 0.65 1.0 1.0 µA 5 10 µA V V Input leakage current VCC = 5.5V; VI = VCC or GND 3-State output OFF-state current VCC = 5.5V; VI = VIH or VIL; VO = VCC or GND Quiescent supply current; SSI VCC = 5.5V; VI = VCC or GND; IO = 0 20.0 40 Quiescent supply current; flip-flops VCC = 5.5V; VI = VCC or GND; IO = 0 20.0 80 Quiescent supply current; MSI VCC = 5.5V; VI = VCC or GND; IO = 0 20.0 160 Quiescent supply current; LSI VCC = 5.5V; VI = VCC or GND; IO = 0 500 1000 Additional quiescent supply current per input VCC = 2.7V to 3.6V; VI = VCC –0.6V 500 850 NOTE: 1. All typical values are measured at Tamb = 25°C. 1997 Mar 20 MIN VCC = 2.0V VCC = 1.2V; VI = VIH or VIL; –IO = 100µA HIGH level output voltage out uts voltage; all outputs MAX VCC = 1.2V VCC = 4.5 to 5.5 VOH -40°C to +125°C 5 µA µA µA Philips Semiconductors Product specification 74LV374 Octal D-type flip-flop; positive edge-trigger (3-State) AC CHARACTERISTICS GND = 0V; tr = tf = 2.5ns; CL = 50pF; RL = 500Ω SYMBOL tPHL/tPLH tPZH/tPZL tPHZ/tPLZ tW tsu th fmax PARAMETER Propagation delay CP to Qn Propagation delay OE to Qn Propagation delay OE to Qn Clock pulse width HIGH or LOW Set-up time Dn to CP Hold time Dn to CP Maximum clock ulse frequency pulse WAVEFORM VCC(V) MIN TYP 1.2 – 2.0 – LIMITS –40 to +125 °C MAX MIN 90 – – – 31 39 – 49 2.7 – 23 29 – 36 – 172 23 – 29 4.5 to 5.5 – – 19 – 24 1.2 – 75 – – – 2.0 – 26 34 – 43 2.7 – 19 25 – 31 3.0 to 3.6 – 142 20 – 25 4.5 to 5.5 – – 17 – 21 1.2 – 80 – – – 2.0 – 29 39 – 48 Figure 2 2.7 – 22 29 – 36 3.0 to 3.6 – 172 24 – 29 4.5 to 5.5 – – 20 – 24 2.0 34 12 – 41 – 2.7 25 9 – 30 – 3.0 to 3.6 20 72 – 24 – 1.2 – 25 – – – 2.0 22 9 – 26 – 2.7 16 6 – 19 – 3.0 to 3.6 13 52 – 15 – 1.2 – –10 – – – 2.0 5 –3 – 5 – 2.7 5 –2 – 5 – 3.0 to 3.6 5 –22 – 5 – 2.0 15 40 – 12 – 2.7 19 58 – 16 – 3.0 to 3.6 24 702 – 20 – Figure 2 Figure 1 Figure 3 Figure 3 Figure 2 6 UNIT MAX 3.0 to 3.6 Figure 1 NOTE: 1. Unless otherwise stated, all typical values are at Tamb = 25°C. 2. Typical value measured at VCC = 3.3V. 3. Typical value measured at VCC = 5.0V. 1997 Mar 20 LIMITS –40 to +85 °C CONDITION ns ns ns ns ns ns MHz Philips Semiconductors Product specification 74LV374 Octal D-type flip-flop; positive edge-trigger (3-State) AC WAVEFORMS VM = 1.5V at VCC 2.7V 3.6V VM = 0.5V * VCC at VCC 2.7V and 4.5V VOL and VOH are the typical output voltage drop that occur with the output load. VI CP INPUT GND 1/fmax VM(1) t su t su ÌÌÌÌ ÌÌÌÌÌÌÌÌ ÌÌÌÌ ÌÌÌÌÌÌÌÌ ÌÌÌÌ ÌÌÌÌÌÌÌÌ th th VI CP INPUT VM Dn INPUT tW GND tPHL tPLH VOH 90% Qn Qn OUTPUT VM OUTPUT VM VM VOL 10% tTHL NOTE: the shaded areas indicate when the input is permitted to change for predictable output performance. tTLH SV00345 Figure 3. SV00343 NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. Figure 1. Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, output transition times and the maximum clock pulse frequency VI OE INPUT VM GND tPLZ tPZL VCC OUTPUT LOW-to-OFF OFF-to-LOW VM VX VOL tPZH tPHZ VOH OUTPUT HIGH-to-OFF OFF-to-HIGH VY VM GND outputs enabled outputs disabled outputs enabled SV00344 Figure 2. Waveforms showing the 3-state enable and disable times 1997 Mar 20 Waveforms showing the data set-up and hold times for the Dn input to the CP input 7 Philips Semiconductors Product specification 74LV374 Octal D-type flip-flop; positive edge-trigger (3-State) TEST CIRCUIT tW 90% S1 Vcc VS1 Open GND NEGATIVE PULSE 90% VM VI VM 10% 10% 0V Vl RL = 1k VO PULSE GENERATOR D.U.T. RL = 1k RT CL= 50pF tTHL (tf) tTLH (tr) tTLH (tr) tTHL (tf) 90% POSITIVE PULSE VI 90% VM VM 10% tW Test Circuit for Outputs 10% 0V VM = 1.5V Input Pulse Definition DEFINITIONS SWITCH POSITION TEST S1 tPLH/tPHL Open < 2.7V VCC 2 VCC tPLZ/tPZL VS1 2.7–3.6V 2.7V 2 VCC tPHZ/tPZH GND ≥ 4.5 V VCC 2 VCC VCC VI RL = Load resistor CL = Load capacitance includes jig and probe capacitance RT = Termination resistance should be equal to ZOUT of pulse generators. VS1 SY00044 Figure 4. 1997 Mar 20 Load circuitry for switching times 8 Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger (3-State) DIP20: plastic dual in-line package; 20 leads (300 mil) 1997 Mar 20 9 74LV374 SOT146-1 Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger (3-State) SO20: plastic small outline package; 20 leads; body width 7.5 mm 1997 Mar 20 10 74LV374 SOT163-1 Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger (3-State) SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm 1997 Mar 20 11 74LV374 SOT339-1 Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger (3-State) 74LV374 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Copyright Philips Electronics North America Corporation 1997 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: yyyy mmm dd 12 Date of release: 05-96 9397-750-04448