INTEGRATED CIRCUITS DATA SHEET 74ALVCH16623 16-bit transceiver with dual enable; 3-state Product specification Supersedes data of 1998 Aug 31 File under Integrated Circuits, IC24 1999 Sep 20 Philips Semiconductors Product specification 16-bit transceiver with dual enable; 3-state 74ALVCH16623 FEATURES DESCRIPTION • Complies with JEDEC standard no. 8-1A The 74ALVCH16623 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. • CMOS low power consumption • Direct interface with TTL levels • MULTIBYTE flow-through standard pin-out architecture • All data inputs have bus hold circuitry • Output drive capability 50 Ω transmission lines at 85 °C • Current drive ±24 mA at 3.0 V. The 74ALVCH16623 is a 16-bit transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. This 16-bit bus transceiver is designed for asynchronous two-way communication between data buses. The control function implementation allows maximum flexibility in timing. This device allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending upon the logic levels at the enable inputs (nOEAB, nOEBA). The enable inputs can be used to disable the device so that the buses are effectively isolated. The dual enable function configuration gives this transceiver the capability to store data by simultaneous enabling of nOEAB and nOEBA. Each output reinforces its input in this transceiver configuration. Thus, when all control inputs are enabled and all other data sources to the four sets of the bus lines are at high-impedance OFF-state, all sets of bus lines will remain at their last states. The 8-bit codes appearing on the two double sets of buses will be complementary. This device can be used as two 8-bit transceivers or one 16-bit transceiver. To ensure the high-impedance state during power-on or power-down, OEBA should be tied to VCC through a pull-up resistor and OEAB should be tied to GND through a pull-down resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level. QUICK REFERENCE DATA Ground = 0; Tamb = 25 °C; tr = tf = 2.5 ns. SYMBOL PARAMETER CONDITIONS tPHL/tPLH propagation delay nAn, nBn to nBn, nAn CI/O input/output capacitance CI input capacitance CPD power dissipation capacitance per buffer notes 1 and 2 UNIT CL = 30 pF; VCC = 2.5 V 2.0 ns CL = 50 pF; VCC = 3.3 V 1.9 ns 10.0 pF 3.0 pF outputs enabled 35 pF outputs disabled 5 pF Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + Σ (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in Volts; Σ (CL × VCC2 × fo) = sum of outputs. 2. The condition is VI = GND to VCC. 1999 Sep 20 TYPICAL 2 Philips Semiconductors Product specification 16-bit transceiver with dual enable; 3-state 74ALVCH16623 ORDERING INFORMATION PACKAGE TYPE NUMBER TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE −40 to +85 °C 48 TSSOP plastic SOT362-1 74ALVCH16623DGG FUNCTION TABLE See note 1. INPUTS nOEAB INPUTS/OUTPUTS nOEBA nAn nBn L L A=B inputs H H inputs B=A L H Z Z H L A=B B=A Note 1. H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state. PINNING PIN SYMBOL DESCRIPTION 1, 24 1OEAB, 2OEAB output enable input (active HIGH) 2, 3, 5, 6, 8, 9, 11, 12 1B0 to 1B7 data inputs/outputs 4, 10, 15, 21, 28, 34, 39, 45 GND ground (0 V) 7, 18, 31, 42 VCC DC supply voltage 13, 14, 16, 17, 19, 20, 22, 23 2B0 to 2B7 data inputs/outputs 25, 48 2OEBA, 1OEBA output enable input (active LOW) 26, 27, 29, 30, 32, 33, 35, 36 2A7 to 2A0 data inputs/outputs 37, 38, 40, 41, 43, 44, 46, 47 1A7 to 1A0 data inputs/outputs 1999 Sep 20 3 Philips Semiconductors Product specification 16-bit transceiver with dual enable; 3-state fpage 1OEAB 1 48 1OEBA 1B0 2 47 1A0 1B1 3 46 1A1 GND 4 45 GND 1B2 5 44 1A2 1B3 6 43 1A3 VCC 7 42 VCC 1B4 8 41 1A4 1B5 40 1A5 9 1 47 1OEBA 25 1OEAB 24 1A0 36 1B0 46 38 1A6 1B6 11 16623 43 35 2A1 2B1 14 34 GND GND 15 41 32 2A3 2B3 17 40 30 2A4 2B4 19 2B5 20 29 2A5 GND 21 28 GND 38 2B6 26 1B7 12 MNA307 Fig.1 Pin configuration. 1999 Sep 20 2B7 23 MNA308 25 2OEBA 2OEAB 24 22 2A7 26 2A7 2B7 23 20 2A6 11 1A7 27 2A6 2B6 22 2B5 27 19 2A5 9 1A6 1B6 37 2B4 29 1B5 17 2A4 8 1A5 31 VCC VCC 18 2B3 30 1B4 16 2A3 6 1A4 33 2A2 2B2 16 2B2 32 1B3 14 2A2 5 1A3 13 2A1 2B1 33 1B2 2A0 3 1A2 37 1A7 36 2A0 2B0 13 44 2OEAB 2B0 35 1B1 2OEBA 2 1A1 39 GND GND 10 1B7 12 48 74ALVCH16623 Fig.2 Logic symbol. 4 Philips Semiconductors Product specification 16-bit transceiver with dual enable; 3-state 48 halfpage handbook, 25 1EN1 1 24 1EN2 1 2EN1 2EN2 1 2 36 46 3 35 14 44 5 33 16 43 6 32 17 41 8 30 19 40 9 29 20 38 11 27 22 37 12 26 47 74ALVCH16623 2 2 13 handbook, halfpage VCC data input to internal circuit MNA310 23 MNA309 Fig.3 IEC logic symbol. 1999 Sep 20 Fig.4 Bus hold circuit. 5 Philips Semiconductors Product specification 16-bit transceiver with dual enable; 3-state 74ALVCH16623 RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER CONDITIONS MIN. TYP. MAX. UNIT DC supply voltage for max. speed performance CL = 30 pF 2.3 2.5 2.7 V for max. speed performance CL = 50 pF 3.0 3.3 3.6 V 1.2 2.4 3.6 V VI DC input voltage for low-voltage applications 0 − VCC V VO DC output voltage 0 − VCC V Tamb operating ambient temperature in free air −40 − +85 °C tr, ft input rise and fall times VCC = 2.3 to 3.0 V 0 − 20 ns/V VCC = 3.0 to 3.6 V 0 − 10 ns/V LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCC DC supply voltage −0.5 +4.6 V IIK DC input diode current VI < 0 − −50 mA VI DC input voltage note 1 −0.5 +4.6 V IOK DC output diode current VO > VCC or VO < 0 − ±50 mA VO DC output voltage note 1 −0.5 VCC + 0.5 V IO DC output source or sink current VO = 0 to VCC − ±50 mA ICC, IGND DC VCC or GND current − ±100 mA Tstg storage temperature −65 +150 °C Ptot power dissipation 600 mW for temperature range: −40 to +125 °C; − note 2 Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. Above 55 °C the value of Ptot derates linearly with 8 mW/K. 1999 Sep 20 6 Philips Semiconductors Product specification 16-bit transceiver with dual enable; 3-state 74ALVCH16623 DC CHARACTERISTICS Over recommended operating conditions. Voltage are referenced to GND (ground = 0 V). Tamb = −40 TO +85 °C TEST CONDITIONS SYMBOL PARAMETER VI (V) VIH HIGH-level input voltage VIL LOW-level input voltage VOH VOL HIGH-level output voltage LOW-level output voltage OTHER VIH or VIL VIH or VIL TYP.(1) MIN. − 2.7 to 3.6 2.0 1.5 − 2.3 to 2.7 − 1.2 0.7 2.7 to 3.6 − 1.5 0.8 IO = −100 µA 2.3 to 3.6 VCC − 0.2 VCC IO = −6 mA 2.3 VCC − 0.3 VCC − 0.08 − IO = −12 mA 2.3 VCC − 0.6 VCC − 0.26 − IO = −12 mA 2.7 VCC − 0.5 VCC − 0.14 − IO = −12 mA 3.0 VCC − 0.6 VCC − 0.09 − IO = −24 mA 3.0 VCC − 1.0 VCC − 0.28 − − IO = 100 µA 2.3 to 3.6 − GND 0.20 IO = 6 mA 2.3 − 0.07 0.40 IO = 12 mA 2.3 − 0.15 0.70 IO = 12 mA 2.7 − 0.14 0.40 3.0 − IO = 24 mA UNIT MAX. 1.2 2.3 to 2.7 1.7 V V V V 0.27 0.55 2.3 to 3.6 − 0.1 5 µA VO = VCC or GND 2.3 to 3.6 − 0.1 10 µA IO = 0 2.3 to 3.6 − 0.2 40 µA IO = 0 2.3 to 3.6 − 150 750 µA 0.7(2) 2.3(2) 45 − − µA 0.8(2) 3.0(2) 75 150 − 1.7(2) 2.3(2) −45 2.0(2) 3.0(2) Il input leakage current VCC or GND IOZ 3-state output OFF-state current VIH or VIL ICC quiescent supply voltage VCC or GND ∆ICC additional quiescent supply VCC − 0.6 current given per data I/O pin with bus hold IBHL bus hold LOW sustaining current bus hold HIGH sustaining current IBHH VCC (V) − µA −75 −175 − IBHLO bus hold LOW overdrive current 3.6(2) 500 − − µA IBHHO bus hold LOW overdrive current 3.6(2) −500 − − µA Notes 1. All typical values are measured at Tamb = 25 °C. 2. Valid for data inputs of bus hold parts. 1999 Sep 20 7 Philips Semiconductors Product specification 16-bit transceiver with dual enable; 3-state 74ALVCH16623 AC CHARACTERISTICS FOR VCC = 2.3 TO 2.7 V Ground = 0 V; tr = tf ≤ 2.0 ns; CL = 30 pF. Tamb = −40 TO +85 °C TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS VCC (V) MIN. TYP.(1) UNIT MAX. tPHL/tPLH propagation delay nAn, nBn to nBn, nAn see Figs 5 and 8 2.3 to 2.7 1.0 2.4 3.5 ns tPZH/tPZL 3-state output enable time nOEAB to nBn see Figs 7 and 8 2.3 to 2.7 1.0 3.0 5.0 ns tPHZ/tPLZ 3-state output disable time nOEBA to nAn see Figs 6 and 8 2.3 to 2.7 1.0 3.0 5.1 ns tPZH/tPZL 3-state output enable time nOEAB to nBn see Figs 7 and 8 2.3 to 2.7 1.0 2.8 4.5 ns tPHZ/tPLZ 3-state output disable time nOEBA to nAn see Figs 6 and 8 2.3 to 2.7 1.0 2.4 4.0 ns Note 1. All typical values are measured at Tamb = 25 °C and VCC = 2.5 V. AC CHARACTERISTICS FOR VCC = 2.7 V AND VCC = 3.0 TO 3.6 V Ground = 0 V; tr = tf ≤ 2.5 ns; CL = 50 pF. Tamb = −40 TO +85 °C TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS tPHL/tPLH tPZH/tPZL tPHZ/tPLZ tPZH/tPZL tPHZ/tPLZ propagation delay nAn, nBn to nBn, nAn see Figs 5 and 8 3-state output enable time nOEAB to nBn see Figs 7 and 8 3-state output disable time nOEBA to nAn see Figs 6 and 8 3-state output enable time nOEAB to nBn see Figs 7 and 8 3-state output disable time nOEBA to nAn see Figs 6 and 8 1. All typical values are measured at Tamb = 25 °C. 2. Typical values at VCC = 3.3 V. 8 MIN. TYP.(1) UNIT MAX. − 2.5 3.0 to 3.6 1.0 2.6(2) 3.1 2.7 − 2.8 4.5 3.0 to 3.6 1.0 2.6(2) 4.0 2.7 3.4 2.7 − 3.3 5.0 3.0 to 3.6 1.0 2.8(2) 4.2 2.7 − 3.8 5.4 3.0 to 3.6 1.0 3.3(2) 4.6 2.7 − 3.2 4.5 1.0 3.0(2) 4.3 3.0 to 3.6 Notes 1999 Sep 20 VCC (V) ns ns ns ns ns Philips Semiconductors Product specification 16-bit transceiver with dual enable; 3-state AC WAVEFORMS 74ALVCH16623 Notes: VCC = 2.3 to 2.7 V VM = 0.5VCC; VX = VOL + 150 mV; VY = VOH − 150 mV; VI = VCC; VOL and VOH are typical output voltage drop that occur with the output load. handbook, halfpage VI nAn, nBn VM input Notes: VCC = 3.0 to 3.6 V and VCC = 2.7 V GND VM = 1.5 V; tPHL tPLH VX = VOL + 300 mV; VOH nBn, nAn output VY = VOH − 300 mV; VM VI = 2.7 V; VOL Fig.5 MNA311 VOL and VOH are typical output voltage drop that occur with the output load. The input nAn, nBn to output nBn, nAn propagation delay times. VI handbook, full pagewidth nOEBA input VM GND tPLZ VCC output LOW-to-OFF OFF-to-LOW VOL tPZL VM VX tPHZ tPZH VOH VY output HIGH-to-OFF OFF-to-HIGH GND VM outputs enabled outputs disabled outputs enabled MNA312 Fig.6 3-state enable and disable times for nOEBA input. 1999 Sep 20 9 Philips Semiconductors Product specification 16-bit transceiver with dual enable; 3-state 74ALVCH16623 VI handbook, full pagewidth nOEAB input VM GND tPLZ tPZL VCC output LOW-to-OFF OFF-to-LOW VM VX VOL tPHZ VOH tPZH VY output HIGH-to-OFF OFF-to-HIGH GND VM outputs enabled outputs enabled outputs disabled MNA313 Fig.7 3-state enable and disable times for nOEAB times. S1 handbook, full pagewidth VCC PULSE GENERATOR VI RL 500 Ω VO 2 × VCC open GND D.U.T. CL 50 pF RT RL 500 Ω MNA296 TEST Definitions for test circuit. CL = load capacitance including jig and probe capacitance (See Chapter “AC characteristics”). RL = load resistance. RT = termination resistance should be equal to the output impedance Zo of the pulse generator. S1 VCC VI tPLH/tPHL open tPLZ/tPZL 2 × VCC <2.7 V tPHZ/tPZH GND 2.7 to 3.6 V 2.7 V VCC Fig.8 Load circuitry for switching times. 1999 Sep 20 10 Philips Semiconductors Product specification 16-bit transceiver with dual enable; 3-state 74ALVCH16623 PACKAGE OUTLINE TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 E D A X c HE y v M A Z 48 25 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 detail X 24 w M bp e 2.5 0 5 mm scale DIMENSIONS (mm are the original dimensions). UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z θ mm 1.2 0.15 0.05 1.05 0.85 0.25 0.28 0.17 0.2 0.1 12.6 12.4 6.2 6.0 0.5 8.3 7.9 1 0.8 0.4 0.50 0.35 0.25 0.08 0.1 0.8 0.4 8 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT362-1 1999 Sep 20 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 93-02-03 95-02-10 MO-153ED 11 o Philips Semiconductors Product specification 16-bit transceiver with dual enable; 3-state SOLDERING 74ALVCH16623 If wave soldering is used the following conditions must be observed for optimal results: Introduction to soldering surface mount packages • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. Reflow soldering The footprint must incorporate solder thieves at the downstream end. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Wave soldering Manual soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. To overcome these problems the double-wave soldering method was specifically developed. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 1999 Sep 20 12 Philips Semiconductors Product specification 16-bit transceiver with dual enable; 3-state 74ALVCH16623 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE REFLOW(1) WAVE BGA, SQFP not suitable HLQFP, HSQFP, HSOP, HTSSOP, SMS not PLCC(3), SO, SOJ suitable suitable(2) suitable suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1999 Sep 20 13 Philips Semiconductors Product specification 16-bit transceiver with dual enable; 3-state NOTES 1999 Sep 20 14 74ALVCH16623 Philips Semiconductors Product specification 16-bit transceiver with dual enable; 3-state NOTES 1999 Sep 20 15 74ALVCH16623 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 245004/02/pp16 Date of release: 1999 Sep 20 Document order number: 9397 750 05254