INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT10 Triple 3-input NAND gate Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification Triple 3-input NAND gate 74HC/HCT10 FEATURES • Output capability: standard • ICC category: SSI GENERAL DESCRIPTION The 74HC/HCT10 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT10 provide the 3-input NAND function. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC tPHL/ tPLH propagation delay nA, nB, nC to nY CI input capacitance CPD power dissipation capacitance per gate CL = 15 pF; VCC = 5 V notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fO) where: fi = input frequency in MHz fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in V ∑ (CL × VCC2 × fo) = sum of outputs 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V. ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. December 1990 2 HCT 9 11 ns 3.5 3.5 pF 12 14 pF Philips Semiconductors Product specification Triple 3-input NAND gate 74HC/HCT10 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1, 3, 9 1A to 3A data inputs 2, 4, 10 1B to 3B data inputs 13, 5, 11 1C to 3C data inputs 12, 6, 8 1Y to 3Y data outputs 7 GND ground (0 V) 14 VCC positive supply voltage Fig.1 Pin configuration. Fig.3 IEC logic symbol. Fig.2 Logic symbol. FUNCTION TABLE INPUTS OUTPUT nA nB nC L L L H L L H H L H L H L H H H H L L H H L H H H H L H H H H L Notes Fig.4 Functional diagram. December 1990 Fig.5 Logic diagram (one gate). 3 1. H = HIGH voltage level L = LOW voltage level nY Philips Semiconductors Product specification Triple 3-input NAND gate 74HC/HCT10 DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: SSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER −40 to + 85 +25 min. tPHL/ tPLH tTHL/ tTLH propagation delay nA, nB, nC to nY output transition time December 1990 min. UNIT VCC (V) typ. max. min. 30 95 120 145 11 19 24 29 9 16 20 25 6.0 19 75 95 110 2.0 7 15 19 22 6 13 16 19 4 max. −40 to + 125 WAVEFORMS max. 2.0 ns ns 4.5 4.5 6.0 Fig.6 Fig.6 Philips Semiconductors Product specification Triple 3-input NAND gate 74HC/HCT10 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: SSI Note to HCT types The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD COEFFICIENT nA, nB, nC 1.5 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HCT SYMBOL PARAMETER −40 to + 85 + 25 min. tPHL/ tPLH tTHL/ tTLH typ. max. min. max. −40 to +125 min. UNIT VCC (V) WAVEFORMS max. propagation delay nA, nB, nC to nY 14 24 30 36 ns 4.5 Fig.6 output transition time 7 15 19 22 ns 4.5 Fig.6 AC WAVEFORMS (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the input (nA, nB, nC) to output (nY) propagation delays and the output transition times. PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. December 1990 5