INTEGRATED CIRCUITS 74F269 8-bit bidirectional binary counter Product specification IC15 Data Handbook 1996 Jan 05 Philips Semiconductors Product specification 8–bit bidirectional binary counter 74F269 FEATURES PIN CONFIGURATION • Synchronous counting and loading • Built-in look-ahead carry capability • Count frequency 115MHz typ • Supply current 95mA typ DESCRIPTION The 74F269 is a fully synchronous 8-stage Up/Down Counter featuring a preset capability for programmable operation, carry look-ahead for easy cascading and a U/D input to control the direction of counting. All state changes, whether in counting or parallel loading, are initiated by the rising edge of the clock. TYPE TYPICAL fMAX TYPICAL SUPPLY CURRENT (TOTAL) 74F269 115MHz 95mA U/D 1 24 PE Q0 2 23 P0 Q1 3 22 P1 Q2 4 21 P2 Q3 5 20 P3 Q4 6 19 VCC GND 7 18 P4 Q5 8 17 P5 Q6 9 16 P6 Q7 10 15 P7 CP 11 14 TC CEP 12 13 CET SF00834 ORDERING INFORMATION DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C PKG DWG # 24-Pin Plastic Slim DIP (300mil) N74F269N SOT222-1 24-Pin Plastic SOL N74F269D SOT137-1 24-Pin Plastic SSOP type II N74F269DB SOT340-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74F(U.L.) HIGH/LOW LOAD VALUE HIGH/LOW P0 - P7 Parallel Data inputs 1.0/1.0 20µA/0.6mA PE Parallel Enable input (active Low) 1.0/1.0 20µA/0.6mA U/D Up/Down count control input 1.0/1.0 20µA/0.6mA CEP Count Enable Parallel input (active Low) 1.0/1.0 20µA/0.6mA CET Count Enable Trickle input (active Low) 1.0/1.0 20µA/0.6mA CP Clock input 1.0/1.0 20µA/0.6mA TC Terminal Count output (active Low) 50/33 1.0mA/20mA Q0 - Q7 Flip-flop outputs 50/33 1.0mA/20mA NOTE: One (1.0) FAST Unit Load is defined as: 20µA in the High state and 0.6mA in the Low state. 1996 Jan 05 2 853–0056 16186 Philips Semiconductors Product specification 8–bit bidirectional binary counter 74F269 LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) CTR DIV 256 24 1 M1[LOAD] M2[COUNT] M3[UP] M4[DOWN] 23 22 21 20 18 17 16 12 15 13 P0 24 PE 1 U/D 12 CEP 13 CET 11 P1 P2 P3 P4 P5 P6 P7 11 23 TC & G5 EN6 2, 3, 5, 6 +/C7 2, 4, 5, 6– Q1 Q2 Q3 Q4 Q5 Q6 3 4 5 6 8 9 8 [32] 16 10 6 [16] 17 2 5 [8] 18 Q7 4 [4] 20 Q0 3 [2] 21 CP 2 1, 7D [1] 22 14 9 [64] 15 10 [128] 14 3, 5, 6 CT=256 4, 5, 8 CT=0 VCC=Pin 19 GND=Pin 7 SF00835 SF00836 APPLICATION CP U/D PE P0 P1 P2 P3 P4 P5 P6 P7 PE U/D P0 P1 P2 P3 P4 P5 P6 P7 P0 P1 P2 P3 P4 P5 P6 P7 P0 P1 P2 P3 P4 P5 P6 P7 PE U/D PE U/D PE U/D CP CEP CP TC CEP CET Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 CP TC CEP CET Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 CP TC CEP CET Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 TC CET Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Least significant 8-bit counter Most significant 8-bit counter SF00851 Figure 1. Synchronous Multistage Counting Scheme MODE SELECT FUNCTION TABLE INPUTS H = h = L = l = q = X = ↑ = (a) = OUTPUTS CP U/D CEP CET PE ↑ X X X l ↑ X X X l ↑ h l l h ↑ l l l h ↑ X h l ↑ X X h Pn OPERATING MODE Qn TC l L (a) h H (a) X Count Up (a) Count Up X Count Down (a) Count Down h X qn (a) h X qn H Parallel load Hold (do nothing) High voltage level High voltage level one setup prior to the Low-to-High clock transition Low voltage level Low voltage level one setup time prior to the Low-to-High clock transition Lower case letters indicate the state of the referenced output prior to the Low-to-High clock transition Don’t care Low-to-High clock transition TC is Low when CET is Low and the counter is at Terminal Count. Terminal Count Up is with all Qn outputs High and Terminal Count Down is with all Qn outputs Low. 1996 Jan 05 3 Philips Semiconductors Product specification 8–bit bidirectional binary counter 74F269 LOGIC DIAGRAM 2 P0 23 P1 P2 P3 22 21 20 DETAIL A 3 DETAIL A P5 17 5 DETAIL A DETAIL A 8 DETAIL A 9 P6 16 DETAIL A P7 15 DETAIL A Q1 4 Q2 DETAIL A 6 P4 18 Q0 10 Q3 Q4 Q5 Q6 Q7 PE 24 CP 11 1 U/D CEP 12 CET 13 14 TOGGLE TC DETAIL A Pn D CP PE Q Q CP VCC=Pin 19 GND=Pin 7 1996 Jan 05 SF00837 4 Philips Semiconductors Product specification 8–bit bidirectional binary counter 74F269 ABSOLUTE MAXIMUM RATINGS (Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL PARAMETER RATING UNIT VCC Supply voltage –0.5 to +7.0 V VIN Input voltage –0.5 to +7.0 V IIN Input current –30 to +5 mA VOUT Voltage applied to output in High output state –0.5 to VCC V IOUT Current applied to output in Low output state Tamb Operating free-air temperature range Tstg Storage temperature 40 mA 0 to +70 °C –65 to +150 °C RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL PARAMETER UNIT MIN NOM MAX 5.0 5.5 VCC Supply voltage 4.5 V VIH High-level input voltage 2.0 VIL Low-level input voltage 0.8 V IIK Input clamp current –18 mA IOH High-level output current –1 mA IOL Low-level output current 20 mA Tamb Operating free-air temperature range 70 °C V 0 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) LIMITS SYMBOL TEST CONDITIONSNO TAG PARAMETER MIN TYP NO TAG MAX UNIT VCC = MIN, VIL = MAX ±10%VCC 2.5 VIH = MIN, IOH = MAX ±5%VCC 2.7 VCC = MIN, VIL = MAX ±10%VCC 0.30 0.50 VIH = MIN, IOL = MAX ±5%VCC 0.30 0.50 –0.73 –1.2 V VCC = MAX, VI = 7.0V 100 µA High-level input current VCC = MAX, VI = 2.7V 20 µA IIL Low-level input current VCC = MAX, VI = 0.5V IOS Short-circuit output currentNO TAG VCC = MAX VOH O High level output voltage High-level VOL O Low level output voltage Low-level VIK Input clamp voltage VCC = MIN, II = IIK II Input current at maximum input voltage IIH ICCH ICC Supply current (total) ICCL VCC = MAX V 3.4 V –60 –0.6 mA –150 mA PE=CET=CEP=U/D=GND, Pn=4.5V, CP=↑ 93 120 mA PE=CET=CEP=U/D=GND, Pn=GND, CP=↑ 98 125 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 1996 Jan 05 5 Philips Semiconductors Product specification 8–bit bidirectional binary counter 74F269 AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER Tamb = +25°C VCC = +5V CL = 50pF, RL = 500Ω TEST CONDITIONS MIN TYP Tamb = 0°C to +70°C VCC = +5V ± 10% CL = 50pF, RL = 500Ω MAX MIN UNIT MAX fMAX Maximum clock frequency Waveform 1 100 115 tPLH tpPHL Propagation delay CP to Qn (Load, PE = Low) Waveform 1 3.0 4.0 6.0 6.5 8.5 8.5 3.0 4.0 85 9.0 9.0 MHz ns ns tPLH tPHL Propagation delay CP to Qn (Count, PE = High) Waveform 1 3.0 4.5 6.0 7.0 9.0 10.0 3.0 4.0 10.0 10.5 ns ns tPLH tPHL Propagation delay CP to TC Waveform 1 4.5 5.0 6.5 6.5 9.5 9.5 4.0 5.0 10.5 10.0 ns ns tPLH tPHL Propagation delay CET to TC Waveform 2 3.5 3.0 6.0 6.5 9.0 9.0 3.0 3.0 10.0 10.0 ns ns tPLH tPHL Propagation delay U/D to TC Waveform 3 4.5 4.5 7.0 7.0 9.0 9.5 4.0 4.0 10.0 10.0 ns ns AC SETUP REQUIREMENTS LIMITS SYMBOL PARAMETER Tamb = +25°C VCC = +5V CL = 50pF, RL = 500Ω TEST CONDITIONS MIN ts(H) ts(L) Setup time, High or Low Pn to CP th(H) th(L) TYP Tamb = 0°C to +70°C VCC = +5V ± 10% CL = 50pF, RL = 500Ω MIN UNIT MAX Waveform 4 3.5 3.5 2.5 2.5 ns ns Hold time, High or Low Pn to CP Waveform 4 1.0 1.0 0 1.0 ns ns ts(H) ts(L) Setup time, High or Low PE to CP Waveform 4 5.5 6.5 5.5 6.5 ns ns th(H) th(L) Hold time, High or Low PE to CP Waveform 4 0 0 0 0 ns ns ts(H) ts(L) Setup time, High or Low CEP or CET to CP Waveform 5 6.0 8.0 5.0 6.5 ns ns th(H) th(L) Hold time, High or Low CEP or CET to CP Waveform 5 0 0 0 0 ns ns ts(H) ts(L) Setup time, High or Low U/D to CP Waveform 6 8.0 6.5 6.5 6.5 ns ns th(H) th(L) Hold time, High or Low U/D to CP Waveform 6 0 0 0 0 ns ns tw(H) tw(L) CP Pulse width High or Low Waveform 1 4.0 4.5 4.0 5.0 ns ns 1996 Jan 05 6 Philips Semiconductors Product specification 8–bit bidirectional binary counter 74F269 TIMING DIAGRAM PE P0 P1 P2 P3 P4 P5 P6 P7 CP U/D CEP AND CET Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 TC 253 SEQUENCE LOAD 254 255 0 COUNT UP 1 2 INHIBIT 2 1 0 255 254 253 COUNT DOWN SF00838B 1996 Jan 05 7 Philips Semiconductors Product specification 8–bit bidirectional binary counter 74F269 AC WAVEFORMS For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance. 1/fMAX CET CP VM VM tW(H) VM tPHL tW(L) tPLH tPHL tPLH TC VM Qn VM VM VM VM SF00792 tPLH tPHL TC VM VM Waveform 2. Propagation Delay, CET Input to Terminal Count Output VM SF00791A Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency Pn VM U/D VM VM tPHL ts tPLH TC VM VM PE VM th VM VM ts(L) VM th = 0 VM ts(H) th = 0 SF00793 Waveform 3. Propagation Delay, Up/Down Count Control Input to Terminal Count Output VM CP VM SF00844 Waveform 4. Parallel Data and Parallel Enable Setup and Hold Times CET VM VM VM U/D VM VM VM VM VM CEP ts(L) th(L) ts(H) VM CP Qn COUNT ts(L) th(H) NO CHANGE Qn COUNT DOWN th VM COUNT UP SF00839 SF00842 Waveform 5. Count Enables Setup and Hold Times 1996 Jan 05 ts(H) VM CP VM th Waveform 6. Up/Down Count Control Setup and Hold Times 8 Philips Semiconductors Product specification 8–bit bidirectional binary counter 74F269 TEST CIRCUIT AND WAVEFORMS VCC VIN tw 90% NEGATIVE PULSE VM D.U.T. RT CL RL AMP (V) VM 10% VOUT PULSE GENERATOR 90% 10% tTHL (tf ) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0V AMP (V) 90% 90% POSITIVE PULSE Test Circuit for Totem-Pole Outputs DEFINITIONS: RL = Load resistor; see AC ELECTRICAL CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC ELECTRICAL CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. VM VM 10% 10% tw 0V Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate tw tTLH tTHL 1MHz 500ns 2.5ns 2.5ns SF00006 1996 Jan 05 9 Philips Semiconductors Product specification 8–bit bidirectional binary counter 74F269 DIP24: plastic dual in-line package; 24 leads (300 mil) 1996 Jan 05 10 SOT222-1 Philips Semiconductors Product specification 8–bit bidirectional binary counter 74F269 SO24: plastic small outline package; 24 leads; body width 7.5 mm 1996 Jan 05 11 SOT137-1 Philips Semiconductors Product specification 8–bit bidirectional binary counter 74F269 SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm 1996 Jan 05 12 SOT340-1 Philips Semiconductors Product specification 8–bit bidirectional binary counter 74F269 NOTES 1996 Jan 05 13 Philips Semiconductors Product specification 8-bit bidirectional binary counter 74F269 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Philips Semiconductors and Philips Electronics North America Corporation register eligible circuits under the Semiconductor Chip Protection Act. Copyright Philips Electronics North America Corporation 1996 All rights reserved. Printed in U.S.A. (print code) Document order number: Date of release: July 1994 9397-750-05112