INTEGRATED CIRCUITS 74F191 Up/down binary counter with reset and ripple clock Product specification IC15 Data Handbook 1995 Jul 17 Philips Semiconductors Product specification Up/Down binary counter with reset and ripple clock FEATURES 74F191 PIN CONFIGURATION • High speed –125MHz typical fMAX • Synchronous, reversible counting • 4-Bit binary • Asynchronous parallel load capability • Cascadable without external logic • Single up/down control input D1 1 DESCRIPTION 16 VCC Q1 2 15 D0 Q0 3 14 CP CE 4 13 RC U/D 5 12 TC Q2 6 11 PL Q3 7 10 D2 GND 8 9 The 74F191 is a 4-bit binary counter. It contains four edge-triggered master/slave flip-flops with internal gating and steering logic to provide asynchronous preset and synchronous count-up and count-down operations. D3 SF00729 Asynchronous parallel load capability permits the counter to be preset to any desired number. Information present on the parallel data inputs (D0 - D3) is loaded into the counter and appears on the outputs when the Parallel Load (PL) input is Low. This operation overrides the counting function. Counting is inhibited by a High level on the count enable (CE) input. When CE is Low, internal state changes are initiated. Overflow/underflow indications are provided by two types of outputs, the Terminal Count (TC) and Ripple Clock (RC). TYPE TYPICAL fMAX TYPICAL SUPPLY CURRENT (TOTAL) 74F191 125MHz 40mA ORDERING INFORMATION The TC output is normally Low and goes High when: 1) the count reaches zero in the countdown mode or 2) reaches “15” in the count up mode. The TC output will remain High until a state change occurs, either by counting or presetting, or until U/D is changed. TC output should not be used as a clock signal because it is subject to decoding spikes. The TC signal is used internally to enable the RC output. When TC is High and CE is Low, the RC follows the clock pulse. The RC output essentially duplicates the Low clock pulse width, although delayed in time by two gate delays. DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C PKG DWG # 16-pin plastic DIP N74F191N SOT38-4 16-pin plastic SO N74F191D SOT109-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74F(U.L.) HIGH/LOW LOAD VALUE HIGH/LOW D0 - D3 Data inputs 1.0/1.0 20µA/0.6mA CE Count enable input (active Low) 1.0/3.0 20µA/1.8mA CP Clock pulse input (active rising edge) 1.0/1.0 20µA/0.6mA PL Asynchronous parallel load control input (active Low) 1.0/1.0 20µA/0.6mA U/D Up/down count control input 1.0/1.0 20µA/0.6mA Q 0 - Q3 Flip-flop outputs 50/33 1.0mA/20mA RC Ripple clock output (active low) 50/33 1.0mA/20mA TC Terminal count output 50/33 1.0mA/20mA NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20µA in the High state and 0.6mA in the Low state. 1995 Jul 17 2 853–0352 15459 Philips Semiconductors Product specification Up/Down binary counter with reset and ripple clock LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) 15 D0 4 1 D1 10 9 D2 U/D 14 CP 11 PL 4 EN1 5 M2[DOWN] D3 14 RC 13 TC 12 G4 5D 1 3 VCC=Pin 16 GND=Pin 8 2 Q2 Q3 6 13 6, 4, 1 C5 [LOAD] 15 Q1 12 2(CT=0)Z6 3(CT=15)Z6 1,2–/1,3+ 11 Q0 CTR DIV 10 M3[UP] CE 5 74F191 3 +– 2 [2] 10 6 [4] 9 7 [1] 7 [8] SF00730 SF00731 LOGIC DIAGRAM D0 PL U/D D1 15 11 D2 1 D3 10 9 5 4 CE 14 CP J CP SD RD Q 13 VCC = Pin 16 GND = Pin 8 1995 Jul 17 12 RC TC K Q J K RD Q 3 Q0 CP SD Q J CP SD RD Q 2 K Q J Q2 K RD Q 6 Q1 CP SD Q 7 Q3 SF00732 3 Philips Semiconductors Product specification Up/Down binary counter with reset and ripple clock 74F191 MODE SELECT — FUNCTION TABLE INPUTS OUTPUTS OPERATING MODE PL U/D CE CP Dn Qn L L X X X X X X L H L H H L l ↑ X Count up H H l ↑ X Count down Count down H X H X X No change Hold (do nothing) Parallel load Count up TC AND RC FUNCTION TABLE INPUTS TERMINAL COUNT STATE OUTPUTS U/D CE CP Q0 Q1 Q2 Q3 TC RC H H X H H H H L H L H X H H H H H H L L H H H H H L H X L L L L L H H H X L L L L H H H L L L L L H H = High voltage level steady state L = Low voltage level steady state X = Don’t care = Low pulse ↑ = Low-to-High clock transition l = Low voltage level one set-up time prior to the Low-to-High clock transition 1995 Jul 17 4 Philips Semiconductors Product specification Up/Down binary counter with reset and ripple clock 74F191 APPLICATIONS DIRECTION CONTROL U/D ENABLE CLOCK RC U/D CE CP RC U/D CE CP RC CE CP a. N-Stage Counter Using Ripple Clock DIRECTION CONTROL U/D U/D RC CE CP ENABLE U/D RC CE CP RC CE CP CLOCK b. Synchronous N-Stage Counter with Common Clock Using Ripple/Clock DIRECTION CONTROL ENABLE U/D CE CP U/D U/D CE CP * TC * TC CE CP TC CLOCK * = Carry Gate c. Synchronous N-Stage Counter with Common Clock and Terminal Count SF00733 Figure 1. ripple fashion and all clock inputs are driven in parallel. The Low state duration of the clock in this configuration must be long enough to allow the negative-going edge of the RC signal to ripple through to the last stage before the clock goes High. Since the RC output of any package goes High shortly after its clock input goes High, there is no such restriction on the High state duration of the clock. The 74F191 simplifies the design of multi-stage counters, as indicated in Figure 1, each RC output is used as the clock input for the next higher stage. When the clock source has a limited drive capability this configuration is particularly advantageous, since the clock source drives only the first stage. It is only necessary to inhibit the first stage to prevent counting in all stages, since a High signal on CE inhibits the RC output pulse as indicated in the Mode Select Table. The timing skew between state changes in the first and last stages is represented by the cumulative delay of the clock as it ripples through the preceding stages. This is a disadvantage of the configuration in some applications. In Figure 1c, the configuration shown avoids ripple delays and their associated restrictions. The combined TC signals from all the preceding stages forms the CE input signal for a given stage. An enable signal must also be included in each carry gate in order to inhibit counting. The TC output of a given stage is not affected by its own CE, therefore, the simple inhibit scheme of Figure 1a and 1b does not apply. Figure 1b shows a method of causing state changes to occur simultaneously in all stages. The RC output signals propagate in 1995 Jul 17 5 Philips Semiconductors Product specification Up/Down binary counter with reset and ripple clock 74F191 ABSOLUTE MAXIMUM RATINGS (Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL PARAMETER RATING UNIT V VCC Supply voltage –0.5 to +7.0 VIN Input voltage –0.5 to +7.0 V IIN Input current –30 to +5.0 mA VOUT Voltage applied to output in High output state –0.5 to +VCC V IOUT Current applied to output in Low output state 40 mA Tamb Operating free-air temperature range 0 to +70 oC Tstg Storage temperature –65 to +150 oC RECOMMENDED OPERATING CONDITIONS SYMBOL LIMITS PARAMETER Min Nom Max 5.0 5.5 UNIT VCC Supply voltage 4.5 V VIH High-level input voltage 2.0 VIL Low-level input voltage 0.8 V IIK Input clamp current –18 mA IOH High-level output current –1 mA IOL Low-level output current 20 mA Tamb Operating free-air temperature range 70 oC V 0 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL VOH O TEST CONDITIONS1 PARAMETER VCC = Min, VIL = Max, IOH = Max, VIH = Min High level output voltage High-level VCC = Min, VIL = Max, IOL = Max, VIH = Min VOL O Low level output voltage Low-level VIK Input clamp voltage VCC = Min, II = IIK II Input current at maximum input voltage VCC = Max, VI = 7.0V IIH High-level input current VCC = Max, VI = 2.7V IIL Low-level input current CE Others IOS Short-circuit output current3 LIMITS Min ±10%VCC 2.5 ±5%VCC 2.7 UNIT V 3.4 V 0.30 0.50 V ±5%VCC 0.30 0.50 V –0.73 –1.2 V 100 µA –60 current4 Max ±10%VCC VCC = Max Max, VI = 0 0.5V 5V VCC = Max Typ2 20 µA –1.8 mA –0.6 mA –150 mA ICC Supply (total) VCC = Max 40 55 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 4. Measure ICC all inputs grounded and all outputs open. 1995 Jul 17 6 Philips Semiconductors Product specification Up/Down binary counter with reset and ripple clock 74F191 AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER Tamb= +25°C VCC = +5.0V CL = 50pF, RL = 500Ω TEST CONDITIONS Min Typ Max Tamb= 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω Min UNIT Max fMAX Maximum clock frequency to Qn outputs Waveform 1 100 125 90 MHz fMAX Maximum clock frequency to RC outputs Waveform 1 85 95 75 MHz tPLH tPHL Propagation delay CP to Qn Waveform 1 2.5 5.0 4.5 7.5 8.0 11.5 2.0 5.0 8.5 12.0 ns ns tPLH tPHL Propagation delay CP to TC Waveform 1 6.5 6.0 9.0 8.0 12.5 11.0 6.0 6.0 13.0 12.0 ns ns tPLH tPHL Propagation delay CP to RC Waveform 2 2.5 3.0 4.5 5.0 7.5 7.5 2.0 2.5 8.0 8.0 ns ns tPLH tPHL Propagation delay CE to RC Waveform 2 2.0 3.0 4.0 5.0 7.0 7.5 2.0 3.0 7.5 8.0 ns ns tPLH tPHL Propagation delay U/D to RC Waveform 2 8.0 4.5 11.0 7.5 16.0 10.5 8.0 4.0 17.0 11.0 ns ns tPLH tPHL Propagation delay U/D to TC Waveform 4 4.0 3.0 6.5 6.0 9.5 9.5 3.0 3.0 10.5 10.0 ns ns tPLH tPHL Propagation delay Dn to Qn Waveform 3 2.0 6.5 4.0 9.0 7.0 12.0 1.5 6.5 7.5 13.0 ns ns tPLH tPHL Propagation delay Dn to TC Waveform 3 Waveform 4 5.5 6.5 9.5 9.5 13.0 13.0 5.0 6.0 14.0 14.0 ns ns tPLH tPHL Propagation delay Dn to RC Waveform 3 Waveform 4 6.0 6.0 14.0 11.0 18.0 13.5 6.0 6.0 19.5 15.0 ns ns tPLH tPHL Propagation delay PL to Qn Waveform 5 4.5 5.5 6.5 8.0 9.5 11.5 4.0 5.0 10.5 12.0 ns ns tPLH tPHL Propagation delay PL to TC Waveform 5 5.5 6.0 8.5 10.5 12.0 13.5 5.5 6.0 13.0 14.5 ns ns tPLH tPHL Propagation delay PL to RC Waveform 5 8.5 7.5 16.0 10.0 18.5 13.0 8.5 7.0 21.0 13.5 ns ns 1995 Jul 17 7 Philips Semiconductors Product specification Up/Down binary counter with reset and ripple clock 74F191 AC SETUP REQUIREMENTS LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb= +25°C VCC = +5.0V CL = 50pF, RL = 500Ω Min Typ Max Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω Min UNIT Max ts(H) ts(L) Setup time, High or Low Dn to PL Waveform 6 4.5 4.5 5.0 5.0 ns ns th(H) th(L) Hold time, High or Low Dn to PL Waveform 6 2.0 2.0 2.0 2.0 ns ns ts(L) Setup time, Low CE to CP Waveform 6 10.0 10.0 ns th(L) Hold time, Low CE to CP Waveform 6 0 0 ns ts(H) ts(L) Setup time, High or Low U/D to CP Waveform 6 12.0 12.0 12.0 12.0 ns ns th(H) th(L) Hold time, High or Low U/D to CP Waveform 6 0 0 0 0 ns ns tw(H) tw(L) CP Pulse width, High or Low Waveform 1 3.5 6.0 3.5 6.0 ns ns tw(L) PL Pulse width, Low Waveform 5 6.0 6.0 ns trec Recovery time, PL to CP Waveform 5 6.0 6.0 ns 1995 Jul 17 8 Philips Semiconductors Product specification Up/Down binary counter with reset and ripple clock 74F191 AC WAVEFORMS NOTE: For all waveforms, VM = 1.5V 1/fMAX CP CE, CP U/D tW(L) VM VM VM VM tPLH tW(H) tPHL tPHL tPLH RC VM RC, Qn, TC VM VM VM SF00734 SF00735 Waveform 2. Propagation Delay, Clock, Clock Enable or Up/Down to Ripple Clock Output Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency. Dn VM VM tPLH tPHL RC, TC, Qn U/D, Dn VM VM VM VM tPHL tPLH RC, TC VM VM SF00736 SF00737 Waveform 4. Propagation Delay, Inverting Path Waveform 3. Propagation Delay, Non-Inverting Path PL VM CE, Dn U/D VM tW(L) tREC VM tS(H) th(H) VM CP PL tS(L) VM th(L) VM tPLH TC, Qn VM CP tPHL RC, Qn VM The shaded areas indicate when the input is permitted to change for predictable output performance. VM SF00739 SF00738 Waveform 6. Data Set Up and Hold Times Waveform 5. Parallel Load Pulse Width, Parallel Load to Output Delay and Parallel Load to Clock Recovery Time 1995 Jul 17 VM 9 Philips Semiconductors Product specification Up/Down binary counter with reset and ripple clock 74F191 TEST CIRCUIT AND WAVEFORM VCC NEGATIVE PULSE VIN tw 90% VM D.U.T. RT CL RL AMP (V) VM 10% VOUT PULSE GENERATOR 90% 10% tTHL (tf ) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0V AMP (V) 90% 90% POSITIVE PULSE DEFINITIONS: RL = Load resistor; see AC ELECTRICAL CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC ELECTRICAL CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. VM VM 10% Test Circuit for Totem-Pole Outputs 10% tw 0V Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate tw tTLH tTHL 1MHz 500ns 2.5ns 2.5ns SF00006 1995 Jul 17 10 Philips Semiconductors Product specification Up/down binary counter with reset and ripple clock DIP16: plastic dual in-line package; 16 leads (300 mil) 1995 Jul 17 11 74F191 SOT38-4 Philips Semiconductors Product specification Up/down binary counter with reset and ripple clock SO16: plastic small outline package; 16 leads; body width 3.9 mm 1995 Jul 17 12 74F191 SOT109-1 Philips Semiconductors Product specification Up/down binary counter with reset and ripple clock NOTES 1995 Jul 17 13 74F191 Philips Semiconductors Product specification Up/down binary counter with reset and ripple clock 74F191 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: yyyy mmm dd 14 Date of release: 10-98 9397-750-05093