INTEGRATED CIRCUITS 74ALS112A Dual J-K negative edge-triggered flip-flop Product specification IC05 Data Handbook 1996 June 27 Philips Semiconductors Product specification Dual J-K negative edge-triggered flip-flop DESCRIPTION 74ALS112A PIN CONFIGURATION The 74ALS112A, dual negative edge-triggered JK-type flip-flop features individual J, K, clock (CPn), set (SD), and reset (RD) inputs, true (Qn) and complementary (Qn) outputs. CP0 1 16 VCC The SD and RD inputs, when Low, set or reset the outputs as shown in the function table regardless of the level at the other inputs. K0 2 15 RD0 J0 3 14 RD1 A High level on the clock (CPn) input enables the J and K inputs and data will be accepted. The logic levels at the J and K inputs may be allowed to change while the CPn is High and the flip-flop will perform according to the function table as long as minimum setup and hold times are observed. Output changes are initiated by the High-to-Low transition of the CPn. SD0 4 13 CP1 TYPE 74ALS112A TYPICAL fMAX TYPICAL SUPPLY CURRENT (TOTAL) 50MHz 3.0mA Q0 5 12 K1 Q0 6 11 J1 Q1 7 10 SD1 GND 8 9 Q1 SF00103 ORDERING INFORMATION ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C DRAWING NUMBER 16-pin plastic DIP 74ALS112AN SOT38-4 16-pin plastic SO 74ALS112AD SOT109-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE 74ALS (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW Clock Pulse input (active falling edge) 1.0/1.0 20µA/0.1mA J0, J1 J inputs 1.0/2.0 20µA/0.2mA K0, K1 K inputs 1.0/2.0 20µA/0.2mA SD0, SD1 Set inputs (active-Low) 1.0/2.0 20µA/0.2mA RD0, RD1 Reset inputs (active-Low) 1.0/2.0 20µA/0.2mA Data outputs 20/80 0.4mA/8mA PINS DESCRIPTION CP0, CP1 Q0, Q1, Q0, Q1 NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state. LOGIC SYMBOL IEC/IEEE SYMBOL 3 11 2 12 3 1 1 J0 CP0 K0 K1 2 15 4 SD0 15 RD0 13 CP1 10 SD1 14 J1 4 11 13 RD1 12 Q0 Q0 Q1 Q1 14 10 VCC = Pin 16 GND = Pin 8 5 6 9 5 C1 1K 6 R S 2J C2 9 2K R 7 S 7 SF00105 SF00104 1996 Jun 27 1J 2 853-1846 16995 Philips Semiconductors Product specification Dual J-K negative edge-triggered flip-flop 74ALS112A LOGIC DIAGRAM 5, 9 6, 7 Qn Qn 4, 10 15, 14 SDn RDn 2, 12 3, 11 Kn Jn 1, 13 VCC = Pin 16 GND = Pin 8 CPn SF00106 FUNCTION TABLE INPUTS OUTPUTS OPERATING MODE SD RD CP J K Q Q L H X X X H L Asynchronous Set H L X X X L H Asynchronous Reset L L X X X H* H* Undetermined * H H ↓ h h q q Toggle H H ↓ h l H L Load “1” (Set) H H ↓ l h L H Load “0” (Reset) H H ↓ l l q q Hold “no change” H H H X X q q Hold “no change” H = High voltage level h = High state must be present one setup time prior to High-to-Low clock transition L = Low voltage level l = Low state must be present one setup time prior to High-to-Low clock transition q = Lower case indicate the state of the referenced output prior to the High-to-Low clock transition X = Don’t care ↓ = High-to-Low clock transition * = Both outputs will be High while both SD and RD are Low, but the output states are unpredictable if SD and RD go High simultaneously Asynchronous inputs: Low input to SD sets Q to High level, Low input to RD sets Q to Low level. Set and reset are independent of clock. Simultaneous Low on both SD and RD makes both Q and Q High. 1996 Jun 27 3 Philips Semiconductors Product specification Dual J-K negative edge-triggered flip-flop 74ALS112A ABSOLUTE MAXIMUM RATINGS (Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) PARAMETER SYMBOL RATING UNIT V VCC Supply voltage –0.5 to +7.0 VIN Input voltage –0.5 to +7.0 V IIN Input current –30 to +5 mA VOUT Voltage applied to output in High output state –0.5 to VCC V IOUT Current applied to output in Low output state 16 mA Tamb Operating free-air temperature range 0 to +70 °C Tstg Storage temperature range –65 to +150 °C RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL PARAMETER UNIT MIN NOM MAX 5.0 5.5 VCC Supply voltage 4.5 VIH High-level input voltage 2.0 VIL Low-level input voltage 0.8 V IIk Input clamp current –18 mA IOH High-level output current –0.4 mA IOL Low-level output current 8 mA +70 °C Tamb Operating free-air temperature range V V 0 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL LIMITS TEST CONDITIONS1 PARAMETER MIN VCC = ±10%, VIL = MAX, VIH = MIN VOH High-level output voltage VOL O Low level output voltage Low-level VIK Input clamp voltage VCC = MIN, II = IIK II Input current at maximum input voltage VCC = MAX, VI = 7.0V IIH High-level input current VCC = MAX, VI = 2.7V IOH = –0.4mA TYP2 VCC – 2 V VCC = MIN, VIL = MAX, IOL = 4mA 0.25 0.40 V VIH = MIN IOL = 8mA 0.35 0.50 V –0.73 –1.5 V 0.1 mA CPn IIL Low-level input current IO Output current3 VCC = MAX, VO = 2.25V ICC Supply current (total) VCC = MAX SDn, RDn, Jn, Kn UNIT MAX VCC = MAX, VI = 0.4V –30 2.5 20 µA –0.1 mA –0.2 mA –112 mA 4.5 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. The output conditions have been chosen to produce a current that closely approximates one half of the true short–circuit output current, IOS. 1996 Jun 27 4 Philips Semiconductors Product specification Dual J-K negative edge-triggered flip-flop 74ALS112A AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω MIN fMAX Maximum clock frequency tPLH tPHL Propagation delay CPn to Qn or Qn tPLH tPHL Propagation delay SDn or RD to Qn or Qn UNIT MAX Waveform 1 35 Waveform 1 2.0 4.0 10.0 10.5 MHz ns Waveform 2, 3 1.5 3.5 8.0 9.5 ns AC SETUP REQUIREMENTS LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω MIN UNIT MAX tsu (H) tsu (L) Setup time, High or Low Jn, Kn to CPn Waveform 1 8.0 8.0 ns th (H) th (L) Hold time, High or Low Jn, Kn to CPn Waveform 1 0.0 0.0 ns tw (H) tw (L) CPn Pulse width high or Low Waveform 1 11.0 8.0 ns tw (L) SDn or RDn Pulse width Low Waveform 2, 3 6.0 ns tREC Recovery time, SDn or RDn to CPn Waveform 2, 3 8.0 ns 1996 Jun 27 5 Philips Semiconductors Product specification Dual J-K negative edge-triggered flip-flop 74ALS112A AC WAVEFORMS For all waveforms, VM = 1.3V. The sahded areas indicate when the input is permitted to change for predictable output performance. Jn, Kn VM tsu(L) VM VM VM tsu(H) th(L) th(H) 1/fmax CPn VM tw(L) VM VM tw(H) tPHL tPLH Qn VM VM tPLH tPHL VM VM Qn SC00136 Waveform 1. Propagation Delay for Data to Output, Data Setup Time and Hold Times, Clock Pulse Width, and Maximum Clock Frequency Jn, Kn SDn Jn, Kn VM tw(L) RDn VM VM tw(L) VM tREC tREC CPn CPn VM VM tPHL tPLH Qn Qn VM tPHL Qn tPLH Qn VM SC00049 VM SC00050 Waveform 2. Propagation Delay for Set to Output, Set Pulse Width, and Recovery Time for Set to Clock 1996 Jun 27 VM Waveform 3. Propagation Delay for Reset to Output, Reset Pulse Width, and Recovery Time for Reset to Clock 6 Philips Semiconductors Product specification Dual J-K negative edge-triggered flip-flop 74ALS112A TEST CIRCUIT AND WAVEFORMS VCC NEGATIVE PULSE VIN CL RL AMP (V) VM 10% D.U.T. RT 90% VM VOUT PULSE GENERATOR tw 90% 10% tTHL (tff) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0.3V AMP (V) 90% Test Circuit for Totem-pole Outputs POSITIVE PULSE 90% VM VM 10% 10% tw 0.3V Input Pulse Definition DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators. INPUT PULSE REQUIREMENTS Family Amplitude VM 74ALS 3.5V 1.3V Rep.Rate tw tTLH tTHL 1MHz 500ns 2.0ns 2.0ns SC00005 1996 Jun 27 7 Philips Semiconductors Product specification Dual J-K negative edge-triggered flip-flop DIP16: plastic dual in-line package; 16 leads (300 mil) 1996 Jun 27 8 74ALS112A SOT38-4 Philips Semiconductors Product specification Dual J-K negative edge-triggered flip-flop SO16: plastic small outline package; 16 leads; body width 3.9 mm 1996 Jun 27 9 74ALS112A SOT109-1 Philips Semiconductors Product specification Dual J-K negative edge-triggered flip-flop 74ALS112A DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Copyright Philips Electronics North America Corporation 1997 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 1996 Jun 27 10