INTEGRATED CIRCUITS 74F195A 4-bit parallel-access shift register Product specification IC15 Data Handbook 1996 Mar 12 Philips Semiconductors Product specification 4-bit parallel-access shift register 74F195A J, K, Dn, and PE inputs for logic operation, other than the set-up and hold time requirements. FEATURES • Shift right and parallel load capability • J – K (D) inputs to first stage • Complement output from last stage • Asynchronous Master Reset • Diode inputs A Low on the asynchronous Master Reset (MR) input sets all Q outputs Low, independent of any other input condition. PIN CONFIGURATION DESCRIPTION The 74F195A is a 4-Bit Parallel Access Shift Register and its functional characteristics are indicated in the Logic Diagram and Function Table. This device is useful in a variety of shifting, counting and storage applications. It performs serial, parallel, serial to parallel, or parallel to serial data transfers at very high speeds. The 74F195A operates in two primary modes: shift right (Q0→Q1) and parallel load, which are controlled by the state of the Parallel Enable (PE) input. Serial data enters the first flip-flop (Q0) via the J and K inputs when the PE input is High, and is shifted one bit in the direction Q0→Q1→Q2→Q3 following each Low-to-High clock transition. MR 1 16 VCC J 2 15 Q0 K 3 14 Q1 D0 4 13 Q2 D1 5 12 Q3 D2 6 11 Q3 D3 7 10 CP GND 8 9 PE SF00757 The J and K inputs provide the flexibility of the J-K type input for special applications, and by tying the two together the simple D-type input is made for general applications. The device appears as four common clocked D flip-flops when the PE input is Low. After the Low-to-High clock transition, data on the parallel inputs (D0–D3) is transferred to the respective Q0–Q3 outputs. Shift left operation (Q3–Q2) can be achieved by tying the Qn outputs to the Dn-1 inputs and holding the PE input Low. TYPE TYPICAL fMAX TYPICAL SUPPLY CURRENT (TOTAL) 74F195A 180MHz 40mA ORDERING INFORMATION All parallel and serial data transfers are synchronous, occurring after each Low-to-High clock transition. The 74F195A utilizes edge-triggering, therefore there is no restriction on the activity of the DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C PKG. DWG. # 16-pin plastic DIP N74F195AN SOT 38-4 16-pin plastic SO N74F195AD SOT 109-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS D0 D3 D0–D3 J K J, CP MR Q0–Q3, Q3 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW 74F195 1.0/0.033 20µA/20µA 74F195A 1.0/1.0 20µA/0.6mA 74F195 1.0/0.033 20µA/20µA 74F195A 1.0/1.0 20µA/0.6mA 74F195 1.0/0.033 20µA/20µA 74F195A 1.0/1.0 20µA/0.6mA 74F195 2.0/0.066 40µA/40µA 74F195A 1.0/1.0 20µA/0.6mA 50/33 1.0mA/20mA DESCRIPTION Data inputs J K or D type serial inputs J-K Clock Pulse input (active rising edge) Master Reset input (active Low) Data outputs NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state. 1996 Mar 12 2 853-0024 16555 Philips Semiconductors Product specification 4-bit parallel-access shift register 74F195A LOGIC SYMBOL IEC/IEEE SYMBOL 4 5 6 7 SRG4 D0 9 PE 2 J D1 D2 D3 9 M1 1 R 10 C2/1 2 1, 2J CP 3 1, 2K 3 K 4 1, 2D 1 MR 5 1, 2D 10 Q3 Q0 Q1 Q2 11 Q3 15 14 6 13 7 12 11 VCC = Pin 16 GND = Pin 8 15 14 13 12 SF00758 SF00759 LOGIC DIAGRAM CP PE J K 10 9 2 3 CP MR R S 15 Q Q0 1 RD Q 4 D0 D1 5 CP R S R S R S 14 Q Q1 RD D2 6 CP 13 Q Q2 RD D3 7 CP RD VCC = Pin 16 GND = Pin 8 1996 Mar 12 12 Q Q 11 Q3 Q3 SF00760 3 Philips Semiconductors Product specification 4-bit parallel-access shift register 74F195A FUNCTION TABLE INPUTS OUTPUTS OPERATING MODES MR CP PE J K Dn Q0 Q1 Q2 Q3 Q3 L X X X X X L L L L H Reset (clear) H ↑ h h h X H q0 q1 q2 q2 Shift, set First stage H ↑ h l l X L q0 q1 q2 q2 Shift, reset First stage H ↑ h h l X q0 q0 q1 q2 q2 Shift, toggle First stage H ↑ h l h X q0 q0 q1 q2 q2 Shift, retain First stage H = High voltage level h = High voltage level one setup time prior to Low-to-High clock transition L = Low voltage level l = Low voltage level one setup time prior to Low-to-High clock transition X = Don’t care ↑ = Low-to-High clock transition dn(qn) = Lower case letters indicate the state of the referenced input (or output) one setup time prior to the Low-to-High clock transition. ABSOLUTE MAXIMUM RATINGS (Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) RATING UNIT VCC Supply voltage PARAMETER –0.5 to +7.0 V VIN Input voltage –0.5 to +7.0 V IIN Input current –30 to +5 mA VOUT Voltage applied to output in High output state –0.5 to +VCC V IOUT Current applied to output in Low output state 40 mA Tamb Operating free-air temperature range 0 to +70 °C Tstg Storage temperature –65 to +150 °C SYMBOL RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL PARAMETER UNIT MIN NOM MAX 5.0 5.5 VCC Supply voltage 4.5 VIH High-level input voltage 2.0 VIL Low-level input voltage 0.8 V IIK Input clamp current –18 mA IOH High-level output current –1 mA IOL Low-level output current 20 mA Tamb Operating free-air temperature range 70 °C 1996 Mar 12 0 4 V V Philips Semiconductors Product specification 4-bit parallel-access shift register 74F195A DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) LIMITS SYMBOL PARAMETER TEST CONDITIONSNO TAG TYP MIN VOH O VCC = MIN,, VIL = MAX VIH = MIN, IOH = MAX High level output voltage High-level ±10%VCC 2.5 ±5%VCC 2.7 NO TAG UNIT MAX V 3.4 V ±10%VCC 0.35 0.50 ±5%VCC 0.35 0.50 –0.73 –1.2 V 100 µA VOL O Low level output voltage Low-level VCC = MIN,, VIL = MAX VIH = MIN, IOL = MAX VIK Input clamp voltage VCC = MIN, II = IIK II Input current at maximum input voltage VCC = MAX, VI = 7.0V 74F195A IIH High-level input current VCC = MAX, VI = 2.7V all others 20 µA IIL Low-level input current VCC = MAX, VI = 0.5V 74F195A –600 mA IOS Short-circuit output current3 VCC = MAX –150 mA ICC Supply current (total) VCC = MAX 58 mA –60 74F195A 40 V NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER Load mode VCC = +5V Tamb = +25°C CL = 50pF, RL = 500Ω TEST CONDITION MAX VCC = +5V ± 10% Tamb = 0°C to +70°C CL = 50pF, RL = 500Ω MIN TYP Waveform NO TAG 165 180 MIN 150 180 190 170 UNIT MAX fMAX Maximum clock frequency tPLH tPHL Propagation delay CP to Qn Waveform NO TAG 3.0 2.5 5.0 4.0 9.5 7.0 2.5 2.0 10.0 7.5 ns tPLH tPHL Propagation delay CP to Q3 Waveform NO TAG 2.0 2.0 5.5 4.0 9.5 6.5 2.5 2.0 9.5 7.0 ns tPHL Propagation delay MR to Qn Waveform 2 2.0 4.0 7.0 2.0 7.0 ns tPLH Propagation delay MR to Q3 Waveform 2 2.5 4.5 8.0 2.0 10.0 ns 1996 Mar 12 Shift mode 5 MHz Philips Semiconductors Product specification 4-bit parallel-access shift register 74F195A AC SETUP REQUIREMENTS LIMITS SYMBOL VCC = +5V Tamb = +25°C CL = 50pF, RL = 500Ω TEST CONDITION PARAMETER MIN TYP VCC = +5V ± 10% Tamb = 0°C to +70°C CL = 50pF, RL = 500Ω MAX MIN UNIT MAX tS(H) tS(L) Setup time, High or Low J, K and Dn to CP Waveform 3 2.5 2.5 2.5 2.5 ns th(H) th(L) Hold time, High or Low J, K and Dn to CP Waveform 3 0.0 1.0 0.0 1.0 ns tS(H) tS(L) Setup time, High or Low PE to CP Waveform 4 2.0 2.5 2.0 2.5 ns th(H) th(L) Hold time, High or Low PE to CP Waveform 4 0.0 0.0 0.0 0.0 ns tW(H) CP Pulse width High Waveform NO TAG 4.5 4.5 ns tW(L) MR Pulse width Low Waveform 2 4.5 4.5 ns tREC Recovery time MR to CP Waveform 2 2.5 3.0 ns AC WAVEFORMS For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance. 1/fmax VM MR VM VM CP trec tw(L) tw(H) tPHL tPLH VM CP VM VM Q3 VM VM tPHL tPLH tPHL Qn VM Qn VM VM tPLH SF00761 Q3 VM Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency SF00762 Waveform 3. Master Reset Pulse Width, Master Reset to Output Delay, and Master Reset to Clock Recovery Time SERIAL-SHIFT RIGHT J, K, Dn VM VM VM VM ts(H) th(H) ts(L) th(L) PE VM VM ts(H) CP VM PARALLEL LOAD VM th VM ts(L) th VM CP VM VM SF00763 Waveform 2. Qn Data Setup and Hold Times RESPONSE Qn=Qn–1 Qn=Dn SF00764 Waveform 4. 1996 Mar 12 6 Setup and Hold Times, Parallel Enable to Clock Philips Semiconductors Product specification 4-bit parallel-access shift register 74F195A TEST CIRCUIT AND WAVEFORMS VCC VIN tw 90% NEGATIVE PULSE VM D.U.T. RT CL RL AMP (V) VM 10% VOUT PULSE GENERATOR 90% 10% tTHL (tf ) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0V AMP (V) 90% 90% POSITIVE PULSE Test Circuit for Totem-Pole Outputs DEFINITIONS: RL = Load resistor; see AC ELECTRICAL CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC ELECTRICAL CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. VM VM 10% 10% tw 0V Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate tw tTLH tTHL 1MHz 500ns 2.5ns 2.5ns SF00006 1996 Mar 12 7 Philips Semiconductors Product specification 74F195A 4-bit parallel-access shift register DIP16: plastic dual in-line package; 16 leads (300 mil) 1996 Mar 12 8 SOT38-4 Philips Semiconductors Product specification 74F195A 4-bit parallel-access shift register NOTES 1996 Mar 12 9 Philips Semiconductors Product specification 74F195A 4-bit parallel-access shift register Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: yyyy mmm dd 10 Date of release: 10-98 9397-750-05096