PHILIPS 74LVC4066D

INTEGRATED CIRCUITS
DATA SHEET
74LVC4066
Quad bilateral switches
Product specification
2003 Aug 12
Philips Semiconductors
Product specification
Quad bilateral switches
74LVC4066
FEATURES
DESCRIPTION
• Very low ON resistance:
The 74LVC4066 is a high-speed Si-gate CMOS device.
– 7.5 Ω (typical) at VCC = 2.7 V
The 74LVC4066 has four independent analog switches.
Each switch has two input/output terminals (nY and nZ)
and an active HIGH enable input (nE). When nE is LOW,
the analog switch is turned off.
– 6.5 Ω (typical) at VCC = 3.3 V
– 6 Ω (typical) at VCC = 5 V.
• ESD protection:
– HBM EIA/JESD22-A114-A Exceeds 2000 V
– MM EIA/JESD22-A115-A Exceeds 200 V.
• High noise immunity
• CMOS low power consumption
• Latch up performance exceeds 250 mA
• Complies with JEDEC standard no. 8-1A
• Direct interface TTL-levels.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns.
SYMBOL
tPZH/tPZL
PARAMETER
turn-on time E to Vos
CONDITIONS
TYPICAL
UNIT
CL = 50 pF; RL = 500 Ω; VCC = 3 V
2.5
ns
CL = 50 pF; RL = 500 Ω; VCC = 5 V
1.9
ns
CL = 50 pF; RL = 500 Ω; VCC = 3 V
3.4
ns
tPHZ/tPLZ
turn-off time E to Vos
CL = 50 pF; RL = 500 Ω; VCC = 5 V
2.5
ns
CI
input capacitance
VCC = 3 V
3.5
pF
CPD
power dissipation capacitance
VCC = 3.3 V; notes 1 and 2
12.5
pF
CS
switch capacitance
OFF-state
8.0
pF
ON-state
14.0
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + ((CL + CS) × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
CS = switch capacitance.
2. The condition is VI = GND to VCC.
2003 Aug 12
2
Philips Semiconductors
Product specification
Quad bilateral switches
74LVC4066
FUNCTION TABLE
See note 1.
INPUT nE
SWITCH
L
OFF
H
ON
Note
1. H = HIGH voltage level;
L = LOW voltage level.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
TEMPERATURE
RANGE
PINS
74LVC4066D
−40 to +125 °C
14
SO14
plastic
SOT108-2
74LVC4066PW
−40 to +125 °C
14
TSSOP14
plastic
SOT402-1
74LVC4066BQ
−40 to +125 °C
14
DHVQFN14
plastic
SOT762-1
PACKAGE
MATERIAL
CODE
PINNING
PIN
SYMBOL
DESCRIPTION
1
1Y
independent input/output
2
1Z
independent output/input
3
2Z
independent output/input
4
2Y
independent input/output
5
2E
enable input (active HIGH)
6
3E
enable input (active HIGH)
7
GND
ground (0 V)
8
3Y
9
handbook, halfpage
1Y
1
14 VCC
1Z
2
13 1E
2Z
3
12 4E
2Y
4
2E
5
10 4Z
independent input/output
3E
6
9
3Z
independent output/input
GND
7
8 3Y
10
4Z
independent output/input
11
4Y
independent input/output
12
4E
enable input (active HIGH)
13
1E
enable input (active HIGH)
14
VCC
supply voltage
2003 Aug 12
4066
11 4Y
3Z
MNB109
Fig.1 Pin configuration SO14 and TSSOP14.
3
Philips Semiconductors
Product specification
Quad bilateral switches
handbook, halfpage
1Y
VCC
1
14
74LVC4066
handbook, halfpage
1Z
2
13
1E
2Z
3
12
4E
2Y
4
11
4Y
2E
5
10
4Z
3E
6
9
3Z
GND(1)
Top view
7
8
GND
3Y
1
1Y
13
1E
4
2Y
5
2E
8
3Y
6
3E
11
4Y
12
4E
1Z
2
2Z
3
3Z
9
4Z 10
MNB110
MNB111
(1) The die substrate is attached to this pad using conductive die
attach material. It can not be used as a supply pin or input.
Fig.2 Pin configuration DHVQFN14.
1
1
2
4
4
3
2
X1
5
1
#
1
3
Z
X1
#
8
6
1
handbook, halfpage
13 #
5
1
13 #
Fig.3 Logic symbol.
9
#
8
6
1
#
1
9
Y
X1
E
11
10
12 #
11
12 #
(a)
1
1
10
X1
VCC
(b)
MNB112
Fig.4 logic symbol (IEEE/IEC).
2003 Aug 12
Fig.5 Logic diagram (one switch).
4
MNA658
Philips Semiconductors
Product specification
Quad bilateral switches
74LVC4066
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VCC
supply voltage
1.65
5.5
V
VI
input voltage
0
5.5
V
VS
switch voltage
0
VCC
V
Tamb
operating ambient temperature
tr, tf
input rise and fall times
−40
+125
°C
VCC = 1.65 to 2.7 V
0
20
ns/V
VCC = 2.7 to 5.5 V
0
10
ns/V
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V);
see note 1.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
−0.5
+6.5
V
VCC
supply voltage
VI
input voltage
note 2
−0.5
+6.5
V
IIK
input diode current
VI < −0.5 V or VI > VCC + 0.5 V
−
−50
mA
ISK
switch diode current
VI < −0.5 V or VI > VCC + 0.5 V
−
±50
mA
VS
switch voltage
enable and disable mode
−0.5
+6.5
V
−0.5 < VS < VCC + 0.5 V
IS
switch source or sink current
−
±50
mA
ICC, IGND
VCC or GND current
−
±100
mA
Tstg
storage temperature
−65
+150
°C
Ptot
power dissipation
−
500
mW
Tamb = −40 to +125 °C; note 3
Notes
1. To avoid drawing VCC current out of terminal Z, when switch current flows in terminal Y, the voltage drop across the
bidirectional switch must not exceed 0.4 V. If the switch current flows into terminal Z, no VCC current will flow out of
terminal Y. In this case there is no limit for the voltage drop across the switch, but the voltage at Y and Z may not
exceed VCC or GND.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
3. For SO14 packages: above 70 °C derate linearly with 8 mW/K.
For TSSOP14 packages: above 60 °C derate linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60 °C derate linearly with 4.5 mW/K.
2003 Aug 12
5
Philips Semiconductors
Product specification
Quad bilateral switches
74LVC4066
DC CHARACTERISTICS
At recommended operating conditions; voltage are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
VCC (V)
OTHER
Tamb = −40 to +85 °C; note 1
VIH
VIL
HIGH-level input
voltage
LOW-level input
voltage
1.65 to 1.95
0.65VCC
−
−
V
2.3 to 2.7
1.7
−
−
V
2.7 to 3.6
2.0
−
−
V
4.5 to 5.5
0.7VCC
−
−
V
1.65 to 1.95
−
−
0.35VCC
V
2.3 to 2.7
−
−
0.7
V
2.7 to 3.6
−
−
0.8
V
4.5 to 5.5
−
−
0.30VCC
V
ILI
input leakage current
(control pin)
VI = 5.5 V or GND
5.5
−
±0.1
±5
µA
IS(OFF)
analog switch
OFF-state current
VI = VIH or VIL;
5.5
|VS| = VCC − GND; see Fig.7
−
±0.1
±5
µA
IS(ON)
analog switch
ON-state current
VI = VIH or VIL;
5.5
|VS| = VCC − GND; see Fig.8
−
±0.1
±5
µA
ICC
quiescent supply
current
VI = VCC or GND;
VS = GND or VCC; IO = 0 A
5.5
−
0.1
10
µA
∆ICC
additional quiescent
supply current per
control pin
VI = VCC − 0.6 V;
VS = GND or VCC; IO = 0 A
5.5
−
5
500
µA
2003 Aug 12
6
Philips Semiconductors
Product specification
Quad bilateral switches
74LVC4066
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
OTHER
TYP.
MAX.
UNIT
VCC (V)
Tamb = −40 to +125 °C
VIH
VIL
HIGH-level input
voltage
LOW-level input
voltage
1.65 to 1.95
0.65VCC
−
−
V
2.3 to 2.7
1.7
−
−
V
2.7 to 3.6
2.0
−
−
V
4.5 to 5.5
0.7VCC
−
−
V
1.65 to 1.95
−
−
0.35VCC
V
2.3 to 2.7
−
−
0.7
V
2.7 to 3.6
−
−
0.8
V
4.5 to 5.5
−
−
0.30VCC
V
ILI
input leakage current
(control pin)
VI = 5.5 V or GND
5.5
−
−
±20
µA
IS(OFF)
analog switch
OFF-state current
5.5
VI = VIH or VIL;
|VS| = VCC − GND; see Fig.7
−
−
±20
µA
IS(ON)
analog switch
ON-state current
5.5
VI = VIH or VIL;
|VS| = VCC − GND; see Fig.8
−
−
±20
µA
ICC
quiescent supply
current
VI = VCC or GND;
VS = GND or VCC; IO = 0 A
5.5
−
−
40
µA
∆ICC
additional quiescent
supply current per
control pin
VI = VCC − 0.6 V;
VS = GND or VCC; IO = 0 A
5.5
−
−
5000
µA
Note
1. All typical values are measured at Tamb = 25 °C.
2003 Aug 12
7
Philips Semiconductors
Product specification
Quad bilateral switches
74LVC4066
Resistance RON
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
OTHER
IS (mA)
TYP.
MAX. UNIT
VCC (V)
Tamb = −40 to +85 °C; note 1; see Fig.6
RON(peak)
RON(rail)
ON-resistance
(peak)
ON-resistance (rail)
VS = GND to VCC;
VI = VIH
VS = GND; VI = VIH
VS = VCC; VI = VIH
RON(flatness)
2003 Aug 12
ON-resistance
(flatness)
VS = GND to VCC;
VI = VIH;
see Figs.10 to 13
8
4
1.65 to 1.95
−
35
100
Ω
8
2.3 to 2.7
−
14
30
Ω
12
2.7
−
11.5
25
Ω
24
3.0 to 3.6
−
8.5
20
Ω
32
4.5 to 5.5
−
6.5
15
Ω
4
1.65 to 1.95
−
10
30
Ω
8
2.3 to 2.7
−
8.5
20
Ω
12
2.7
−
7.5
18
Ω
24
3.0 to 3.6
−
6.5
15
Ω
32
4.5 to 5.5
−
6
10
Ω
4
1.65 to 1.95
−
12
30
Ω
8
2.3 to 2.7
−
8.5
20
Ω
12
2.7
−
7.5
18
Ω
24
3.0 to 3.6
−
6.5
15
Ω
32
4.5 to 5.5
−
6
10
Ω
4
1.8
−
100
−
Ω
8
2.5
−
17
−
Ω
12
2.7
−
10
−
Ω
24
3.3
−
5
−
Ω
32
5.0
−
3
−
Ω
Philips Semiconductors
Product specification
Quad bilateral switches
74LVC4066
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
OTHER
IS (mA)
TYP.
MAX. UNIT
VCC (V)
Tamb = −40 to +125 °C; see Fig.6
RON(peak)
RON(rail)
ON-resistance
(peak)
ON-resistance (rail)
VS = GND to VCC;
VI = VIH
VS = GND; VI = VIH
VS = VCC; VI = VIH
4
1.65 to 1.95
−
−
150
Ω
8
2.3 to 2.7
−
−
45
Ω
12
2.7
−
−
38
Ω
24
3.0 to 3.6
−
−
30
Ω
32
4.5 to 5.5
−
−
23
Ω
4
1.65 to 1.95
−
−
45
Ω
8
2.3 to 2.7
−
−
30
Ω
12
2.7
−
−
27
Ω
24
3.0 to 3.6
−
−
23
Ω
32
4.5 to 5.5
−
−
15
Ω
4
1.65 to 1.95
−
−
45
Ω
8
2.3 to 2.7
−
−
30
Ω
12
2.7
−
−
27
Ω
24
3.0 to 3.6
−
−
23
Ω
32
4.5 to 5.5
−
−
15
Ω
Note
1. Typical value Ron(flatness) is measured at Tamb = −40 to +85 °C, all other typical values are measured at Tamb = 25 °C.
2003 Aug 12
9
Philips Semiconductors
Product specification
Quad bilateral switches
74LVC4066
E
VIL
E
VIH
V
Y
Y
Z
Z
VS = GND to VCC
A
A
VI = VCC or GND
VO = GND or VCC
IS
GND
GND
MNA659
GND
MNA660
Fig.6
Test circuit for measuring ON-state
resistance (RON).
Fig.7 Test circuit for measuring OFF-state current.
MNA673
102
handbook, halfpage
RON
(Ω)
VIH
VCC = 1.8 V
E
Y
Z
2.5 V
2.7 V
10
3.3 V
A
A
VI = VCC or GND
VO (open circuit)
5.0 V
GND
MNA661
1
Fig.9
Fig.8 Test circuit for measuring ON-state current.
2003 Aug 12
10
0
1
2
3
4
VI (V)
5
Typical ON-resistance (RON) as a function
of input voltage (VS) for VS = GND to VCC.
Philips Semiconductors
Product specification
Quad bilateral switches
74LVC4066
MNA663
15
RON
handbook, halfpage
RON
Tamb = +85 °C
+25 °C
−40 °C
(Ω)
10
(Ω)
Tamb = +85 °C
+25 °C
−40 °C
10
5
0
MNA664
15
handbook, halfpage
5
0
1
2
Vl (V)
0
3
0
Fig.10 RON for VCC = 2.5 V.
2
Vl (V)
3
Fig.11 RON for VCC = 2.7 V.
MNA665
10
1
MNA666
8
handbook, halfpage
handbook, halfpage
RON
RON
(Ω)
(Ω)
Tamb =
8
7
+85 °C
6
Tamb = +85 °C
+25 °C
6
5
−40 °C
+25 °C
4
4
2
−40 °C
3
2
0
0
1
2
3
Vl (V)
0
4
Fig.12 RON for VCC = 3.3 V.
2003 Aug 12
1
2
3
4
VI (V)
Fig.13 RON for VCC = 5.0 V.
11
5
Philips Semiconductors
Product specification
Quad bilateral switches
74LVC4066
AC CHARACTERISTICS
GND = 0 V.
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
WAVEFORMS
TYP.
MAX.
UNIT
VCC (V)
Tamb = −40 to +85 °C; note 1
tPHL/tPLH
tPZH/tPZL
tPHZ/tPLZ
propagation delay nY to nZ see Figs 14 and 16;
or nZ to nY
note 2
turn-ON time E to VOS
turn-OFF time E to VOS
see Figs 15 and 16
see Figs 15 and 16
1.65 to 1.95
−
0.8
2.0
ns
2.3 to 2.7
−
0.4
1.2
ns
2.7
−
0.4
1.0
ns
3.0 to 3.6
−
0.3
0.8
ns
4.5 to 5.5
−
0.2
0.6
ns
1.65 to 1.95
1.0
5.3
10
ns
2.3 to 2.7
1.0
3.0
5.6
ns
2.7
1.0
2.6
5.0
ns
3.0 to 3.6
1.0
2.5
4.4
ns
4.5 to 5.5
1.0
1.9
3.9
ns
1.65 to 1.95
1.0
4.2
9.0
ns
2.3 to 2.7
1.0
2.4
5.5
ns
2.7
1.0
3.6
6.5
ns
3.0 to 3.6
1.0
3.4
6.0
ns
4.5 to 5.5
1.0
2.5
5.0
ns
Tamb = −40 to +125 °C
tPHL/tPLH
tPZH/tPZL
tPHZ/tPLZ
propagation delay nY to nZ see Figs 14 and 16;
or nZ to nY
note 2
turn-ON time E to VOS
turn-OFF time E to VOS
see Figs 15 and 16
see Figs 15 and 16
1.65 to 1.95
−
−
3.0
ns
2.3 to 2.7
−
−
2.0
ns
2.7
−
−
1.5
ns
3.0 to 3.6
−
−
1.5
ns
4.5 to 5.5
−
−
1.0
ns
1.65 to 1.95
1.0
−
12.5
ns
2.3 to 2.7
1.0
−
7.0
ns
2.7
1.0
−
6.5
ns
3.0 to 3.6
1.0
−
5.5
ns
4.5 to 5.5
1.0
−
5.0
ns
1.65 to 1.95
1.0
−
11.5
ns
2.3 to 2.7
1.0
−
7.0
ns
2.7
1.0
−
8.5
ns
3.0 to 3.6
1.0
−
7.5
ns
4.5 to 5.5
1.0
−
6.5
ns
Notes
1. All typical values are measured at Tamb = 25 °C.
2. tPHL/tPLH propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and
the specified capacitance when driven by an ideal voltage source (zero output impedance).
2003 Aug 12
12
Philips Semiconductors
Product specification
Quad bilateral switches
74LVC4066
AC WAVEFORMS
handbook, halfpage VI
VM
Y or Z
GND
t PHL
t PLH
VOH
VM
Z or Y
VOL
MNA667
INPUT
VCC
VM
VI
tr = tf
1.65 to 1.95 V
0.5VCC
VCC
≤ 2.0 ns
2.3 to 2.7 V
0.5VCC
VCC
≤ 2.0 ns
2.7 and 3.0 to 3.6 V 1.5 V
2.7 V
≤ 2.5 ns
4.5 to 5.5 V
VCC
≤ 2.5 ns
0.5VCC
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.14 The input (VS) to output (VO) propagation delays.
2003 Aug 12
13
Philips Semiconductors
Product specification
Quad bilateral switches
74LVC4066
VI
handbook, full pagewidth
E
VM
GND
t PLZ
t PZL
VCC
output
LOW-to-OFF
OFF-to-LOW
Y or Z
VM
VX
VOL
t PZH
t PHZ
output
HIGH-to-OFF
OFF-to-HIGH
Y or Z
VOH
VY
VM
GND
switch
enabled
switch
disabled
switch
enabled
MNA668
INPUT
VCC
VM
VI
tr = tf
1.65 to 1.95 V
0.5VCC
VCC
≤ 2.0 ns
2.3 to 2.7 V
0.5VCC
VCC
≤ 2.0 ns
2.7 and 3.0 to 3.6 V
1.5 V
2.7 V
≤ 2.5 ns
4.5 to 5.5 V
0.5VCC
VCC
≤ 2.5 ns
VX = VOL + 0.3 V at VCC ≥ 2.7 V;
VX = VOL + 0.1 × VCC at VCC < 2.7 V;
VY = VOH − 0.3 V at VCC ≥ 2.7 V;
VY = VOH − 0.1 × VCC at VCC < 2.7 V.
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.15 Turn-on and turn-off times.
2003 Aug 12
14
Philips Semiconductors
Product specification
Quad bilateral switches
74LVC4066
VEXT
handbook, full pagewidth
VCC
VI
PULSE
GENERATOR
RL
VO
D.U.T.
CL
RT
RL
MNA616
VCC
VI
CL
VEXT
RL
tPLH/tPHL
tPZH/tPHZ
tPZL/tPLZ
1.65 to 1.95 V
VCC
30 pF
1 kΩ
open
GND
2VCC
2.3 to 2.7 V
VCC
30 pF
500 Ω
open
GND
2VCC
2.7 and 3.0 to 3.6 V 2.7 V
50 pF
500 Ω
open
GND
6V
4.5 to 5.5 V
50 pF
500 Ω
open
GND
2VCC
VCC
Definitions for test circuits:
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.16 Load circuitry for switching times.
ADDITIONAL AC CHARACTERISTICS
Recommended conditions and typical values at Tamb = 25 °C.
SYMBOL
dsin
PARAMETER
sine-wave distortion
RL = 10 kΩ; CL = 50 pF; fin = 1 kHz; 1.65
see Fig.18
2.3
RL = 10 kΩ; CL = 50 pF;
fin = 10 kHz; see Fig.18
fON
switch ON signal frequency
response
RL = 600 Ω; CL = 50 pF; see
Fig.17; note 1
RL = 50 Ω; CL = 5 pF; see Fig.17;
note 1
2003 Aug 12
VCC (V)
TEST CONDITIONS
15
TYPICAL
UNIT
0.032
%
0.008
%
3
0.006
%
4.5
0.005
%
1.65
0.068
%
2.3
0.009
%
3
0.008
%
4.5
0.006
%
1.65
170
MHz
2.3
210
MHz
3
212
MHz
4.5
215
MHz
1.65
> 500
MHz
2.3
> 500
MHz
3
> 500
MHz
4.5
> 500
MHz
Philips Semiconductors
Product specification
Quad bilateral switches
SYMBOL
αOFF(feedthru)
74LVC4066
PARAMETER
TEST CONDITIONS
switch OFF signal feed-through
attenuation
VCC (V)
RL = 600 Ω; CL = 50 pF;
fin = 1 MHz; see Fig.19; note 2
αct(S)
crosstalk between control input
to signal output
crosstalk between switches)
−46
dB
2.3
−46
dB
3
−46
dB
4.5
−46
dB
1.65
−42
dB
2.3
−42
dB
3
−42
dB
4.5
−42
dB
RL = 600 Ω; CL = 50 pF;
fin = 1 MHz; tr = tf = 2 ns; see
Fig.20
1.65
69
mV
2.3
87
mV
3
156
mV
4.5
302
mV
RL = 600 Ω; CL = 50 pF;
fin = 1 MHz; see Fig.21
1.65
−58
dB
2.3
−58
dB
3
−58
dB
4.5
−58
dB
1.65
−58
dB
2.3
−58
dB
3
−58
dB
4.5
−58
dB
RL = 50 Ω; CL = 5 pF; fin = 1 MHz;
see Fig.21
CPD
Q
power dissipation capacitance
fin = 10 MHz
2.5
11.0
pF
3.3
12.5
pF
5.0
15.6
pF
0.8
pC
1.2
pC
CL = 0.1 nF; Vgen = 0 V; Rgen = 0 Ω; 3.3
f = 1 MHz; RL = 1 MΩ; see Fig.22; 5.5
note 3
charge injection
Notes
1. Adjust fin voltage to obtain 0 dBm level at output. Increase fin frequency until dB meter reads −3 dB.
2. Adjust fin voltage to obtain 0 dBm level at input.
3. Guaranteed by design.
handbook, full pagewidth
VIH
E
0.1 µF
fin
Y/Z
Z/Y
50 Ω
VO
RL
channel
ON
1/2VCC
CL dB
MNA669
Fig.17 Test circuit for measuring the frequency response when switch is ON.
2003 Aug 12
UNIT
1.65
RL = 50 Ω; CL = 5 pF; fin = 1 MHz;
see Fig.19; note 2
αct(E-Y/Z)
TYPICAL
16
Philips Semiconductors
Product specification
Quad bilateral switches
74LVC4066
E
handbook, full pagewidth
VIH
Y/Z
600 Ω
fin
10 µF
Z/Y
VO
CL
RL
channel
ON
DISTORTION
METER
1/2VCC
MNA670
VCC
VIH
1.65 V
1.4 V (p-p)
2.3 V
2 V (p-p)
3V
2.5 V (p-p)
4. V
4 V (p-p)
Fig.18 Test circuit for measuring sine-wave distortion.
handbook, full pagewidth
VIL
E
0.1 µF
fin
50 Ω
Y/Z
Z/Y
RL
VO
RL
channel
OFF
1/2VCC
CL dB
1/2VCC
MNB113
Fig.19 Test circuit for measuring feed-through when switch is OFF.
handbook, full pagewidth
E
Y/Z
50 Ω
Z/Y
VO
RL
600 Ω
Rin
600 Ω
CL
50 pF
1/2VCC
1/2VCC
MNA672
Fig.20 Crosstalk between control input to signal output.
2003 Aug 12
17
Philips Semiconductors
Product specification
Quad bilateral switches
74LVC4066
handbook, full pagewidth
E1
VIH
0.1 µF
Rin
1Y or 1Z
1Z or 1Y
VO1
600 Ω
fin
RL
600 Ω
50 Ω
CL
50 pF
channel ON
1/2VCC
E2
VIL
2Y or 2Z
2Z or 2Y
VO2
RL
600 Ω
Rin
600 Ω
CL
50 pF
channel OFF
1/2VCC
MNB114
Fig.21 Crosstalk between switches.
E
handbook, full pagewidth
Rgen
Y/Z
logic
input
Z/Y
Vgen
RL
VO
1
MΩ
CL
MNA674
handbook, full pagewidth
logic
input (E)
off
on
off
∆Vout
VO
MNA675
Q = ∆Vout × CL
Fig.22 Charge injection test.
2003 Aug 12
18
0.1
nF
Philips Semiconductors
Product specification
Quad bilateral switches
74LVC4066
PACKAGE OUTLINES
SO14: plastic small outline package; 14 leads; body width 3.9 mm; body thickness 1.47 mm
D
E
SOT108-2
A
X
c
y
HE
v M A
Z
8
14
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
7
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.55
1.40
0.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.25
0.25
0.1
0.7
0.3
0.010 0.061
0.004 0.055
0.01
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.05
0.01
0.01
0.004
0.028
0.012
inches 0.069
0.244
0.039
0.041
0.228
0.016
θ
o
8
0o
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
OUTLINE
VERSION
SOT108-2
2003 Aug 12
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
01-05-29
03-02-19
MS-012
19
Philips Semiconductors
Product specification
Quad bilateral switches
74LVC4066
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
E
D
A
X
c
y
HE
v M A
Z
8
14
Q
(A 3)
A2
A
A1
pin 1 index
θ
Lp
L
1
7
detail X
w M
bp
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.72
0.38
8
0o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT402-1
2003 Aug 12
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
MO-153
20
o
Philips Semiconductors
Product specification
Quad bilateral switches
74LVC4066
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
SOT762-1
14 terminals; body 2.5 x 3 x 0.85 mm
A
B
D
A
A1
E
c
detail X
terminal 1
index area
terminal 1
index area
C
e1
e
2
6
y
y1 C
v M C A B
w M C
b
L
1
7
Eh
e
14
8
13
9
Dh
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max.
A1
b
c
D (1)
Dh
E (1)
Eh
e
e1
L
v
w
y
y1
mm
1
0.05
0.00
0.30
0.18
0.2
3.1
2.9
1.65
1.35
2.6
2.4
1.15
0.85
0.5
2
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT762-1
---
MO-241
---
2003 Aug 12
21
EUROPEAN
PROJECTION
ISSUE DATE
02-10-17
03-01-27
Philips Semiconductors
Product specification
Quad bilateral switches
74LVC4066
DATA SHEET STATUS
LEVEL
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
Development
DEFINITION
I
Objective data
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Production
This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
DEFINITIONS
DISCLAIMERS
Short-form specification  The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Life support applications  These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition  Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes  Philips Semiconductors
reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2003 Aug 12
22
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: [email protected].
SCA75
© Koninklijke Philips Electronics N.V. 2003
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
613508/01/pp23
Date of release: 2003
Aug 12
Document order number:
9397 750 11652