Philips Semiconductors Product specification N-channel TrenchMOS transistor FEATURES PHX14NQ20T , PHF14NQ20T SYMBOL QUICK REFERENCE DATA • ’Trench’ technology • Low on-state resistance • Fast switching d VDSS = 200 V ID = 7.6 A g RDS(ON) ≤ 230 mΩ s GENERAL DESCRIPTION N-channel enhancement mode field-effect power transistor in a plastic full pack envelope using ’trench’ technology. The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching applications. The PHX14NQ20T is supplied in the SOT186A (FPAK) conventional leaded package. PINNING SOT186A (FPAK) PIN SOT186 (FPAK) DESCRIPTION case case 1 gate 2 drain 3 source case isolated 1 2 3 1 2 3 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDSS VDGR VGS ID Drain-source voltage Drain-gate voltage Gate-source voltage Continuous drain current Tj = 25 ˚C to 150˚C Tj = 25 ˚C to 150˚C; RGS = 20 kΩ IDM PD Tj, Tstg Pulsed drain current Total power dissipation Operating junction and storage temperature - 55 200 200 ± 20 7.6 4.8 30 30 150 V V V A A A W ˚C November 2000 Ths = 25 ˚C; VGS = 10 V Ths = 100 ˚C; VGS = 10 V Ths = 25 ˚C Ths = 25 ˚C 1 Rev 1.100 Philips Semiconductors Product specification N-channel TrenchMOS transistor PHX14NQ20T , PHF14NQ20T AVALANCHE ENERGY LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER EAS Non-repetitive avalanche energy IAS Peak non-repetitive avalanche current CONDITIONS MIN. MAX. UNIT - 70 mJ - 14 A Unclamped inductive load, IAS = 14 A; tp = 38 µs; Tj prior to avalanche = 25˚C; VDD ≤ 25 V; RGS = 50 Ω; VGS = 10 V; refer to fig 15 THERMAL RESISTANCES SYMBOL PARAMETER Rth j-hs Rth j-a Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS MIN. SOT186A package, in free air TYP. MAX. UNIT - - 4.17 K/W - 55 - K/W ELECTRICAL CHARACTERISTICS Tj= 25˚C unless otherwise specified SYMBOL PARAMETER V(BR)DSS VGS(TO) Drain-source breakdown voltage Gate threshold voltage CONDITIONS VGS = 0 V; ID = 0.25 mA; Tj = -55˚C VDS = VGS; ID = 1 mA Tj = 150˚C Tj = -55˚C RDS(ON) MIN. TYP. MAX. UNIT 200 178 2 1 6 - 3 150 12.1 10 0.05 - 4 6 230 540 100 10 500 V V V V V mΩ mΩ S nA µA µA Drain-source on-state resistance Forward transconductance Gate source leakage current Zero gate voltage drain current VGS = 10 V; ID = 7 A VGS = 10 V; ID = 7 A; Tj = 150˚C VDS = 25 V; ID = 7 A VGS = ± 10 V; VDS = 0 V VDS = 200 V; VGS = 0 V Tj = 150˚C Qg(tot) Qgs Qgd Total gate charge Gate-source charge Gate-drain (Miller) charge ID = 14 A; VDD = 160 V; VGS = 10 V - 38 4 13.3 - nC nC nC td on tr td off tf Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time VDD = 100 V; RD = 10 Ω; VGS = 10 V; RG = 5.6 Ω Resistive load - 25 40 83 31 - ns ns ns ns Ld Ls Internal drain inductance Internal source inductance Measured from drain lead to centre of die Measured from source lead to source bond pad - 4.5 7.5 - nH nH Ciss Coss Crss Input capacitance Output capacitance Feedback capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 1500 128 60 - pF pF pF gfs IGSS IDSS November 2000 2 Rev 1.100 Philips Semiconductors Product specification N-channel TrenchMOS transistor PHX14NQ20T , PHF14NQ20T REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25˚C unless otherwise specified SYMBOL PARAMETER VSD Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage trr Qrr Reverse recovery time Reverse recovery charge IS ISM CONDITIONS MIN. TYP. MAX. UNIT - - 14 A - - 56 A IF = 14 A; VGS = 0 V - 1.0 1.5 V IF = 14 A; -dIF/dt = 100 A/µs; VGS = 0 V; VR = 30 V - 135 690 - ns nC ISOLATION LIMITING VALUE & CHARACTERISTIC Ths = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS Visol R.M.S. isolation voltage from all three terminals to external heatsink SOT186A package; f = 50-60 Hz; sinusoidal waveform; R.H. ≤ 65%; clean and dustfree Visol Repetitive peak voltage from all three terminals to external heatsink Cisol Capacitance from pin 2 to external heatsink November 2000 MAX. UNIT - 2500 V SOT186 package; R.H. ≤ 65%; clean and dustfree - 1500 V f = 1 MHz - - pF 3 MIN. TYP. 10 Rev 1.100 Philips Semiconductors Product specification N-channel TrenchMOS transistor Normalised Power Derating PD% 120 PHX14NQ20T , PHF14NQ20T Transient thermal impedance, Zth j-a (K/W) 10 with heatsink compound 110 D = 0.5 100 90 0.2 1 80 70 0.1 60 0.05 50 0.02 0.1 40 single pulse 30 20 10 0.01 1E-06 0 0 20 40 60 80 Ths / C 100 120 140 Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tmb) 120 1E-04 1E-03 1E-02 1E-01 Pulse width, tp (s) 10V 15V 25 100 6.5V 90 6V 20 80 70 15 60 50 5.5 10 40 5V 30 5 VGS=4.5 20 10 0 0 0 20 40 60 80 Ths / C 100 120 0 140 1 2 3 4 5 6 7 8 9 10 Drain-Source Voltage, VDS (V) Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 10 V Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS); parameter VGS Drain-Source On Resistance, RDS(on) (Ohms) Peak Pulsed Drain Current, IDM (A) 1000 1E+01 Drain Current, ID (A) 30 with heatsink compound 110 1E+00 Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T Normalised Current Derating ID% 1E-05 0.8 4.5V 0.7 100 5V 0.6 RDS(on) = VDS/ ID 5.5V 0.5 tp = 10 us 0.4 10 100us 6V 6.5V 10V 0.3 1 ms D.C. 1 0.2 10 ms VGS =20 V 0.1 100 ms 0 0.1 1 10 100 Drain-Source Voltage, VDS (V) 0 1000 Fig.3. Safe operating area. Tmb = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp November 2000 10 Drain Current, ID (A) 20 Fig.6. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(ID); parameter VGS 4 Rev 1.100 Philips Semiconductors Product specification N-channel TrenchMOS transistor PHX14NQ20T , PHF14NQ20T Drain current, ID (A) 5 28 VGS(TO) / V 4.5 24 4 20 3.5 max typ 3 16 min 2.5 150 C 12 2 Tj = 25 C 1.5 8 1 4 0.5 0 0 2 4 6 Gate-source voltage, VGS (V) 8 0 -100 10 Fig.7. Typical transfer characteristics. ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj 20 -50 0 Tj / C 50 100 150 Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS Transconductance, gfs (S) Sub-Threshold Conduction 1E-01 1E-02 15 2% 1E-03 10 typ 98% 1E-04 5 1E-05 0 0 4 8 12 16 ID / (A) 20 24 28 1E-06 Fig.8. Typical transconductance, Tj = 25 ˚C. gfs = f(ID); conditions: VDS = 25 V 2.5 a 0 1 2 3 4 5 Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS Rds(on) normalised to 25 deg C Capacitances, Ciss, Coss, Crss (pF) 10000 Ciss 2 1000 Coss 1.5 100 Crss 1 10 0.5 -70 -20 30 80 Ths / deg C 0 130 20 30 40 Drain-Source Voltage, VDS (V) Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 7 A; VGS = 10 V November 2000 10 Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz 5 Rev 1.100 Philips Semiconductors Product specification N-channel TrenchMOS transistor PHX14NQ20T , PHF14NQ20T Gate-source voltage, VGS (V) Maximum Avalanche Current, IAS (A) 100 14 12 VDD = 40 V 10 25 C 10 8 6 VDD = 160 V 1 Tj prior to avalanche = 150 C 4 2 0.1 0.001 0 0 10 20 30 40 Gate charge, QG (nC) Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); conditions: ID = 14 A; parameter VDS 0.01 0.1 Avalanche time, tAV (ms) 1 10 Fig.15. Maximum permissible non-repetitive avalanche current (IAS) versus avalanche time (tAV); unclamped inductive load Source-Drain Diode Current, IF (A) 30 VGS = 0 V 20 150 C Tj = 25 C 10 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 Source-Drain Voltage, VSDS (V) Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj November 2000 6 Rev 1.100 Philips Semiconductors Product specification N-channel TrenchMOS transistor PHX14NQ20T , PHF14NQ20T MECHANICAL DATA Dimensions in mm Plastic single-ended package; isolated heatsink mounted; 1 mounting hole; 3 lead TO-220 SOT186A Net Mass: 2 g E A A1 P q D1 T D j L2 L1 K Q b1 L b2 1 2 3 b c w M e e1 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) (1) UNIT A A1 b b1 b2 c D D1 E mm 4.6 4.0 2.9 2.5 0.9 0.7 1.1 0.9 1.4 1.2 0.7 0.4 15.8 15.2 6.5 6.3 10.3 9.7 e 2.54 e1 j K 5.08 2.7 2.3 0.6 0.4 L L1 14.4 3.30 13.5 2.79 L2 max. P Q q 3 3.2 3.0 2.6 2.3 3.0 2.6 T (2) 2.5 w 0.4 Notes 1. Terminal dimensions within this zone are uncontrolled. Terminals in this zone are not tinned. 2. Both recesses are ∅ 2.5 × 0.8 max. depth OUTLINE VERSION SOT186A REFERENCES IEC JEDEC TO-220 EIAJ EUROPEAN PROJECTION ISSUE DATE 97-06-11 Fig.16. SOT186A; The seating plane is electrically isolated from all terminals. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Refer to mounting instructions for F-pack envelopes. 3. Epoxy meets UL94 V0 at 1/8". November 2000 7 Rev 1.100 Philips Semiconductors Product specification N-channel TrenchMOS transistor PHX14NQ20T , PHF14NQ20T MECHANICAL DATA Dimensions in mm Plastic single-ended package; isolated heatsink mounted; 1 mounting hole; 3 lead TO-220 exposed tabs SOT186 Net Mass: 2 g E E1 A P A1 m q D1 D L1 Q b1 L L2 1 2 3 b c w M e e1 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 b b1 c D D1 E E1 mm 4.4 4.0 2.9 2.5 0.9 0.7 1.5 1.3 0.55 0.38 17.0 16.4 7.9 7.5 10.2 9.6 5.7 5.3 e 2.54 e1 L L1(1) 5.08 14.3 13.5 4.8 4.0 L2 m P Q q w 10 0.9 0.5 3.2 3.0 1.4 1.2 4.4 4.0 0.4 Note 1. Terminal dimensions within this zone are uncontrolled. Terminals in this zone are not tinned. OUTLINE VERSION SOT186 REFERENCES IEC JEDEC TO-220 EIAJ EUROPEAN PROJECTION ISSUE DATE 97-06-11 Fig.17. SOT186; The seating plane is electrically isolated from all terminals. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Refer to mounting instructions for F-pack envelopes. 3. Epoxy meets UL94 V0 at 1/8". November 2000 8 Rev 1.100 Philips Semiconductors Product specification N-channel TrenchMOS transistor PHX14NQ20T , PHF14NQ20T DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 2000 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. November 2000 9 Rev 1.100