HEF4516B
Binary up/down counter
Rev. 06 — 11 December 2009
Product data sheet
1. General description
The HEF4516B is an edge-triggered synchronous 4-bit binary up/down counter with a
clock input (CP), an up/down count control input (UP/DN), an active LOW count enable
input (CE), an asynchronous active HIGH parallel load input (PL), four parallel inputs
(D0 to D3), four parallel outputs (Q0 to Q3), an active LOW terminal count output (TC),
and an overriding asynchronous master reset input (MR).
Information on D0 to D3 is loaded into the counter while PL is HIGH, independent of all
other input conditions except for MR which must be LOW. When PL and CE are LOW, the
counter changes on the LOW-to-HIGH transition of CP. Input UP/DN determines the
direction of the count, counting up when HIGH and counting down when LOW. When
counting up, TC is LOW when Q0 and Q3 are HIGH and CE is LOW. When counting
down, TC is LOW when Q0 to Q3 and CE are LOW. A HIGH on MR resets the counter
(Q0 to Q3 = LOW) independent of all other input conditions.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input. It is
also suitable for use over the full industrial (−40 °C to +85 °C) temperature range.
2. Features
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Operates across the full industrial temperature range −40 °C to +85 °C
Complies with JEDEC standard JESD 13-B
3. Applications
Industrial
4. Ordering information
Table 1.
Ordering information
All types operate from −40 °C to +85 °C.
Type number
Package
Name
Description
Version
HEF4516BP
DIP16
plastic dual in-line package; 16-leads (300 mil)
SOT38-4
HEF4516BT
SO16
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
HEF4516B
NXP Semiconductors
Binary up/down counter
5. Functional diagram
4
12
D0
1
15
5
10
9
PL
CP
3
D2
D3
PARALLEL LOAD CIRCUITRY
SD/CD
CE
MR
TC
UP/DOWN
COUNTER
UP/DN
7
CD
Q0
6
Fig 1.
D1
13
Q1
11
Q2
14
Q3
2
001aae667
Functional diagram
HEF4516B_6
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 06 — 11 December 2009
2 of 16
HEF4516B
NXP Semiconductors
Binary up/down counter
D1
D2
D3
D4
MR
PL
CP
UP/DN
J
SD
J
Q
FF1
CE
CD
CP
K
Q
CD
SD
J
Q
FF3
K
Q
TC
Q1
CD
SD
Q
FF4
CP
Q0
Fig 2.
J
Q
FF2
CP
K
SD
CP
K
Q
Q2
CD
Q
Q3
001aaj798
Logic diagram
HEF4516B_6
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 06 — 11 December 2009
3 of 16
HEF4516B
NXP Semiconductors
Binary up/down counter
6. Pinning information
6.1 Pinning
HEF4516B
PL
1
16 VDD
Q3
2
15 CP
D3
3
14 Q2
D0
4
13 D2
CE
5
12 D1
Q0
6
11 Q1
TC
7
10 UP/DN
VSS
8
9
MR
001aae689
Fig 3.
Pin configuration
6.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
PL
1
parallel load input (active HIGH)
D0 to D3
4, 12, 13, 3
parallel input
CE
5
count enable input (active LOW)
Q0 to Q3
6, 11, 14, 2
parallel output
VSS
8
ground supply voltage
TC
7
terminal count output (active LOW)
MR
9
master reset input
UP/DN
10
up/down count control input
CP
15
clock pulse input (LOW to HIGH, edge triggered)
VDD
16
supply voltage
HEF4516B_6
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 06 — 11 December 2009
4 of 16
HEF4516B
NXP Semiconductors
Binary up/down counter
7. Functional description
Table 3.
Function table[1]
MR
PL
UP/DN
CE
CP
MODE
L
H
X
X
X
parallel load
L
L
X
H
X
no change
L
L
L
L
↑
count down
L
L
H
L
↑
count up
H
X
X
X
X
reset
[1]
H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = positive-going transition.
CP
CE
UP/DN
MR
PL
VDD
D0
D1
VSS
D2
D3
Q0
Q1
Q2
Q3
TC
count
5
6
7
8
9
10
11
12
13
14
15
9
8
7
6
5
4
3
2
1
0
0
15 0
001aae693
Fig 4.
Timing diagram
HEF4516B_6
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 06 — 11 December 2009
5 of 16
HEF4516B
NXP Semiconductors
Binary up/down counter
0
1
2
3
4
15
5
14
6
13
7
11
12
10
count up
count down
9
8
001aae692
Logic equation for terminal count:
TC = CE • { ( UP ⁄ DN ) • Q0 • Q1 • Q2 • Q3 + ( UP ⁄ DN ) • Q0 • Q1 • Q2 • Q3 } .
Fig 5.
State diagram
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDD
supply voltage
IIK
input clamping current
VI
input voltage
IOK
output clamping current
-
±10
mA
II/O
input/output current
-
±10
mA
IDD
supply current
-
50
mA
Tstg
storage temperature
−65
+150
°C
Tamb
ambient temperature
Ptot
total power dissipation
P
power dissipation
Conditions
Min
VI < −0.5 V or VI > VDD + 0.5 V
Max
+18
V
-
±10
mA
−0.5
VO < −0.5 V or VO > VDD + 0.5 V
Unit
−0.5
VDD + 0.5
V
−40
+85
°C
DIP16 package
[1]
-
750
mW
SO16 package
[2]
-
500
mW
-
100
mW
per output
[1]
For DIP16 package: Ptot derates linearly with 12 mW/K above 70 °C.
[2]
For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C.
9. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol
Parameter
VDD
Conditions
Min
Typ
Max
Unit
supply voltage
3
-
15
V
VI
input voltage
0
-
VDD
V
Tamb
ambient temperature
−40
-
+85
°C
in free air
HEF4516B_6
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 06 — 11 December 2009
6 of 16
HEF4516B
NXP Semiconductors
Binary up/down counter
Table 5.
Recommended operating conditions …continued
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Δt/ΔV
input transition rise and fall rate
VDD = 5 V
-
-
3.75
μs/V
VDD = 10 V
-
-
0.5
μs/V
VDD = 15 V
-
-
0.08
μs/V
10. Static characteristics
Table 6.
Static characteristics
VSS = 0 V; VI = VSS or VDD unless otherwise specified.
Symbol Parameter
VIH
VIL
VOH
VOL
IOH
IOL
HIGH-level input voltage
LOW-level input voltage
Conditions
|IO| < 1 μA
5V
|IO| < 1 μA;
VI = VSS or VDD
Min
Max
Min
Max
Min
Max
3.5
-
3.5
-
3.5
-
V
7.0
-
7.0
-
7.0
-
V
11.0
-
11.0
-
11.0
-
V
5V
-
1.5
-
1.5
-
1.5
V
10 V
-
3.0
-
3.0
-
3.0
V
15 V
-
4.0
-
4.0
-
4.0
V
5V
4.95
-
4.95
-
4.95
-
V
10 V
9.95
-
9.95
-
9.95
-
V
15 V
14.95
-
14.95
-
14.95
-
V
-
0.05
-
0.05
-
0.05
V
-
0.05
-
0.05
-
0.05
V
15 V
-
0.05
-
0.05
-
0.05
V
5V
−1.7
-
−1.4
-
−1.1
-
mA
VO = 4.6 V
5V
−0.52
-
−0.44
-
−0.36
-
mA
VO = 9.5 V
10 V
−1.3
-
−1.1
-
−0.9
-
mA
VO = 13.5 V
15 V
−3.6
-
−3.0
-
−2.4
-
mA
VO = 0.4 V
5V
0.52
-
0.44
-
0.36
-
mA
VO = 0.5 V
10 V
1.3
-
1.1
-
0.9
-
mA
VO = 1.5 V
15 V
3.6
-
3.0
-
2.4
-
mA
15 V
-
±0.3
-
±0.3
-
±1.0
μA
5V
-
20
-
20
-
150
μA
10 V
-
40
-
40
-
300
μA
15 V
-
80
-
80
-
600
μA
-
-
-
-
7.5
-
-
pF
VDD = 15 V
IDD
supply current
IO = 0 A;
VI = VSS or VDD
HEF4516B_6
Product data sheet
Unit
5V
input leakage current
input capacitance
Tamb = 85 °C
10 V
II
CI
Tamb = 25 °C
15 V
HIGH-level output current VO = 2.5 V
LOW-level output current
Tamb = −40 °C
10 V
|IO| < 1 μA
HIGH-level output voltage |IO| < 1 μA;
VI = VSS or VDD
LOW-level output voltage
VDD
© NXP B.V. 2009. All rights reserved.
Rev. 06 — 11 December 2009
7 of 16
HEF4516B
NXP Semiconductors
Binary up/down counter
11. Dynamic characteristics
Table 7.
Dynamic characteristics
VSS = 0 V; Tamb = 25 °C; for test circuit see Figure 8; unless otherwise specified.
Symbol
tPHL
Parameter
HIGH to LOW
propagation delay
Conditions
CP to Qn
CP to TC
PL to Qn
PL to TC
CE to TC
MR to Qn, TC
tPLH
LOW to HIGH
propagation delay
CP to Qn
VDD
5V
PL to Qn
PL to TC
CE to TC
MR to TC
Extrapolation formula
Min
Typ
Max
Unit
118 ns + (0.55 ns/pF)CL
-
145
290
ns
10 V
49 ns + (0.23 ns/pF)CL
-
60
120
ns
15 V
37 ns + (0.16 ns/pF)CL
-
45
90
ns
5V
233 ns + (0.55 ns/pF)CL
-
260
525
ns
10 V
94 ns + (0.23 ns/pF)CL
-
105
210
ns
15 V
67 ns + (0.16 ns/pF)CL
-
75
150
ns
5V
98 ns + (0.55 ns/pF)CL
-
125
255
ns
10 V
44 ns + (0.23 ns/pF)CL
-
55
110
ns
15 V
32 ns + (0.16 ns/pF)CL
-
40
85
ns
5V
223 ns + (0.55 ns/pF)CL
-
250
500
ns
10 V
99 ns + (0.23 ns/pF)CL
-
110
220
ns
15 V
72 ns + (0.16 ns/pF)CL
-
80
160
ns
5V
138 ns + (0.55 ns/pF)CL
-
165
330
ns
10 V
54 ns + (0.23 ns/pF)CL
-
65
135
ns
15 V
42 ns + (0.16 ns/pF)CL
-
50
100
ns
5V
178 ns + (0.55 ns/pF)CL
-
205
405
ns
10 V
54 ns + (0.23 ns/pF)CL
-
65
130
ns
15 V
37 ns + (0.16 ns/pF)CL
-
45
85
ns
128 ns + (0.55 ns/pF)CL
-
155
310
ns
54 ns + (0.23 ns/pF)CL
-
65
130
ns
15 V
37 ns + (0.16 ns/pF)CL
-
45
90
ns
5V
153 ns + (0.55 ns/pF)CL
-
180
360
ns
10 V
64 ns + (0.23 ns/pF)CL
-
75
150
ns
15 V
47 ns + (0.16 ns/pF)CL
-
55
115
ns
5V
10 V
CP to TC
[1]
[1]
5V
143 ns + (0.55 ns/pF)CL
-
170
340
ns
10 V
59 ns + (0.23 ns/pF)CL
-
70
140
ns
15 V
42 ns + (0.16 ns/pF)CL
-
50
105
ns
5V
223 ns + (0.55 ns/pF)CL
-
250
500
ns
10 V
99 ns + (0.23 ns/pF)CL
-
110
220
ns
15 V
72 ns + (0.16 ns/pF)CL
-
80
160
ns
5V
118 ns + (0.55 ns/pF)CL
-
145
290
ns
10 V
49 ns + (0.23 ns/pF)CL
-
60
125
ns
15 V
37 ns + (0.16 ns/pF)CL
-
45
95
ns
5V
198 ns + (0.55 ns/pF)CL
-
225
450
ns
10 V
64 ns + (0.23 ns/pF)CL
-
75
150
ns
15 V
42 ns + (0.16 ns/pF)CL
-
50
100
ns
HEF4516B_6
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 06 — 11 December 2009
8 of 16
HEF4516B
NXP Semiconductors
Binary up/down counter
Table 7.
Dynamic characteristics …continued
VSS = 0 V; Tamb = 25 °C; for test circuit see Figure 8; unless otherwise specified.
Symbol
tt
Parameter
Conditions
VDD
transition time
5V
maximum frequency see Figure 6
fmax
pulse width
tW
recovery time
set-up time
10 ns + (1.00 ns/pF)CL
-
60
120
ns
10 V
9 ns + (0.42 ns/pF)CL
-
30
60
ns
15 V
6 ns + (0.28 ns/pF)CL
-
20
40
ns
5V
3
6
-
MHz
10 V
7
14
-
MHz
15 V
18
-
MHz
45
-
ns
10 V
35
20
-
ns
15 V
25
15
-
ns
PL input HIGH;
minimum width;
see Figure 7
5V
105
55
-
ns
10 V
45
25
-
ns
15 V
35
15
-
ns
5V
120
60
-
ns
10 V
50
25
-
ns
15 V
40
20
-
ns
5V
130
65
-
ns
10 V
45
20
-
ns
15 V
30
15
-
ns
5V
150
75
-
ns
10 V
50
25
-
ns
15 V
30
15
-
ns
MR input;
see Figure 7
Dn to PL;
see Figure 7
Dn to PL;
see Figure 7
UP/DN to CP;
see Figure 6
CE to CP;
see Figure 6
[1]
Unit
9
CE to CP;
see Figure 6
hold time
Max
95
UP/DN to CP;
see Figure 6
th
Typ
5V
PL input;
see Figure 7
tsu
Min
CP input LOW;
minimum width;
see Figure 6
MR input HIGH;
minimum width;
see Figure 7
trec
Extrapolation formula
[1]
5V
100
50
-
ns
10 V
50
25
-
ns
15 V
40
20
-
ns
5V
250
125
-
ns
10 V
100
50
-
ns
15 V
75
35
-
ns
5V
120
60
-
ns
10 V
40
20
-
ns
15 V
25
10
-
ns
5V
+10
−40
-
ns
10 V
+5
−20
-
ns
15 V
0
−20
-
ns
5V
+35
−90
-
ns
10 V
+15
−35
-
ns
15 V
+15
−25
-
ns
5V
+20
−40
-
ns
10 V
+5
−15
-
ns
15 V
+5
−10
-
ns
The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
HEF4516B_6
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 06 — 11 December 2009
9 of 16
HEF4516B
NXP Semiconductors
Binary up/down counter
Table 8.
Dynamic power dissipation PD
PD can be calculated from the formulas shown. VSS = 0 V; CL = 50 pF; tr = tf ≤ 20 ns; Tamb = 25 °C.
Symbol
Parameter
PD
dynamic power
dissipation
VDD
Typical formula for PD (μW)
Where:
5V
PD = 1000 × fi + Σ(fo × CL) × VDD2
fi = input frequency in MHz;
10 V
PD = 4500 × fi + Σ(fo × CL) × VDD2
fo = output frequency in MHz;
15 V
PD = 11200 × fi + Σ(fo × CL) ×
CL = output load capacitance in pF;
VDD2
VDD = supply voltage in V;
Σ(fo × CL) = sum of the outputs.
12. Waveforms
tW
VI
CP input
VM
VSS
tsu
VI
th
VM
CE input
VSS
tsu
VI
UP/DN input
th
tsu
th
VM
VSS
001aae672
Measurement points are given in Table 9.
Fig 6.
Waveforms showing minimum pulse width for CP, set-up and hold times for CE to CP and UP/DN to CP
VI
CP input
VM
VSS
tW
VI
VM
PL input
VSS
tsu
VI
Dn input
trec
th
VM
VSS
trec
VI
MR input
VSS
VM
tW
001aae673
Measurement points are given in Table 9.
Fig 7.
Waveforms showing PL and MR minimum pulse widths and recovery times, and Dn to PL set-up and hold
times
HEF4516B_6
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 06 — 11 December 2009
10 of 16
HEF4516B
NXP Semiconductors
Binary up/down counter
tW
VI
90 %
negative
pulse
VM
VM
10 %
0V
tf
tr
tr
tf
VI
90 %
positive
pulse
VM
VM
10 %
0V
tW
001aaj781
a. Input waveforms
VDD
VI
VO
G
DUT
RT
CL
001aag182
b. Test circuit
Test data is given in Table 9.
Definitions for test circuit:
DUT = Device Under Test
CL = Load capacitance including jig and probe capacitance;
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
Fig 8.
Test circuit for measuring switching times
Table 9.
Measurement points and test data
Supply voltage
5 V to 15 V
Input
Load
VI
VM
tr, tf
CL
VDD
0.5VI
≤ 20 ns
50 pF
HEF4516B_6
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 06 — 11 December 2009
11 of 16
HEF4516B
NXP Semiconductors
Binary up/down counter
13. Package outline
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
ME
seating plane
D
A2
A
A1
L
c
e
Z
w M
b1
(e 1)
b
b2
MH
9
16
pin 1 index
E
1
8
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
b2
c
D (1)
E (1)
e
e1
L
ME
MH
w
Z (1)
max.
mm
4.2
0.51
3.2
1.73
1.30
0.53
0.38
1.25
0.85
0.36
0.23
19.50
18.55
6.48
6.20
2.54
7.62
3.60
3.05
8.25
7.80
10.0
8.3
0.254
0.76
inches
0.17
0.02
0.13
0.068
0.051
0.021
0.015
0.049
0.033
0.014
0.009
0.77
0.73
0.26
0.24
0.1
0.3
0.14
0.12
0.32
0.31
0.39
0.33
0.01
0.03
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
ISSUE DATE
95-01-14
03-02-13
SOT38-4
Fig 9.
EUROPEAN
PROJECTION
Package outline SOT38-4 (DIP16)
HEF4516B_6
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 06 — 11 December 2009
12 of 16
HEF4516B
NXP Semiconductors
Binary up/down counter
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
HE
v M A
Z
16
9
Q
A2
(A 3)
A1
A
pin 1 index
Lp
1
L
8
e
0
detail X
w M
bp
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.01
0.019 0.0100 0.39
0.014 0.0075 0.38
0.039
0.016
0.028
0.020
inches
0.010 0.057
0.069
0.004 0.049
0.16
0.15
0.05
0.244
0.041
0.228
0.01
0.01
0.028
0.004
0.012
o
8
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT109-1
076E07
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 10. Package outline SOT109-1 (SO16)
HEF4516B_6
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 06 — 11 December 2009
13 of 16
HEF4516B
NXP Semiconductors
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14. Revision history
Table 10.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
HEF4516B_6
20091211
Product data sheet
-
HEF4516B_5
Modifications:
•
Section 9 “Recommended operating conditions” Δt/ΔV values updated.
HEF4516B_5
20090812
Product data sheet
-
HEF4516B_4
HEF4516B_4
20090312
Product data sheet
-
HEF4516B_CNV_3
HEF4516B_CNV_3
19950101
Product specification
-
HEF4516B_CNV_2
HEF4516B_CNV_2
19950101
Product specification
-
-
HEF4516B_6
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 06 — 11 December 2009
14 of 16
HEF4516B
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15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
Definition
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
HEF4516B_6
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 06 — 11 December 2009
15 of 16
HEF4516B
NXP Semiconductors
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17. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
11
12
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14
Legal information. . . . . . . . . . . . . . . . . . . . . . . 15
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Contact information. . . . . . . . . . . . . . . . . . . . . 15
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 11 December 2009
Document identifier: HEF4516B_6