INTEGRATED CIRCUITS DATA SHEET P80CL31; P80CL51 Low voltage 8-bit microcontrollers with UART Product specification Supersedes data of January 1995 File under Integrated circuits, IC20 1997 Apr 15 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART CONTENTS P80CL31; P80CL51 13.3 Baud rates 14 INTERRUPT SYSTEM External interrupts INT2 to INT9 Interrupt priority Interrupt registers 1 FEATURES 2 GENERAL DESCRIPTION 2.1 Versions: P80CL31 and P80C51 14.1 14.2 14.3 3 APPLICATIONS 15 OSCILLATOR CIRCUITRY 4 ORDERING INFORMATION 16 RESET 5 BLOCK DIAGRAM 6 FUNCTIONAL DIAGRAM 16.1 16.2 External reset using the RST pin Power-on-reset 7 PINNING INFORMATION 17 MASK OPTIONS FOR P80CL31 AND P80C51 7.1 7.2 Pinning Pin description 17.1 17.2 P80CL31: ROMless version P80C51: 5V standard version 8 FUNCTIONAL DESCRIPTION OVERVIEW 18 8.1 8.2 General CPU timing SPECIAL FUNCTION REGISTERS OVERVIEW 19 INSTRUCTION SET 9 MEMORY ORGANIZATION 20 LIMITING VALUES 9.1 9.2 9.3 9.4 Program Memory Data Memory Special Function Registers (SFRs) Addressing 21 DC CHARACTERISTICS FOR P80CL31 AND P80CL51 22 DC CHARACTERISTICS FOR P80C51 23 AC CHARACTERISTICS 10 I/O FACILITIES 24 10.1 10.2 10.3 10.4 Ports Port options Port 0 options SET/RESET options P85CL000HFZ ‘PIGGY-BACK’ SPECIFICATION 24.1 24.2 11 TIMERS/EVENT COUNTERS 12 REDUCED POWER MODES 12.1 12.2 12.3 12.4 12.5 Idle mode Power-down mode Wake-up from Power-down mode Power Control Register (PCON) Status of external pins General description Feature differences/additional features with respect to P80CL51 Common specification/feature differences between P85CL000HFZ and P83CL410/P80CL51 13 STANDARD SERIAL INTERFACE SIO0: UART 13.1 13.2 Multiprocessor communications Serial Port Control and Status Register (S0CON) 1997 Apr 15 24.3 2 25 PACKAGE OUTLINES 26 SOLDERING 26.1 26.2 26.3 Introduction DIP QFP and VSO 27 DEFINITIONS 28 LIFE SUPPORT APPLICATIONS Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART 1 FEATURES P80CL31; P80CL51 2 • Full static 80C51 Central Processing Unit GENERAL DESCRIPTION The P80CL31; P80CL51 (hereafter generally referred to as the P80CLx1) is manufactured in an advanced CMOS technology. The P80CLx1 has the same instruction set as the 80C51, consisting of over 100 instructions: 49 one-byte, 46 two-byte, and 16 three-byte. The device operates over a wide range of supply voltages and has low power consumption; there are two software selectable modes for power reduction: Idle and Power-down. For emulation purposes, the P85CL000 (piggy-back version) with 256 bytes of RAM is recommended. • 8-bit CPU, ROM, RAM, I/O in a 40-lead DIP, 40-lead VSO or 44-lead QFP package • 128 bytes on-chip RAM Data Memory • 4 kbytes on-chip ROM Program Memory for P80CL51 • External memory expandable up to 128 kbytes: RAM up to 64 kbytes and ROM up to 64 kbytes • Four 8-bit ports; 32 I/O lines • Two 16-bit Timer/Event counters This data sheet details the specific properties of the P80CL31; P80CL51. For details of the 80C51 core see “Data Handbook IC20”. • On-chip oscillator suitable for RC, LC, quartz crystal or ceramic resonator • Thirteen source, thirteen vector, nested interrupt structure with two priority levels 2.1 • Full duplex serial port (UART) Versions: P80CL31 and P80C51 The P80CL31 is the ROMless version of the P80CL51. The mask options on the P80CL31 are fixed as follows: • Enhanced architecture with: – non-page oriented instructions • All ports have option ‘1S’ (standard, HIGH after reset) – direct addressing • Oscillator option: Oscillator 3 – four 8-byte RAM register banks • Power-on-reset option: OFF. – stack depth limited only by available internal RAM (maximum 128 bytes) The P80C51 is a restricted-voltage range version of the P80CL51. The operating voltage is 5.0 V ±10%. – multiply, divide, subtract and compare instructions • Reduced power consumption through Power-down and Idle modes 3 The P80CLx1 is especially suited for real-time applications such as instrumentation, industrial control, intelligent computer peripherals and consumer products. The P80CLx1 also functions as an arithmetic processor having facilities for both binary and BCD arithmetic plus bit-handling capabilities. • Wake-up via external interrupts at Port 1 • Frequency range: 0 to 16 MHz (P80C51: 3.5 MHz min.) • Supply voltage: 1.8 to 6.0 V (P80C51: 5.0 V ±10%) • Very low current consumption • Operating ambient temperature range: −40 to +85 °C. 1997 Apr 15 APPLICATIONS 3 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART 4 P80CL31; P80CL51 ORDERING INFORMATION TYPE NUMBER(1) ROMless ROM PACKAGE NAME DESCRIPTION plastic dual in-line package; 40 leads (600 mil) VERSION P80CL31HFP P80CL51HFP DIP40 P80CL31HFT P80CL51HFT VSO40 plastic very small outline package; 40 leads SOT158-1 P80CL31HFH P80CL51HFH QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 × 10 × 1.75 mm SOT307-2 − P80C51HFP DIP40 SOT129-1 − P80C51HFT VSO40 plastic very small outline package; 40 leads SOT158-1 − P80C51HFH QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 × 10 × 1.75 mm SOT307-2 plastic dual in-line package; 40 leads (600 mil) Note 1. Refer to the Order Entry Form (OEF) for this device for the full type number, including options/program. 1997 Apr 15 4 SOT129-1 1997 Apr 15 5 internal interrupts 3 (1) Pins shared with parallel port pins. control 64 kbyte BUS EXPANSION CONTROL PROGRAM MEMORY (4K x 8 ROM) Fig.1 Block diagram. parallel ports, address/data bus and I/O pins PROGRAMMABLE I/O DATA MEMORY (128 x 8 RAM) T1 RXD (1) TXD PROGRAMMABLE SERIAL PORT FULL DUPLEX UART SYNCHRONOUS SHIFT P80CL31 P80CL51 TWO 16-BIT TIMER/EVENT COUNTERS T0 MLA556 Low voltage 8-bit microcontrollers with UART external interrupts (1) 10 CPU OSCILLATOR AND TIMING XTAL1 counter (1) 5 XTAL2 frequency reference Philips Semiconductors Product specification P80CL31; P80CL51 BLOCK DIAGRAM Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART 6 P80CL31; P80CL51 FUNCTIONAL DIAGRAM VSS VDD RST handbook, full pagewidth XTAL1 XTAL2 port 0 address and data bus port 1 INT2/INT9 port 2 address bus EA PSEN ALE P80CL31 P80CL51 RXD / data TXD / clock INT0 alternative functions INT1 port 3 T0 T1 WR RD MLA557 Fig.2 Functional diagram. 1997 Apr 15 6 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART 7 7.1 P80CL31; P80CL51 PINNING INFORMATION Pinning handbook, halfpage P1.0/INT2 1 40 V DD P1.1/INT3 2 39 P0.0/AD0 P1.2/INT4 3 38 P0.1/AD1 P1.3/INT5 4 37 P0.2/AD2 P1.4/INT6 5 36 P0.3/AD3 P1.5/INT7 6 35 P0.4/AD4 P1.6/INT8 7 34 P0.5/AD5 P1.7/INT9 8 33 P0.6/AD6 RST 9 32 P0.7/AD7 31 EA 30 ALE P3.2/INT0 12 29 PSEN P3.3/INT1 13 28 P2.7/A15 P3.4/T0 14 27 P2.6/A14 P3.5/T1 15 26 P2.5/A13 P3.6/WR 16 25 P2.4/A12 P3.7/RD 17 24 P2.3/A11 XTAL2 18 23 P2.2/A10 XTAL1 19 22 P2.1/A9 P3.0/RXD/data 10 P3.0/TXD/clock VSS 11 P80CL31 P80CL51 20 21 P2.0/A8 MLA558 Fig.3 Pin configuration for DIP40 and VSO40 packages. 1997 Apr 15 7 Philips Semiconductors Product specification 34 P0.3/AD3 35 P0.2/AD2 36 P0.1/AD1 37 P0.0/AD0 P80CL31; P80CL51 38 VDD 39 n.c. 40 P1.0/INT2 41 P1.1/INT3 42 P1.2/INT4 handbook, full pagewidth 43 P1.3/INT5 44 P1.4/INT6 Low voltage 8-bit microcontrollers with UART P1.5/INT7 1 33 P0.4/AD4 P1.6/INT8 2 32 P0.5/AD5 P1.7/INT9 3 31 P0.6/AD6 RST 4 30 P0.7/AD7 P3.0/RXD/data 5 29 EA P80CL31 P83CL51 28 n.c. P3.4/T0 10 24 P2.6/A14 P3.5/T1 11 23 P2.5/A13 P2.4/A12 22 25 P2.7/A15 P2.3/A11 21 9 P2.2/A10 20 P3.3/INT1 P2.1/A9 19 26 PSEN P2.0/A8 18 8 n.c. 17 P3.2/INT0 VSS 16 27 ALE XTAL1 15 7 XTAL2 14 P3.1/TXD/clock P3.7/RD 13 6 P3.6/WR 12 n.c. Fig.4 Pin configuration for QFP44 package. 1997 Apr 15 8 MBK034 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART 7.2 P80CL31; P80CL51 Pin description Table 1 Pin description for DIP40 (SOT190-1), VSO40 (SOT319-2) and QFP44 (SOT307-2) packages For more extensive description of the port pins see Chapter 10 “I/O facilities”. PIN SYMBOL DESCRIPTION DIP40 VSO40 QFP44 P1.0/INT2 1 40 P1.1/INT3 2 41 P1.2/INT4 3 42 P1.3/INT5 4 43 • Port 1: 8-bit bidirectional I/O port (P1.0 to P1.7). Port pins that have logic 1s written to them are pulled HIGH by internal pull-ups, and in this state can be used as inputs. As inputs, Port 1 pins that are externally pulled LOW will source current (IIL, see Chapter 21) due to the internal pull-ups. Port 1 output buffers can sink/source 4 LS TTL loads. P1.4/INT6 5 44 • Alternative functions: P1.5/INT7 6 1 P1.6/INT8 7 2 P1.7/INT9 8 3 RST 9 4 Reset: a HIGH level on this pin for two machine cycles while the oscillator is running resets the device. P3.0/RXD/data 10 5 – INT2 to INT9 are external interrupt inputs. P3.1/TXD/clock 11 7 • Port 3: 8-bit bidirectional I/O port (P3.0 to P3.7). Same characteristics as Port 1. P3.2/INT0 12 8 • Alternative functions: P3.3/INT1 13 9 P3.4/T0 14 10 P3.5/T1 15 11 P3.6/WR 16 12 P3.7/RD 17 13 – RXD/data is the serial port receiver data input (asynchronous) or data input/output (synchronous) – TXD/clock is the serial port receiver data output (asynchronous) or clock output (synchronous) – INT0 and INT1 are external interrupts 0 and 1 – T0 and T1 are external inputs for timers 0 and 1 – WR is the external Data Memory write strobe – RD is the external Data Memory read strobe. XTAL2 18 14 Crystal oscillator output: output of the inverting amplifier of the oscillator. Left open when external clock is used. XTAL1 19 15 Crystal oscillator input: input to the inverting amplifier of the oscillator, also the input for an externally generated clock source. VSS 20 16 Ground: circuit ground potential. 21 to 28 18 to 25 P2.0 to P2.7 A8 to A15 • Port 2: 8-bit bidirectional I/O port (P2.0 to P2.7) with internal pull-ups. Same characteristics as Port 1. • High-order addressing: Port 2 emits the high-order address byte (A8 to A15) during accesses to external memory that use 16-bit addresses (MOVX @DPTR). In this application it uses the strong internal pull-ups when emitting logic 1s. During accesses to external memory that use 8-bit addresses (MOVX @Ri), Port 2 emits the contents of the P2 Special Function Register. PSEN 1997 Apr 15 29 26 Program Store Enable. Output read strobe to external Program Memory. When executing code out of external Program Memory, PSEN is activated twice each machine cycle. However, during each access to external Data Memory two PSEN activations are skipped. 9 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART P80CL31; P80CL51 PIN SYMBOL DESCRIPTION DIP40 VSO40 QFP44 ALE 30 27 Address Latch Enable. Output pulse for latching the low byte of the address during access to external memory. ALE is emitted at a constant rate of 1⁄6 × fosc, and may be used for external timing or clocking purposes (assuming MOVX instructions are not used). EA 31 29 External Access. When EA is held HIGH the CPU executes out of internal program memory (unless the program counter exceeds 0FFFH). Holding EA LOW forces the CPU to execute out of external memory regardless of the value of the program counter. 32 to 39 30 to 37 • Port 0: 8-bit open-drain bidirectional I/O port. As an open-drain output port it can sink 8 LS TTL loads. Port 0 pins that have logic 1s written to them float, and in that state will function as high impedance inputs. P0.7 to P0.0 AD7 to AD0 • Low-order addressing: Port 0 is also the multiplexed low-order address and data bus during access to external memory. The strong internal pull-ups are used while emitting logic 1s within the low order address. VDD 40 n.c. − 1997 Apr 15 38 Power supply. 6, 17, 28, Not connected. 39 10 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART 8 P80CL31; P80CL51 The P80CLx1 contains 4 kbytes Program Memory (ROM; P80CL51 only); a static 128 bytes Data Memory (RAM); 32 I/O lines; two16-bit timer/event counters; a thirteen-source, two priority-level, nested interrupt structure and on-chip oscillator and timing circuit. A standard UART serial interface is also provided. FUNCTIONAL DESCRIPTION OVERVIEW This chapter gives a brief overview of the device. The detailed functional description is in the following chapters as follows: Chapter 9 “Memory organization” Chapter 10 “I/O facilities” The device has two software-selectable modes of reduced activity for power reduction: Chapter 11 “Timers/event counters” • Idle mode; freezes the CPU while allowing the timers, serial I/O and interrupt system to continue functioning. Chapter 12 “Reduced power modes” Chapter 13 “Standard serial interface SIO0: UART” • Power-down mode; saves the RAM contents but freezes the oscillator causing all other chip functions to be inoperative. Chapter 14 “Interrupt system” Chapter 15 “Oscillator circuitry” Chapter 16 “Reset”. 8.2 8.1 General A machine cycle consists of a sequence of 6 states. Each state lasts for two oscillator periods, thus a machine cycle takes 12 oscillator periods or 1 µs if the oscillator frequency (fosc) is 12 MHz. The P80CLx1 is a stand-alone high-performance CMOS microcontroller designed for use in real-time applications such as instrumentation, industrial control, intelligent computer peripherals and consumer products. The device provides hardware features, architectural enhancements and new instructions to function as a controller for applications requiring up to 64 kbytes of Program Memory and/or up to 64 kbytes of Data Memory. 1997 Apr 15 CPU timing 11 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART 9 internal ROM. Fetches from addresses 1000H to FFFFH are directed to external ROM. Program Counter values greater than 0FFFH are automatically addressed to external memory regardless of the state of the EA pin. MEMORY ORGANIZATION The P80CLx1 has 4 kbytes of Program Memory (ROM; P80CL51 only) plus 128 bytes of Data Memory (RAM) on board.The device has separate address spaces for Program and Data Memory (see Fig.5). Using Port latches P0 and P2, the P80CLx1 can address a maximum of 64 kbytes of program memory and a maximum of 64 kbytes of data memory. The CPU generates both read (RD) and write (WR) signals for external Data Memory accesses, and the read strobe (PSEN) for external Program Memory. 9.1 9.2 Data Memory The P80CLx1 contains 128 bytes of internal RAM and 25 Special Function Registers (SFR). The memory map (Fig.5) shows the internal Data Memory space divided into the lower 128, the upper 128, and the SFR space. The lower 128 bytes of the internal RAM are organized as mapped in Fig.6. The lowest 32 bytes are grouped into 4 banks of 8 registers. Program instructions refer to these registers within a register bank as R0 through R7. Two bits in the Program Status Word select which register bank is in use. The next 16 bytes above the register banks form a block of bit-addressable memory space. The 128 bits in this area can be directly addressed by the single-bit manipulation instructions. The remaining registers (30H to 7FH) are directly and indirectly byte addressable. Program Memory The P80CL51 contains 4 kbytes of internal ROM. After reset the CPU begins execution at location 0000H. The lower 4 kbytes of Program Memory can be implemented in either on-chip ROM or external Program Memory. If the EA pin is tied to VDD, then Program Memory fetches from addresses 0000H to 0FFFH are directed to the handbook, full pagewidth P80CL31; P80CL51 64K EXTERNAL 64K 4096 4095 4095 OVERLAPPED SPACE INTERNAL EXTERNAL (EA = 1) (EA = 0) 255 SPECIAL FUNCTION REGISTERS 127 INTERNAL DATA RAM 0 0 INTERNAL DATA MEMORY PROGRAM MEMORY MLA559 Fig.5 Memory map. 1997 Apr 15 12 EXTERNAL DATA MEMORY Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART P80CL31; P80CL51 7FH handbook, halfpage 30H 2FH bit-addressable space (bit addresses 0 to 7F) R7 20H 1FH R0 R7 18H 17H R0 R7 10H 0FH R0 R7 08H 07H R0 0 4 banks of 8 registers (R0 to R7) MLA560 - 1 Fig.6 The lower 128 bytes of internal RAM. 9.3 The first three methods can be used for addressing destination operands. Most instructions have a ‘destination/source’ field that specifies the data type, addressing methods and operands involved. For operations other than MOVs, the destination operand is also a source operand. Special Function Registers (SFRs) The upper 128 bytes are the address locations of the SFRs. Figure 7 shows the SFR space. The SFRs include the port latches, timers, peripheral control, serial I/O registers, etc. These registers can only be accessed by direct addressing. There are 128 directly addressable locations in the SFR address space (SFRs with addresses divisible by eight). 9.4 Access to memory addressing is as follows: • Registers in one of the four register banks through register, direct or register-indirect Addressing • Internal RAM (128 bytes) through direct or register-indirect The P8xCL410 has five methods for addressing source operands: • Special Function Registers through direct • Register • External data memory through register-indirect • Direct • Program Memory look-up tables through base-register plus index-register-indirect. • Register-indirect • Immediate • Base-register plus index-register-indirect. 1997 Apr 15 13 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART book, full pagewidth REGISTER MNEMONIC IP1 B P80CL31; P80CL51 DIRECT BYTE ADDRESS (HEX) BIT ADDRESS FF FE FD FC FB FA F9 F8 F8H F7 F5 F4 F3 F2 F1 F0 F0H F6 IX1 E9H IEN1 EF EE ED EC EB EA E9 E8 E8H ACC E7 E6 E5 E4 E3 E2 E1 E0 E0H PSW D7 D6 D5 D4 D3 D2 D1 D0 D0H IRQ1 C7 C6 C5 C4 C3 C2 C1 C0 C0H BD BC BB BA B9 B8 B8H B5 B4 B2 B1 B0 B0H AC AB AA A9 A8 A8H IP0 P3 B7 B6 AF AE AD IEN0 P2 B3 A0H A7 A6 A5 A4 A3 A2 A1 A0 S0CON 9F 9E 9D 9C 9B 9A 99 98 98H P1 97 96 95 94 93 92 91 90 90H 99H S0BUF TH1 TH0 8DH 8CH TL1 8BH TL0 8AH 89H TMOD TCON 8F 8E 8D 8C 8B 8A 89 88 88H PCON 87H DPH 83H DPL 82H 81H SP P0 SFRs containing directly addressable bits 87 86 85 84 83 82 81 80 80H MLA561 Fig.7 Special Function Register memory map. 1997 Apr 15 14 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART Option 3 Push-pull; output with drive capability in both polarities. Under this option, pins can only be used as outputs; see Fig.8(c). 10 I/O FACILITIES 10.1 P80CL31; P80CL51 Ports The P80CLx1 has 32 I/O lines treated as 32 individually addressable bits or as four parallel 8-bit addressable ports. Ports 0, 1, 2 and 3 perform the alternative functions detailed below. To enable a port pin alternate function, the port bit latch in its SFR must contain a logic 1. 10.3 Port 0 options The definition of port options for Port 0 is slightly different. Two cases are considered. First, access to external memory (EA = 0 or access above the built-in memory boundary) and second, I/O accesses. Port 0 Provides the multiplexed low-order address and data bus for expanding the device with standard memories and peripherals. 10.3.1 EXTERNAL MEMORY ACCESSES Port 1 Provides the inputs for the external interrupts INT2 to INT9. Option 1 True logic 0 and logic 1 are written as address to the external memory (strong pull-up to be used). Port 2 Provides the high-order address when expanding the device with external Program or Data Memory. Option 2 An external pull-up resistor is required for external accesses. Port 3 Pins can be configured individually to provide: Option 3 Not allowed for external memory accesses as the port can only be used as output. • External interrupt request inputs: INT1 and INT0 • Timer/counter inputs: T1 and T0 10.3.2 • Control signals to read and write to external memories: RD and WR Option 1 When writing a logic 1 to the port latch, the strong pull-up ‘p1’ will be on for 2 oscillator periods. No weak pull-up exists. Without an external pull-up, this option can be used as a high-impedance input. • UART input and output: RXD/data and TXD/clock. Each port consists of a latch (SFRs P0 to P3), an output driver and input buffer. Ports 1, 2, and 3 have internal pull-ups Figure 8(a) shows that the strong transistor ‘p1’ is turned on for only 2 oscillator periods after a LOW-to-HIGH transition in the port latch. When on, it turns on ‘p3’ (a weak pull-up) through the inverter. This inverter and ‘p3’ form a latch which holds the logic 1. In Port 0 the pull-up ‘p1’ is only on when emitting logic 1s for external memory access. Writing a logic 1 to a Port 0 bit latch leaves both output transistors switched off so that the pin can be used as a high-impedance input. 10.2 Option 2 Open-drain; quasi-directional I/O with n-channel open-drain output. Use as an output requires the connection of an external pull-up resistor. See Fig.8(b). Option 3 Push-Pull; output with drive capability in both polarities. Under this option pins can only be used as outputs. See Fig.8(c). 10.4 SET/RESET options Individual mask selection of the post-reset state is available with any of the above pins. The required selection is made by appending ‘S’ or ‘R’ to Options 1, 2, or 3 above. Port options The pins of port 1, port 2 and port 3 may be individually configured with one of the following options. These options are also shown in Fig.8. Option R RESET, at reset this pin will be initialized LOW. Option 1 Standard Port; quasi-bidirectional I/O with pull-up. The strong booster pull-up ‘p1’ is turned on for two oscillator periods after a LOW-to-HIGH transition in the port latch; Fig.8(a). Option S SET, at reset this pin will be initialized HIGH. Option 2 Open-drain; quasi-bidirectional I/O with n-channel open-drain output. Use as an output requires the connection of an external pull-up resistor; see Fig.8(b). 1997 Apr 15 I/O ACCESSES 15 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART P80CL31; P80CL51 strong pull-up handbook, full pagewidth +5 V 2 oscillator periods p2 p3 p1 I/O pin Q from port latch n input data INPUT BUFFER read port pin (a) Standard +5 V external pull-up Q from port latch I/O pin n input data read port pin INPUT BUFFER (b) Open-drain strong pull-up +5 V p1 I/O pin Q from port latch n (c) Push-pull Fig.8 Port configuration options. 1997 Apr 15 16 MGD677 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART P80CL31; P80CL51 The following functions remain active during the Idle mode: 11 TIMERS/EVENT COUNTERS The P80CLx1 contains two16-bit timer/event counter registers; Timer 0 and Timer 1, which can perform the following functions: • Timer 0 and Timer 1 • UART • Measure time intervals and pulse durations • External interrupt. • Count events These functions may generate an interrupt or reset; thus ending the Idle mode. • Generate interrupt requests. There are two ways to terminate the Idle mode: In the ‘Timer’ operating mode the register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1⁄12 × fosc. 1. Activation of any enabled interrupt will cause IDL (PCON.0) to be cleared by hardware thus terminating the Idle mode. The interrupt is serviced, and following the RETI instruction, the next instruction to be executed will be the one following the instruction that put the device in the Idle mode. The flag bits GF0 (PCON.2) and GF1 (PCON.3) may be used to determine whether the interrupt was received during normal execution or during the Idle mode. For example, the instruction that writes to PCON.0 can also set or clear one or both flag bits. When the Idle mode is terminated by an interrupt, the service routine can examine the status of the flag bits. In the ‘Counter’ operating mode, the register is incremented in response to a HIGH-to-LOW transition. Since it takes 2 machine cycles (24 oscillator periods) to recognize a HIGH-to-LOW transition, the maximum count rate is 1⁄24 × fosc. To ensure a given level is sampled, it should be held for at least one complete machine cycle. Timer 0 and Timer 1 can be programmed independently to operate in four modes: Mode 0 8-bit timer or 8-bit counter each with divide-by-32 prescaler. 2. The second way of terminating the Idle mode is with an external hardware reset. Since the oscillator is still running, the hardware reset is required to be active for two machine cycles (24 oscillator periods) to complete the reset operation. Reset redefines all SFRs but does not affect the on-chip RAM. Mode 1 16-bit time-interval or event counter. Mode 2 8-bit time-interval or event counter with automatic reload upon overflow. Mode 3 Timer 0 establishes TL0 and TH0 as two separate counters. 12.2 12 REDUCED POWER MODES Operation in Power-down mode freezes the oscillator. The internal connections which link both Idle and Power-down signals to the clock generation circuit are shown in Fig.9. There are two software selectable modes of reduced activity for further power reduction: Idle and Power-down. 12.1 Power-down mode Idle mode Idle mode operation permits the external interrupts, UART, and timer blocks to continue to function while the clock to the CPU is halted. Power-down mode is entered by setting the PD bit in the Power Control Register (PCON.1, see Table 2). The instruction that sets PD is the last executed prior to going into the Power-down mode. Idle mode is entered by setting the IDL bit in the Power Control Register (PCON.0, see Table 2). The instruction that sets IDL is the last instruction executed in the normal operating mode before the Idle mode is activated. Once in the Power-down mode, the oscillator is stopped. The contents of the on-chip RAM and the SFRs are preserved. The port pins output the value held by their respective SFRs. ALE and PSEN are held LOW. Once in Idle mode, the CPU status is preserved along with the Stack Pointer, Program Counter, Program Status Word and Accumulator. The RAM and all other registers maintain their data during Idle mode. The status of the external pins during Idle mode is shown in Table 3. In the Power-down mode, VDD may be reduced to minimize circuit power consumption. The supply voltage must not be reduced until the Power-down mode is entered, and must be restored before the hardware reset is applied which will free the oscillator. Reset should not be released until the oscillator has restarted and stabilized. 1997 Apr 15 17 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART 12.3 12.4 Wake-up from Power-down mode 12.5 Status of external pins The status of the external pins during Idle and Power-down mode is shown in Table 4. If the Power-down mode is activated whilst accessing external Program Memory, the port data that is held in the Special Function Register P2 is restored to Port 2. WAKE-UP USING INT2 TO INT9 If any of the interrupts INT2 to INT9 are enabled, the device can be woken-up from the Power-down mode with the external interrupts. To ensure that the oscillator is stable before the controller restarts, the internal clock will remain inactive for 1536 oscillator periods. This is controlled by an on-chip delay counter. 12.3.2 Power Control Register (PCON) See Tables 2 and 3. Idle and Power-down modes are activated by software using this SFR. PCON is not bit-addressable. When in Power-down mode the controller can be woken-up with either the external interrupts INT2 to INT9, or a reset operation. The wake-up operation has two basic approaches as explained in Section 12.3.1; 12.3.2 and illustrated in Fig.10. 12.3.1 P80CL31; P80CL51 If the data is a logic 1, the port pin is held HIGH during the Power-down mode by the strong pull-up transistor ‘p1’; see Fig.8(a). WAKE-UP USING RST To wake-up the P80CLx1, the RST pin must be kept HIGH for a minimum of 24 periods. The on-chip delay counter is inactive. The user must ensure that the oscillator is stable before any operation is attempted. Table 2 Power Control Register (address 87H) 7 6 5 4 3 2 1 0 SMOD − − − GF1 GF0 PD IDL Table 3 Description of PCON bits BIT SYMBOL 7 SMOD 6, 5, 4 − 3 and 2 DESCRIPTION Double Baud rate bit; see description of UART reserved GF1 and GF0 General purpose flag bits 1 PD Power-down bit; setting this bit activates the Power-down mode 0 IDL Idle mode bit; setting this bit activates the Idle mode Table 4 Status of external pins during Idle and Power-down modes MODE Idle Power-down 1997 Apr 15 MEMORY ALE PSEN PORT 0 PORT 1 PORT 2 PORT 3 PORT 4 internal 1 1 port data port data port data port data port data external 1 1 floating port data address port data port data internal 0 0 port data port data port data port data port data external 0 0 floating port data port data port data port data 18 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART P80CL31; P80CL51 handbook, full pagewidth XTAL2 XTAL1 OSCILLATOR interrupts serial ports timer blocks CLOCK GENERATOR CPU IDL PD MLA563 Fig.9 Internal clock control in Idle and Power-down mode. handbook, full pagewidth power-down RST pin external interrupt oscillator MGD679 24 periods delay counter 1536 periods Fig.10 Wake-up operation. 1997 Apr 15 19 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART In all four modes, transmission is initiated by any instruction that uses S0BUF as a destination register. Reception is initiated in Mode 0 by the condition RI = 0 and REN = 1. Reception is initiated in the other modes by the incoming start bit if REN = 1. 13 STANDARD SERIAL INTERFACE SIO0: UART This serial port is full duplex which means that it can transmit and receive simultaneously. It is also receive-buffered and can commence reception of a second byte before a previously received byte has been read from the register. (However, if the first byte has not been read by the time the reception of the second byte is complete, one of the bytes will be lost). The serial port receive and transmit registers are both accessed via the Special Function Register S0BUF. Writing to S0BUF loads the transmit register and reading S0BUF accesses a physically separate receive register. 13.1 Multiprocessor communications Modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data bits are received. The 9th bit goes into RB8. The following bit is the stop bit. The port can be programmed such that when the stop bit is received, the serial port interrupt will be activated, but only if RB8 = 1. This feature is enabled by setting bit SM2 in S0CON. One use of this feature, in multiprocessor systems, is as follows. The serial port can operate in 4 modes: Mode 0 Serial data enters and exits through RXD. TXD outputs the shift clock. Eight bits are transmitted/received (LSB first). The baud rate is fixed at 1⁄12 × fosc. When the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from a data byte in that the 9th bit is HIGH in an address byte and LOW in a data byte. With SM2 = 1, no slave will be interrupted by a data byte. An address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will be sent. The slaves that were not being addressed leave their SM2 bits set and go on about their business, ignoring the coming data bytes. Mode 1 10 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8 data bits (LSB first), and a stop bit (logic 1). On receive, the stop bit goes into RB8 in Special Function Register S0CON. The baud rate is variable. Mode 2 11 bits are transmitted (through TXD) or received (through RXD): start bit (logic 0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). On transmit, the 9th data bit (TB8 in S0CON) can be assigned the value of a logic 0 or logic 1. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. On receive, the 9th data bit goes into RB8 in S0CON, while the stop bit is ignored. The baud rate is programmable to either 1⁄32 or 1⁄64 × fosc. SM2 has no effect in Mode 0, and in Mode 1 can be used to check the validity of the stop bit. In a Mode 1 reception, if SM2 = 1, the receive interrupt will not be activated unless a valid stop bit is received. 13.2 Mode 3 11 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8 data bits (LSB first), a programmable 9th data bit and a stop bit (logic 1). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable. 1997 Apr 15 P80CL31; P80CL51 Serial Port Control and Status Register (S0CON) The Serial Port Control and Status Register is the Special Function Register S0CON. The register contains not only the mode selection bits, but also the 9th data bit for transmit and receive (TB8 and RB8), and the serial port interrupt bits (TI and RI). 20 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART Table 5 P80CL31; P80CL51 Serial Port Control Register (address 98H) 7 6 5 4 3 2 1 0 SM0 SM1 SM2 REN TB8 RB8 TI RI Table 6 Description of S0CON bits BIT SYMBOL 7 SM0 6 SM1 5 SM2 Enables the multiprocessor communication feature in Modes 2 and 3. In these modes, if SM2 = 1, then RI will not be activated if the received 9th data bit (RB8) is a logic 0. In Mode 1, if SM2 = 1, then RI will not be activated unless a valid stop bit was received. In Mode 0, SM2 should be a logic 0. 4 REN Enables serial reception and is set by software to enable reception, and cleared by software to disable reception. 3 TB8 Is the 9th data bit that will be transmitted in Modes 2 and 3; set or cleared by software as desired. 2 RB8 In Modes 2 and 3, is the 9th data bit received. In Mode 1, if SM2 = 0 then RB8 is the stop bit that was received; in Mode 0, RB8 is not used. 1 TI The transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit time in the other modes, in any serial transmission. Must be cleared by software. 0 RI The receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other modes, in any serial transmission (except see SM2). Must be cleared by software. Table 7 DESCRIPTION These bits are used to select the serial port mode; see Table 7. Selection of the serial port modes SM0 SM1 MODE DESCRIPTION 0 0 Mode 0 Shift register 0 1 Mode 1 8-bit UART 1 0 Mode 2 9-bit UART 1 1 Mode 3 9-bit UART 1997 Apr 15 21 BAUD RATE 1⁄ 12 × fosc variable 1⁄ 32 or 1⁄64 × fosc variable Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART 13.3 follows: Baud rates SMOD The baud rate in Mode 0 is fixed and may be calculated as: f osc Baud Rate = -------12 2 Baud Rate = ----------------- × Timer 1 Overflow Rate. 32 The Timer 1 interrupt should be disabled in this application. The Timer itself can be configured for either ‘timer’ or ‘counter’ operation in any of its 3 running modes. In most typical applications, it is configured for ‘timer’ operation, in the Auto-reload mode (high nibble of TMOD = 0010B). In this case the baud rate is given by the formula: The baud rate in Mode 2 depends on the value of the SMOD bit in Special Function Register PCON and may be calculated as: SMOD 2 Baud Rate = ----------------- × f osc 64 • If SMOD = 0 (value on reset), the baud rate is 1⁄64 × fosc SMOD f osc 2 Baud Rate = ----------------- × -------------------------------------------------------32 { 12 × ( 256 – TH1 ) } • If SMOD = 1, the baud rate is 1⁄32 × fosc The baud rates in Modes 1 and 3 are determined by the Timer 1 or Timer 2 overflow rate. 13.3.1 By configuring Timer 1 to run as a 16-bit timer (high nibble of TMOD = 0001B), and using the Timer 1 interrupt to do a 16-bit software reload, very low baud rates can be achieved. Table 8 lists commonly used baud rates and how they can be obtained from Timer 1. USING TIMER 1 TO GENERATE BAUD RATES When Timer 1 is used as the Baud Rate Generator, the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate and the value of the SMOD bit as Table 8 P80CL31; P80CL51 Commonly used baud rates generated by Timer 1 BAUD RATE (kbits/s) fosc (MHz) SMOD C/T TIMER 1 MODE RELOAD VALUE 1330.0(1) 16.000 X(2) X X X 500.0(3) 16.000 1 X X X 83.3(4) 16.000 1 0 Mode 2 FFH 19.2 11.059 1 0 Mode 2 FDH 9.6 11.059 0 0 Mode 2 FDH 4.8 11.059 0 0 Mode 2 FAH 2.4 11.059 0 0 Mode 2 F4H 1.2 11.059 0 0 Mode 2 E8H 137.5 11.986 0 0 Mode 2 1DH 110.0 6.000 0 0 Mode 2 72H 110.0 12.000 0 0 Mode 1 FEEBH Notes 1. Maximum in Mode 0. 2. X = don’t care. 3. Maximum in Mode 2. 4. Maximum in Modes 1 and 3. 1997 Apr 15 22 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART andbook, full pagewidth P80CL31; P80CL51 INTERNAL BUS write to SBUF D S CL Q S0 BUFFER ZERO DETECTOR START S6 RXD P3.0 ALT output function TX CONTROL TX CLOCK SHIFT SHIFT SEND T1 serial port interrupt TXD P3.1 ALT output function SHIFT CLOCK R1 RX CLOCK REN RI START RECEIVE RX CONTROL SHIFT 1 1 1 1 1 1 1 0 RXD P3.0 ALT input function INPUT SHIFT REGISTER SHIFT LOAD SBUF S0 BUFFER READ SBUF INTERNAL BUS MGC752 Fig.11 Serial port Mode 0. 1997 Apr 15 23 24 TXD (SHIFT CLOCK) SHIFT RXD (DATA IN) RECEIVE RI TSC (SHIFT CLOCK) RXD (DATA OUT) SHIFT S6P2 D0 S3P1 S6P1 S5P2 D0 WRITE TO SCON (CLEAR R1) WRITE TO SBUF D1 D1 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 MLA567 R E C E I V E T R A N S M I T Low voltage 8-bit microcontrollers with UART Fig.12 Serial port Mode 0 timing. D2 ...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 handbook, full pagewidth 1997 Apr 15 SEND ALE Philips Semiconductors Product specification P80CL31; P80CL51 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART dbook, full pagewidth P80CL31; P80CL51 INTERNAL BUS TB8 Timer 1 overflow Timer 2 overflow D S Q CL 2 0 SMOD write to SBUF TXD S0 BUFFER 1 0 1 SHIFT ZERO DETECTOR RTCLK START 16 TX CONTROL TX CLOCK SHIFT DATA SEND T1 serial port interrupt 16 sample HIGH-TO-LOW TRANSITION DETECTOR RX CLOCK START R1 RX CONTROL LOAD SBUF SHIFT INPUT SHIFT REGISTER (9-BITS) BIT DETECTOR RXD SHIFT LOAD SBUF S0 BUFFER READ SBUF INTERNAL BUS MGC755 Fig.13 Serial port Mode 1. 1997 Apr 15 25 1997 Apr 15 26 R E C E I V E RI SHIFT BIT DETECTOR SAMPLE TIME RXD RX CLOCK TI TXD SHIFT DATA START BIT S1P1 SEND WRITE TO SBUF START BIT ÷16 RESET D0 D0 D2 D1 D2 D3 D4 D3 D4 D5 D5 D6 D7 D6 D7 MLA569 STOP BIT STOP BIT T R A N S M I T Low voltage 8-bit microcontrollers with UART Fig.14 Serial port Mode 1 timing. D1 handbook, full pagewidth TX CLOCK Philips Semiconductors Product specification P80CL31; P80CL51 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART handbook, full pagewidth P80CL31; P80CL51 INTERNAL BUS TB8 write to SBUF phase 2 clock (fosc / 2) D S Q TXD S0 BUFFER CL 2 0 SHIFT 1 ZERO DETECTOR CSMOD at PCON.7 STOP BIT START 16 TX CONTROL SHIFT DATA TX CLOCK SEND T1 serial port interrupt 16 sample HIGH-TO-LOW TRANSITION DETECTOR RX CLOCK START R1 LOAD SBUF RX CONTROL SHIFT INPUT SHIFT REGISTER (9-BITS) BIT DETECTOR SHIFT RXD LOAD SBUF S0 BUFFER READ SBUF INTERNAL BUS MGC754 Fig.15 Serial port Mode 2. 1997 Apr 15 27 1997 Apr 15 R E C E I V E 28 SHIFT RI SEND START BIT S1P1 BIT DETECTOR SAMPLE TIME RXD RX CLOCK STOP BIT GEN TI TXD SHIFT DATA D0 START BIT ÷16 RESET WRITE TO SBUF D1 D1 D3 D2 D4 D3 D5 D4 D6 D5 D7 D6 TB8 D7 RB8 STOP BIT MLA571 STOP BIT T R A N S M I T Low voltage 8-bit microcontrollers with UART Fig.16 Serial port Mode 2 timing. D0 D2 handbook, full pagewidth TX CLOCK Philips Semiconductors Product specification P80CL31; P80CL51 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART handbook, full pagewidth P80CL31; P80CL51 INTERNAL BUS TB8 write to SBUF Timer 1 overflow Timer 2 overflow D S Q TXD S0 BUFFER CL 2 0 SMOD 1 SHIFT ZERO DETECTOR 0 1 RTCLK START 16 TX CONTROL TX CLOCK SHIFT DATA SEND T1 serial port interrupt 16 sample HIGH-TO-LOW TRANSITION DETECTOR RX CLOCK START R1 RX CONTROL LOAD SBUF SHIFT INPUT SHIFT REGISTER (9-BITS) BIT DETECTOR RXD SHIFT LOAD SBUF S0 BUFFER READ SBUF INTERNAL BUS MGC753 Fig.17 Serial port Mode 3. 1997 Apr 15 29 1997 Apr 15 30 R E C E I V E RI SHIFT SEND START BIT S1P1 BIT DETECTOR SAMPLE TIME RXD RX CLOCK TI TXD SHIFT DATA WRITE TO SBUF START BIT ÷16 RESET D0 D1 D1 D2 D3 D3 D4 D4 D5 D5 D6 D7 D6 TB8 D7 TB8 STOP BIT MLA573 STOP BIT T R A N S M I T Low voltage 8-bit microcontrollers with UART Fig.18 Serial port Mode 3 timing. D0 D2 handbook, full pagewidth TX CLOCK Philips Semiconductors Product specification P80CL31; P80CL51 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART P80CL31; P80CL51 14 INTERRUPT SYSTEM 14.2 External events and the real-time-driven on-chip peripherals require service by the CPU at unpredictable times. To tie the asynchronous activities of these functions to normal program execution a multiple-source, two-priority-level, nested interrupt system is provided. The system is shown in Fig.19. The P80CLx1 acknowledges interrupt requests from thirteen sources as follows: Each interrupt source can be set to either a high priority or to a low priority. If a low priority interrupt is received simultaneously with a high priority interrupt, the high priority interrupt will be dealt with first. Interrupt priority If interrupts of the same priority are requested simultaneously, the processor will branch to the interrupt polled first, according to the sequence shown in Table 9 and in Fig.19. The ‘vector address’ is the ROM location where the appropriate interrupt service routine starts. • INT0 to INT9 • Timer 0 and Timer 1 Table 9 • UART. Each interrupt vectors to a separate location in Program Memory for its service routine. Each source can be individually enabled or disabled by corresponding bits in the Interrupt Enable Registers (IEN0 and IEN1). The priority level is selected via the Interrupt Priority Registers (IP0 and IP1). All enabled sources can be globally disabled or enabled. Figure 19 shows the interrupt system. 14.1 External interrupts INT2 to INT9 Port 1 lines serve an alternative purpose as eight additional interrupts INT2 to INT9. When enabled, each of these lines may wake-up the device from the Power-down mode. Using the Interrupt Polarity Register (IX1), each pin may be initialized to be either active HIGH or active LOW. IRQ1 is the Interrupt Request Flag Register. If the interrupt is enabled, each flag will be set on an interrupt request but must be cleared by software, i.e. via the interrupt software or when the interrupt is disabled. SYMBOL VECTOR ADDRESS (HEX) X0 (first) 0003 External 0 S0 002B UART X5 0053 External 5 T0 000B Timer 0 X6 005B External 6 X1 0013 External 1 X2 003B External 2 SOURCE X7 0063 External 7 T1 001B Timer 1 X3 0043 External 3 X8 006B External 8 X4 004B External 4 X9 (last) 0073 External 9 A low priority interrupt routine can only be interrupted by a high priority interrupt. A high priority interrupt routine cannot be interrupted. Port 1 interrupts are level sensitive. A Port 1 interrupt will be recognized when a level (HIGH or LOW depending on the Interrupt Polarity Register) on P1.n is held active for at least one machine cycle. The interrupt request is not serviced until the next machine cycle. Figure 20 shows the external interrupt configuration. 1997 Apr 15 Interrupt vector polling sequence 31 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART handbook, full pagewidth INTERRUPT SOURCES IEN0/1 P80CL31; P80CL51 IP0/1 PRIORITY REGISTERS HIGH X0 LOW S0 X5 T0 INTERRUPT POLLING SEQUENCE X6 X1 X2 X7 T1 X3 X8 X4 X9 GLOBAL ENABLE Fig.19 Interrupt system. 1997 Apr 15 32 MLA574 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART P80CL31; P80CL51 IX1 handbook, full pagewidth IEN1 IRQ1 P1.7 X9 P1.6 X8 P1.5 X7 P1.4 X6 P1.3 X5 P1.2 X4 P1.1 X3 P1.0 X2 MLA575 WAKE-UP Fig.20 External interrupt configuration. 14.3 Interrupt registers The registers used in the interrupt system are listed in Table 10. Tables 11 to 22 describe the contents of these registers. Table 10 Special Function Registers related to the interrupt system ADDRESS REGISTER A8H IEN0 Interrupt Enable Register E8H IEN1 Interrupt Enable Register (INT2 to INT9) B8H IP0 Interrupt Priority Register F8H IP1 Interrupt Priority Register (INT2 to INT9 E9H IX1 Interrupt Polarity Register C0H IRQ1 1997 Apr 15 DESCRIPTION Interrupt Request Flag Register 33 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART 14.3.1 P80CL31; P80CL51 INTERRUPT ENABLE REGISTER (IEN0) Bit values: 0 = interrupt disabled; 1 = interrupt enabled. Table 11 Interrupt Enable Register (SFR address A8H) 7 6 5 4 3 2 1 0 EA − − ES0 ET1 EX1 ET0 EX0 Table 12 Description of IEN0 bits BIT SYMBOL 7 EA DESCRIPTION general enable/disable control. If EA = 0, no interrupt is enabled; if EA = 1, any individually enabled interrupt will be accepted 6 − reserved 5 − reserved 4 ES0 enable UART SIO interrupt 3 ET1 enable Timer 1 interrupt (T1) 2 EX1 enable external interrupt 1 1 ET0 enable Timer 0 interrupt (T0) 0 EX0 enable external interrupt 0 14.3.2 INTERRUPT ENABLE REGISTER (IEN1) Bit values: 0 = interrupt disabled; 1 = interrupt enabled. Table 13 Interrupt Enable Register (SFR address E8H) 7 6 5 4 3 2 1 0 EX9 EX8 EX7 EX6 EX5 EX4 EX3 EX2 Table 14 Description of IEN1 bits BIT SYMBOL 7 EX9 enable external interrupt 9 6 EX8 enable external interrupt 8 5 EX7 enable external interrupt 7 4 EX6 enable external interrupt 6 3 EX5 enable external interrupt 5 2 EX4 enable external interrupt 4 1 EX3 enable external interrupt 3 0 EX2 enable external interrupt 2 1997 Apr 15 DESCRIPTION 34 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART 14.3.3 P80CL31; P80CL51 INTERRUPT PRIORITY REGISTER (IP0) Bit values: 0 = low priority; 1 = high priority. Table 15 Interrupt Priority Register (SFR address B8H) 7 6 5 4 3 2 1 0 − − − PS0 PT1 PX1 PT0 PX0 Table 16 Description of IP0 bits BIT SYMBOL 7 − DESCRIPTION reserved 6 − reserved 5 − reserved 4 PS0 UART SIO interrupt priority level 3 PT1 Timer 1 interrupt priority level 2 PX1 external interrupt 1 priority level 1 PT0 Timer 0 interrupt priority level 0 PX0 external interrupt 0 priority level 14.3.4 INTERRUPT PRIORITY REGISTER (IP1) Bit values: 0 = low priority; 1 = high priority. Table 17 Interrupt Priority Register (SFR address F8H) 7 6 5 4 3 2 1 0 PX9 PX8 PX7 PX6 PX5 PX4 PX3 PX2 Table 18 Description of IP1 bits BIT SYMBOL 7 PX9 external interrupt 9 priority level 6 PX8 external interrupt 8 priority level 5 PX7 external interrupt 7 priority level 4 PX6 external interrupt 6 priority level 3 PX5 external interrupt 5 priority level 1997 Apr 15 DESCRIPTION 35 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART BIT SYMBOL 2 PX4 external interrupt 4 priority level 1 PX3 external interrupt 3 priority level 0 PX2 external interrupt 2 priority level 14.3.5 P80CL31; P80CL51 DESCRIPTION INTERRUPT POLARITY REGISTER (IX1) Writing either a logic 1 or logic 0 to any Interrupt Polarity Register bit sets the polarity level of the corresponding external interrupt to an active HIGH or active LOW respectively. Table 19 Interrupt Polarity Register (SFR address E9H) 7 6 5 4 3 2 1 0 IL9 IL8 IL7 IL6 IL5 IL4 IL3 IL2 Table 20 Description of IX1 bits BIT SYMBOL DESCRIPTION 7 IL9 external interrupt 9 polarity level 6 IL8 external interrupt 8 polarity level 5 IL7 external interrupt 7 polarity level 4 IL6 external interrupt 6 polarity level 3 IL5 external interrupt 5 polarity level 2 IL4 external interrupt 4 polarity level 1 IL3 external interrupt 3 polarity level 0 IL2 external interrupt 2 polarity level INTERRUPT REQUEST FLAG REGISTER (IRQ1) 14.3.6 Table 21 Interrupt Request Flag Register (SFR address C0H) 7 6 5 4 3 2 1 0 IQ9 IQ8 IQ7 IQ6 IQ5 IQ4 IQ3 IQ2 Table 22 Description of IRQ1 bits BIT SYMBOL 7 IQ9 external interrupt 9 request flag 6 IQ8 external interrupt 8 request flag 5 IQ7 external interrupt 7 request flag 4 IQ6 external interrupt 6 request flag 3 IQ5 external interrupt 5 request flag 2 IQ4 external interrupt 4 request flag 1 IQ3 external interrupt 3 request flag 0 IQ2 external interrupt 2 request flag 1997 Apr 15 DESCRIPTION 36 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART P80CL31; P80CL51 To drive the device with an external clock source, apply the external clock signal to XTAL1, and leave XTAL2 to float, as shown in Fig.21(f). There are no requirements on the duty cycle of the external clock, since the input to the internal clocking circuitry is buffered by a flip-flop. 15 OSCILLATOR CIRCUITRY The on-chip oscillator circuitry of the P80CLx1 is a single-stage inverting amplifier biased by an internal feedback resistor. The oscillator circuit is shown in Fig.22. For operation as a standard quartz oscillator, no external components are needed, except for the 32 kHz option. When using external capacitors, ceramic resonators, coils and RC networks to drive the oscillator, five different configurations are supported (see Table 23 and Fig.21). Various oscillator options are provided for optimum on-chip oscillator performance; these are specified in Table 23 and shown in Fig.21. The required option should be stated when ordering. In the Power-down mode the oscillator is stopped and XTAL1 is pulled HIGH. The oscillator inverter is switched off to ensure no current will flow regardless of the voltage at XTAL1, for configurations (a), (b), (c), (d), (e) and (g) of Fig.21. Table 23 Oscillator options OPTION APPLICATION Oscillator 1 for 32 kHz clock applications with external trimmer for frequency adjustment; a 4.7 MΩ bias resistor is needed for use in parallel with the crystal; see Fig.21(c) Oscillator 2 low-power, low-frequency operations using LC components; see Fig.21(e) Oscillator 3 medium frequency range applications Oscillator 4 high frequency range applications RC oscillator RC oscillator configuration; see Figs 21(g) and 23 QUARTZ OSCILLATOR WITH EXTERNAL CAPACITORS STANDARD QUARTZ OSCILLATOR handbook, full pagewidth XTAL1 XTAL2 XTAL1 (a) CERAMIC RESONATOR XTAL1 XTAL2 XTAL1 (b) LC - OSCILLATOR XTAL2 32 kHz OSCILLATOR XTAL1 (c) EXTERNAL CLOCK XTAL2 XTAL2 XTAL1 XTAL2 n.c. RC - OSCILLATOR XTAL1 XTAL2 n.c. VDD (d) (e) (f) Fig.21 Oscillator configurations. 1997 Apr 15 37 (g) MLA577 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART handbook, full pagewidth P80CL31; P80CL51 VDD to internal timing circuits P80CL31 P80CL51 PD VDD C1 i VDD C2 i R bias XTAL1 MLA576 XTAL2 Fig.22 Standard oscillator. MLA579 600 handbook, halfpage f osc (kHz) 400 200 0 0 2 4 RC (µs) 6 RC oscillator frequency is externally adjustable; 100 kHz ≤ fosc ≤ 500 kHz. Fig.23 RC oscillator frequency as a function of RC. 1997 Apr 15 38 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART P80CL31; P80CL51 Table 24 Oscillator type selection guide RESONATOR Quartz FREQUENCY (MHz) 0.032 OPTION (see Table 23) MIN. MAX. Oscillator 1 0 0 5 15 15 kΩ(1) 0 30 0 30 600 Ω Oscillator 2 0 15 0 15 100 Ω 0 20 0 20 75 Ω 0 10 0 10 60 Ω 0 15 0 15 60 Ω 0 10 0 10 40Ω Oscillator 3 10.0 12.0 Oscillator 4 0 15 0 15 20 Ω 0.455 40 50 40 50 10 Ω 1.0 15 50 15 50 100 Ω 16.0 PXE 0 40 0 40 10 Ω 4.0 0 40 0 40 10 Ω 6.0 0 20 0 20 5Ω 6Ω 3.58 LC RESONATOR MAX. SERIES RESISTANCE MAX. 4.0 6.0 C2 EXT. (pF) MIN. 1.0 3.58 C1 EXT. (pF) Oscillator 2 10.0 Oscillator 3 0 15 0 15 12.0 Oscillator 4 10 40 10 40 6Ω − Oscillator 2 20 90 20 90 10 µH = 1 Ω 100 µH = 5 Ω 1 mH = 75 Ω Note 1. 32 kHz quartz crystals with a series resistance >15 kΩ will reduce the guaranteed supply voltage range to 2.5 to 3.5 V. 1997 Apr 15 39 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART P80CL31; P80CL51 Rf handbook, full pagewidth XTAL1 XTAL2 C1 i V1 gm R2 C2 i MLA578 Fig.24 Oscillator equivalent circuit diagram. Table 25 Oscillator equivalent circuit parameters The equivalent circuit data of the internal oscillator compares with that of matched crystals. SYMBOL gm PARAMETER transconductance OPTION CONDITION Tamb = +25 °C; VDD = 4.5 V C2i R2 1997 Apr 15 input capacitance output capacitance output resistance TYP. MAX. UNIT − 15 − µS 200 600 1000 µS Oscillator 3 400 1500 4000 µS Oscillator 1; 32 kHz Oscillator 2 C1i MIN. Oscillator 4 1000 4000 10000 µS Oscillator 1; 32 kHz − 3.0 − pF Oscillator 2 − 8.0 − pF Oscillator 3 − 8.0 − pF Oscillator 4 − 8.0 − pF Oscillator 1; 32 kHz − 23 − pF Oscillator 2 − 8.0 − pF Oscillator 3 − 8.0 − pF Oscillator 4 − 8.0 − pF Oscillator 1; 32 kHz − 3800 − kΩ Oscillator 2 − 65 − kΩ Oscillator 3 − 18 − kΩ Oscillator 4 − 5.0 − kΩ 40 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART P80CL31; P80CL51 16 RESET 16.2 To initialize the P80CLx1 a reset is performed by either of three methods: The device contains on-chip circuitry which switches the port pins to the customer defined logic level as soon as VDD exceeds 1.3 V; if the mask option ‘ON’ has been chosen. As soon as the minimum supply voltage is reached, the oscillator will start up. However, to ensure that the oscillator is stable before the controller starts, the clock signals are gated away from the CPU for a further 1536 oscillator periods. During that time the CPU is held in a reset state. A hysteresis of approximately 50 mV at a typical power-on switching level of 1.3 V will ensure correct operation (see Fig.27). • Applying an external signal to the RST pin • Via Power-on-reset circuitry. A reset leaves the internal registers as shown in Chapter 18. The reset state of the port pins is mask-programmable and can be defined by the user. 16.1 External reset using the RST pin The reset input for the P80CLx1 is RST. A Schmitt trigger is used at the input for noise rejection. The output of the Schmitt trigger is sampled by the reset circuitry every machine cycle. A reset is accomplished by holding the RST pin HIGH for at least two machine cycles (24 oscillator periods) while the oscillator is running. The CPU responds by executing an internal reset. Port pins adopt their reset state immediately after the RST goes HIGH. During reset, ALE and PSEN are held HIGH. Power-on-reset The on-chip Power-on-reset circuitry can also be switched off via the mask option ‘OFF’. This option reduces the Power-down current to typically 800 nA and can be chosen if external reset circuitry is used. For applications not requiring the internal reset, option ‘OFF’ should be chosen. An automatic reset can be obtained by connecting the RST pin to VDD via a 10 µF capacitor. At power-on, the voltage on the RST pin is equal to VDD minus the capacitor voltage, and decreases from VDD as the capacitor charges through the internal resistor (RRST) to ground. The larger the capacitor, the more slowly VRST decreases. VRST must remain above the lower threshold of the Schmitt trigger long enough to effect a complete reset. The time required is the oscillator start-up time, plus 2 machine cycles. The Power-on-reset circuitry is shown in Fig.26. The external reset is asynchronous to the internal clock. The RST pin is sampled during state 5, phase 2 of every machine cycle. After a HIGH is detected at the RST pin, an internal reset is repeated until RST goes LOW. The internal RAM is not affected by reset. When VDD is turned on, the RAM contents are indeterminate. V DD handbook, halfpage VDD handbook, halfpage RST 10 µF SCHMITT TRIGGER P80CL31 P80CL51 RESET CIRCUITRY RST MLA580 R RST MLA582 Fig.25 Reset configuration. 1997 Apr 15 Fig.26 Recommended Power-on-reset circuitry. 41 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART P80CL31; P80CL51 switching level POR handbook, full pagewidth SUPPLY hysteresis VOLTAGE POWER-ON-RESET (INTERNAL) OSCILLATOR CPU RUNNING MLA581 Start-up time 1536 oscillator periods delay Fig.27 Power-on-reset switching level. 17 17.1 MASK OPTIONS FOR P80CL31 AND P80C51 17.2 The P80C51 is a 5 V version of the low voltage P80CL51 microcontroller. All functional features of the P80CL51 are maintained in the P80C51 with the exception of the mask options. The mask options on the P80C51 are fixed as follows: P80CL31: ROMless version The P80CL31 is a low voltage ROMless version of the P80CL51 microcontroller. The mask options for the P80CL31 are fixed as follows: • Port options: all ports have option “1S”, i.e. standard port, HIGH after reset • Port options: all ports have option “1S”, i.e. standard port, HIGH after reset • Oscillator option: Oscillator 3 • Oscillator option: Oscillator 3 • Power-on-reset option: OFF. 1997 Apr 15 P80C51: 5 V standard version • Power-on-reset option: OFF. 42 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART P80CL31; P80CL51 18 SPECIAL FUNCTION REGISTERS OVERVIEW The P80CLx1 has 25 SFRs available to the user. ADDRESS (HEX) NAME RESET VALUE (B) FUNCTION F8 IP1(1) 00000000 Interrupt Priority Register (INT2 to INT9) F0 B(1) 00000000 B Register E9 IX1 00000000 Interrupt Polarity Register E8 IEN1(1) 00000000 Interrupt Enable Register 1 E0 ACC(1) 00000000 Accumulator D0 PSW(1) 00000000 Program Status Word C0 IRQ1(1) 00000000 Interrupt Request Flag Register B8 IP0(1) X0000000 Interrupt Priority Register 0 B0 P3(1) XXXXXXXX(2) Digital I/O Port Register 3 A8 IEN0(1) 00000000 Interrupt Enable Register A0 P2(1) XXXXXXXX(2) Digital I/O Port Register 2 99 S0BUF XXXXXXXX Serial Data Buffer Register 0 98 S0CON(1) 00000000 Serial Port Control Register 0 90 P1(1) XXXXXXXX(2) 8D TH1 00000000 Timer 1 High byte 8C TH0 00000000 Timer 0 High byte 8B TL1 00000000 Timer 1 Low byte 8A TL0 00000000 Timer 0 Low byte 89 TMOD 00000000 Timer 0 and 1 Mode Control Register 88 TCON(1) 00000000 Timer 0 and 1 Control/External Interrupt Control Register 87 PCON 0XX00000 Power Control Register 83 DPH 00000000 Data Pointer High byte 82 DPL 00000000 Data Pointer Low byte 81 SP 00000111 Stack Pointer 80 P0(1) XXXXXXXX(2) Digital I/O Port Register 1 Digital I/O Port Register 0 Notes 1. Bit addressable register. 2. Port reset state determined by the customer. 1997 Apr 15 43 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART P80CL31; P80CL51 19 INSTRUCTION SET The P80CLx1 uses a powerful instruction set which permits the expansion of on-chip CPU peripherals and optimizes byte efficiency and execution speed. Assigned opcodes add new high-power operation and permit new addressing modes. The instruction set consists of 49 single-byte, 46 two-byte and 16 three-byte instructions. When using a 12 MHz oscillator, 64 instructions execute in 1 µs and 45 instructions execute in 2 µs. Multiply and divide instructions execute in 4 µs. For the description of the Data Addressing modes and Hexadecimal opcode cross-reference see Table 30. Table 26 Instruction set description: Arithmetic operations MNEMONIC DESCRIPTION BYTES CYCLES OPCODE (HEX) Arithmetic operations ADD A,Rr add register to A 1 1 2* ADD A,direct add direct byte to A 2 1 25 ADD A,@Ri add indirect RAM to A 1 1 26, 27 ADD A,#data add immediate data to A 2 1 24 ADDC A,Rr add register to A with carry flag 1 1 3* ADDC A,direct add direct byte to A with carry flag 2 1 35 ADDC A,@Ri add indirect RAM to A with carry flag 1 1 36, 37 ADDC A,#data add immediate data to A with carry flag 2 1 34 SUBB A,Rr subtract register from A with borrow 1 1 9* SUBB A,direct subtract direct byte from A with borrow 2 1 95 SUBB A,@Ri subtract indirect RAM from A with borrow 1 1 96, 97 SUBB A,#data subtract immediate data from A with borrow 2 1 94 INC A increment A 1 1 04 INC Rr increment register 1 1 0* INC direct increment direct byte 2 1 05 INC @Ri increment indirect RAM 1 1 06, 07 DEC A decrement A 1 1 14 DEC Rr decrement register 1 1 1* DEC direct decrement direct byte 2 1 15 DEC @Ri decrement indirect RAM 1 1 16, 17 INC DPTR increment data pointer 1 2 A3 MUL AB multiply A and B 1 4 A4 DIV AB divide A by B 1 4 84 DA A decimal adjust A 1 1 D4 1997 Apr 15 44 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART P80CL31; P80CL51 Table 27 Instruction set description: Logic operations MNEMONIC DESCRIPTION BYTES CYCLES 1 1 OPCODE (HEX) Logic operations ANL A,Rr AND register to A ANL A,direct AND direct byte to A 2 1 55 ANL A,@Ri AND indirect RAM to A 1 1 56, 57 ANL A,#data AND immediate data to A 2 1 54 ANL direct,A AND A to direct byte 2 1 52 ANL direct,#data AND immediate data to direct byte 3 2 53 ORL A,Rr OR register to A 1 1 4* ORL A,direct OR direct byte to A 2 1 45 ORL A,@Ri OR indirect RAM to A 1 1 46, 47 ORL A,#data OR immediate data to A 2 1 44 ORL direct,A OR A to direct byte 2 1 42 ORL direct,#data OR immediate data to direct byte 3 2 43 XRL A,Rr exclusive-OR register to A 1 1 6* XRL A,direct exclusive-OR direct byte to A 2 1 65 XRL A,@Ri exclusive-OR indirect RAM to A 1 1 66, 67 XRL A,#data exclusive-OR immediate data to A 2 1 64 XRL direct,A exclusive-OR A to direct byte 2 1 62 XRL direct,#data exclusive-OR immediate data to direct byte 3 2 63 CLR A clear A 1 1 E4 CPL A complement A 1 1 F4 RL A rotate A left 1 1 23 RLC A rotate A left through the carry flag 1 1 33 RR A rotate A right 1 1 03 RRC A rotate A right through the carry flag 1 1 13 SWAP A swap nibbles within A 1 1 C4 1997 Apr 15 45 5* Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART P80CL31; P80CL51 Table 28 Instruction set description: Data transfer MNEMONIC DESCRIPTION OPCODE (HEX) BYTES CYCLES 1 1 E* Data transfer MOV A,Rr move register to A MOV A,direct (note 1) move direct byte to A 2 1 E5 MOV A,@Ri move indirect RAM to A 1 1 E6, E7 MOV A,#data move immediate data to A 2 1 74 MOV Rr,A move A to register 1 1 F* MOV Rr,direct move direct byte to register 2 2 A* MOV Rr,#data move immediate data to register 2 1 7* MOV direct,A move A to direct byte 2 1 F5 MOV direct,Rr move register to direct byte 2 2 8* MOV direct,direct move direct byte to direct 3 2 85 MOV direct,@Ri move indirect RAM to direct byte 2 2 86, 87 MOV direct,#data move immediate data to direct byte 3 2 75 MOV @Ri,A move A to indirect RAM 1 1 F6, F7 MOV @Ri,direct move direct byte to indirect RAM 2 2 A6, A7 MOV @Ri,#data move immediate data to indirect RAM 2 1 76, 77 MOV DPTR,#data 16 load data pointer with a 16-bit constant 3 2 90 MOVC A,@A+DPTR move code byte relative to DPTR to A 1 2 93 MOVC A,@A+PC move code byte relative to PC to A 1 2 83 MOVX A,@Ri move external RAM (8-bit address) to A 1 2 E2, E3 MOVX A,@DPTR move external RAM (16-bit address) to A 1 2 E0 MOVX @Ri,A move A to external RAM (8-bit address) 1 2 F2, F3 MOVX @DPTR,A move A to external RAM (16-bit address) 1 2 F0 PUSH direct push direct byte onto stack 2 2 C0 POP direct pop direct byte from stack 2 2 D0 XCH A,Rr exchange register with A 1 1 C* XCH A,direct exchange direct byte with A 2 1 C5 XCH A,@Ri exchange indirect RAM with A 1 1 C6, C7 XCHD A,@Ri exchange LOW-order digit indirect RAM with A 1 1 D6, D7 Note 1. MOV A,ACC is not permitted. 1997 Apr 15 46 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART P80CL31; P80CL51 Table 29 Instruction set description: Boolean variable manipulation, Program and machine control MNEMONIC DESCRIPTION BYTES CYCLES OPCODE (HEX) Boolean variable manipulation CLR C clear carry flag 1 1 C3 CLR bit clear direct bit 2 1 C2 SETB C set carry flag 1 1 D3 SETB bit set direct bit 2 1 D2 CPL C complement carry flag 1 1 B3 CPL bit complement direct bit 2 1 B2 ANL C,bit AND direct bit to carry flag 2 2 82 ANL C,/bit AND complement of direct bit to carry flag 2 2 B0 ORL C,bit OR direct bit to carry flag 2 2 72 ORL C,/bit OR complement of direct bit to carry flag 2 2 A0 MOV C,bit move direct bit to carry flag 2 1 A2 MOV bit,C move carry flag to direct bit 2 2 92 Program and machine control ACALL addr11 absolute subroutine call 2 2 •1 LCALL addr16 long subroutine call 3 2 12 RET return from subroutine 1 2 22 RETI return from interrupt 1 2 32 AJMP addr11 absolute jump 2 2 ♦1 LJMP addr16 long jump 3 2 02 SJMP rel short jump (relative address) 2 2 80 JMP @A+DPTR jump indirect relative to the DPTR 1 2 73 JZ rel jump if A is zero 2 2 60 JNZ rel jump if A is not zero 2 2 70 JC rel jump if carry flag is set 2 2 40 JNC rel jump if carry flag is not set 2 2 50 JB bit,rel jump if direct bit is set 3 2 20 JNB bit,rel jump if direct bit is not set 3 2 30 JBC bit,rel jump if direct bit is set and clear bit 3 2 10 CJNE A,direct,rel compare direct to A and jump if not equal 3 2 B5 CJNE A,#data,rel compare immediate to A and jump if not equal 3 2 B4 CJNE Rr,#data,rel compare immediate to register and jump if not equal 3 2 B* CJNE @Ri,#data,rel compare immediate to indirect and jump if not equal 3 2 B6, B7 DJNZ Rr,rel decrement register and jump if not zero 2 2 D* DJNZ direct,rel decrement direct and jump if not zero 3 2 D5 no operation 1 1 00 NOP 1997 Apr 15 47 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART P80CL31; P80CL51 Table 30 Description of the mnemonics in the Instruction set MNEMONIC DESCRIPTION Data addressing modes Rr working register R0-R7 direct 128 internal RAM locations and any special function register (SFR) @Ri indirect internal RAM location addressed by register R0 or R1 of the actual register bank #data 8-bit constant included in instruction #data 16 16-bit constant included as bytes 2 and 3 of instruction bit direct addressed bit in internal RAM or SFR. addr16 16-bit destination address. Used by LCALL and LJMP; the branch will be anywhere within the 64 kbytes Program Memory address space addr11 111-bit destination address. Used by ACALL and AJMP. The branch will be within the same 2 kbytes page of Program Memory as the first byte of the following instruction rel signed (two's complement) 8-bit offset byte. Used by SJMP and all conditional jumps; range is −128 to +127 bytes relative to first byte of the following instruction Hexadecimal opcode cross-reference * 8, 9, A, B, C, D, E, F • 1, 3, 5, 7, 9, B, D, F ♦ 0, 2, 4, 6, 8, A, C, E 1997 Apr 15 48 1997 Apr 15 ACALL addr11 AJMP addr11 ACALL addr11 AJMP addr11 ACALL addr11 AJMP addr11 ACALL addr11 AJMP addr11 ACALL addr11 AJMP addr11 ACALL addr11 AJMP addr11 ACALL addr11 JNB bit,rel JC rel JNC rel JZ rel JNZ rel SJMP rel MOV DTPR,#data16 ORL C,/bit ANL C,/bit PUSH direct POP direct MOVX A,@DTPR MOVX @DTPR,A 2 3 4 5 6 7 49 8 9 A B C D E F CLR C CPL C INC DPTR MOVC A,@A+DPTR MOVC A,@A+PC JMP @A+DPTR XRL direct,#data ANL direct,#data ORL direct,#data RLC A 1. MOV A, ACC is not a valid instruction. SETB SETB bit C MOVX A,@Ri 0 1 MOVX @Ri,A 0 1 CLR bit CPL bit MOV bit,C MOV bit,C ANL C,bit ORL C,bit XRL direct,A ANL direct,A ORL direct,A RETI RET RL A RRC A DJNZ direct,rel MOV A,direct (1) MOV direct,A CLR A CPL A XCH A,direct CJNE A,direct,rel SUBB A,direct MOV direct,direct MOV direct,#data XRL A,direct ANL A,direct ORL A,direct ADDC A,direct ADD A,direct DEC direct DA A SWAP A CJNE A,#data,rel MUL AB SUBB A,#data DIV AB MOV A,#data XRL A,#data ANL A,#data ORL A,#data ADDC A,#data ADD A,#data DEC A DEC @Ri 0 1 ADD A,@Ri 0 1 ADDC A,@Ri 0 1 ORL A,@Ri 0 1 ANL A,@Ri 0 1 XRL A,@Ri 0 1 MOV @Ri,#data 0 1 MOV direct,@Ri 0 1 SUBB A,@Ri 0 1 MOV @Ri,direct 0 1 CJNE @Ri,#data,rel 0 1 XCH A,@Ri 0 1 XCHD A,@Ri 0 1 MOV A,@Ri 0 1 MOV @Ri,A 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 A B C D E INC Rr 1 2 3 4 5 6 DEC Rr 1 2 3 4 5 6 ADD A,Rr 1 2 3 4 5 6 ADDC A,Rr 1 2 3 4 5 6 ORL A,Rr 1 2 3 4 5 6 ANL A,Rr 1 2 3 4 5 6 XRL A,Rr 1 2 3 4 5 6 MOV Rr,#data 1 2 3 4 5 6 MOV direct,Rr 1 2 3 4 5 6 SUB A,Rr 1 2 3 4 5 6 MOV Rr,direct 1 2 3 4 5 6 CJNE Rr,#data,rel 1 2 3 4 5 6 XCH A,Rr 1 2 3 4 5 6 DJNZ Rr,rel 1 2 3 4 5 6 MOV A,Rr 1 2 3 4 5 6 MOV Rr,A 1 2 3 4 5 6 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 F Low voltage 8-bit microcontrollers with UART Note AJMP addr11 JB bit,rel LCALL addr16 0 8 ACALL addr11 1 7 JBC bit,rel INC @Ri 1 0 6 NOP INC direct 5 0 INC A 4 3 2 LJMP addr16 1 AJMP addr11 0 ↓ RR A ← Second hexadecimal character of opcode → First hexadecimal character of opcode Table 31 Instruction map Philips Semiconductors Product specification P80CL31; P80CL51 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART P80CL31; P80CL51 20 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER MIN. MAX. UNIT VDD supply voltage −0.5 +6.5 V VI input voltage on any pin with respect to ground (VSS) −0.5 VDD + 0.5 V II DC current on any input −5.0 +5.0 mA IO DC current on any output −5.0 +5.0 mA Ptot total power dissipation − 300 mW Tstg storage temperature −65 +150 °C Tamb operating ambient temperature −40 +85 °C Tj operating junction temperature − +125 °C 21 DC CHARACTERISTICS FOR P80CL31 AND P80CL51 VSS = 0 V; Tamb = −40 to +85 °C; all voltages with respect to VSS unless otherwise specified. SYMBOL VDD PARAMETER CONDITIONS MIN. MAX. UNIT supply voltage operating VSS = 0 V 1.8 6.0 V 1.0 − V Oscillator 1; fclk = 32 kHz; VDD = 1.8 V; Tamb = 25 °C − 50 µA Oscillator 2; fclk = 3.58 MHz; VDD = 3 V − 2.5 mA Oscillator 3; fclk = 16 MHz; VDD = 5 V − 24 mA Oscillator 4; fclk = 16 MHz; VDD = 5 V − 26 mA Oscillator 1; fclk = 32 kHz; VDD = 1.8 V; Tamb = 25 °C − 25 µA Oscillator 2; fclk = 3.58 MHz; VDD = 3 V − 1.0 mA Oscillator 3; fclk = 16 MHz; VDD = 5 V − 10 mA Oscillator 4; fclk = 16 MHz; VDD = 5 V − 12 mA − 10 µA RAM retention in Power-down mode Supply current (note 1, note 2) IDD operating supply current Supply current (Idle mode) (note 2, note 3) IDD(idle) supply current (Idle mode) Supply current (Power-down mode) (note 2, note 4) IDD(pd) 1997 Apr 15 supply current (Power-down mode) VDD = 1.8 V; Tamb = 25 °C 50 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART SYMBOL PARAMETER P80CL31; P80CL51 CONDITIONS MIN. MAX. UNIT Inputs VIL LOW level input voltage VSS VIH HIGH level input voltage 0.7VDD VDD V IIL input current logic 0 (port 1,2,3) − µA IITL input current logic 0, HIGHto-LOW transition (port 1,2,3) input leakage current (port 0, EA) ILI VDD = 5 V; VI = 0.4 V 0.3VDD V −100 VDD = 2.5 V; VI = 0.4 V − −50 µA VDD = 5 V; VI = 0.5VDD − −1.0 mA VDD = 2.5 V; VI = 0.5VDD − −500 µA VSS < VI < VDD − 10 µA VDD = 5 V; VOL = 0.4 V 1.6 − mA VDD = 2.5 V; VOL = 0.4 V 0.7 − mA VDD = 5 V; VOH = VDD − 0.4 V −1.6 − mA VDD = 2.5 V; VOH = VDD − 0.4 V −0.7 − mA 10 200 kΩ Port outputs IOL IOH RRST LOW level output current HIGH level output current (push-pull options) RST pull-down resistor Notes 1. The operating supply current is measured with all output pins disconnected; XTAL 1 driven with tr = tf = 10 ns; VIL = VSS; VIH = VDD; XTAL 2 not connected; EA = RST = Port 0 = VDD; all open drain outputs connected to VSS. 2. Circuits with Power-on-reset option ‘OFF’ are tested at VDD(min) = 1.8 V; within option ‘ON’ (typically 1.3 V) they are tested at VDD(min) = 2.3 V. Please note, option ‘ON’ is only available on P80CL51. 3. The Idle mode supply current is measured with all output pins disconnected; XTAL 1 driven with tr = tf = 10 ns; VIL = VSS. XTAL 2 not connected; EA = Port 0 = VDD; RST = VSS; all open drain outputs connected to VSS. 4. The Power-down current is measured with all output pins disconnected; XTAL 1 not connected; EA = Port 0 = VDD; RST = VSS; all open drain outputs connected to VSS. 1997 Apr 15 51 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART P80CL31; P80CL51 22 DC CHARACTERISTICS FOR P80C51 VSS = 0 V; VDD = 5.0V ±10%; fclk = 3.5 to 16 MHz; Tamb = −40 to +85 °C all voltages with respect to VSS unless otherwise specified. Note that the Power-on-reset option is ‘OFF’ and the Oscillator option is ‘Oscillator 3’. SYMBOL VDD PARAMETER CONDITIONS MIN. MAX. UNIT supply voltage operating VSS = 0 V 4.5 5.5 V 1.0 − V fclk = 16 MHz; VDD = 5.0 V; note 1 − 24 mA RAM retention in Power-down mode IDD operating supply current IDD(idle) supply current (Idle mode) fclk = 16 MHz; VDD = 5.0 V; note 2 − 10 mA IDD(pd) supply current (Power-down mode) VDD = 5.0 V; note 3 − 50 mA Inputs VIL LOW level input voltage VSS 0.3VDD V VIH HIGH level input voltage 0.7VDD VDD V IIL input current logic 0 (port 1,2,3) VI = 0.4 V − 100 µA ITL input current logic 0, HIGH- to-LOW transition (port 1,2,3) VI = 0.5VDD − 1.0 mA ILI input leakage current (port 0, EA) VSS < VI < VDD − 10 µA Port outputs IOL LOW level output current VOL = 0.4 V 1.6 − mA IOH HIGH level output current (push-pull options) VOH = VDD − 0.4 V −1.6 − mA RRST RST pull-down resistor 10 200 kΩ Notes 1. The operating supply current is measured with all output pins disconnected; XTAL 1 driven with tr = tf = 10 ns; VIL = VSS; VIH = VDD; XTAL 2 not connected; EA = RST = Port 0 = VDD; all open drain outputs connected to VSS. 2. The Idle mode supply current is measured with all output pins disconnected; XTAL 1 driven with tr = tf = 10 ns; VIL = VSS. XTAL 2 not connected; EA = Port 0 = VDD; RST = VSS; all open drain outputs connected to VSS. 3. The Power-down current is measured with all output pins disconnected; XTAL 1 not connected; EA = Port 0 = VDD; RST = VSS; all open drain outputs connected to VSS. 1997 Apr 15 52 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART P80CL31; P80CL51 MBK035 20 MBK036 20 handbook, halfpage handbook, halfpage fXTAL IDD (mA) (MHz) 16 16 12 12 8 8 4 4 16 MHz 12 MHz 8 MHz 3.58 MHz 0 0 2 4 VDD (V) 0 6 0 2 4 VDD (V) 6 Tamb = 25 °C. Fig.29 Typical operating current as a function of frequency and VDD. Fig.28 Frequency operating range. MBK046 6 MLA592 6 handbook, halfpage handbook, halfpage IDD IDD(pd) 16 MHz (µA) (idle) 4 4 12 MHz 8 MHz 2 2 3.58 MHz 0 0 0 2 4 VDD (V) 6 0 2 4 VDD (V) 6 Tamb = 25 °C. Tamb = 25 °C. Fig.30 Typical Idle current as a function of frequency and VDD. Fig.31 Typical Power-down current as a function of VDD. 1997 Apr 15 53 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART P80CL31; P80CL51 23 AC CHARACTERISTICS VDD = 5 V; VSS = 0 V; Tamb = −40 to +85 °C; CL = 50 pF for Port 0, ALE and PSEN; CL = 40 pF for all other outputs unless specified; tCLK = 1/ fCLK. SYMBOL fosc = 12 MHz PARAMETER MIN. fosc = VARIABLE MAX. MIN. UNIT MAX. Program Memory (Fig.32) tLHLL ALE pulse width 127 − 2tCLK − 40 − ns tAVLL address valid to ALE LOW 43 − tCLK − 40 − ns tLLAX address hold after ALE LOW 48 − tCLK − 35 − ns tLLIV ALE LOW to valid instruction in − 233 − 4tCLK − 100 ns tLLPL ALE LOW to PSEN LOW 58 − tCLK − 25 − ns tPLPH PSEN pulse width 215 − 3tCLK − 35 − ns tPLIV PSEN LOW to valid instruction in − 125 − 3tCLK − 125 ns tPXIX input instruction hold after PSEN 0 − 0 − ns tPXIZ input instruction float after PSEN − 63 − tCLK − 20 ns tPXAV PSEN to address valid 75 − tCLK − 8 − ns tAVIV address to valid instruction in − 302 − 5tCLK − 115 ns tPLAZ PSEN LOW to address float 12 − 0 − ns External Data Memory (Figs 33 and 34) tRLRH RD pulse width 400 − 6tCLK − 100 − ns tWLWH WR pulse width 400 − 6tCLK − 100 − ns tLLAX address hold after ALE LOW 48 − tCLK − 35 − ns tRLDV RD LOW to valid data in − 150 − 5tCLK − 165 ns tRHDZ data float after RD − 97 − 2tCLK − 70 ns tLLDV ALE LOW to valid data in − 517 8tCLK − 150 ns tAVDV address to valid data in − 585 − 9tCLK − 165 ns tLLWL ALE LOW to RD or WR LOW 200 300 3tCLK − 50 3tCLK + 50 ns tAVWL address valid to RD or WR LOW 203 − 4 − ns tWHLH RD or WR HIGH to ALE HIGH 43 123 tCLK − 40 tCLK + 40 ns tQVWX data valid to WR transition 23 − tCLK − 60 − ns tQVWH data valid time WR HIGH 433 − 7tCLK − 150 − ns tWHQX data hold after WR 33 − tCLK − 50 − ns tRLAZ RD LOW to address float − 12 − 12 ns 1997 Apr 15 54 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART P80CL31; P80CL51 t CY handbook, full pagewidth t LLIV t LHLL ALE t LLPL t PLPH PSEN t LLAX t AVLL PORT 0 t PXAV t PLIV t PXIZ A0 to A7 inst. input t PLAZ A0 to A7 inst. input t PXIX t AVIV PORT 2 address A8 to A15 address A8 to A15 MGD680 Fig.32 Read from Program Memory. t CY handbook, full pagewidth t LHLL t LLDV t WHLH ALE PSEN t LLWL t RLRH RD t AVLL t LLAX t RHDZ t RLDV t AVWL PORT 0 A0 to A7 t RHDX data input t RLAZ tAVDV PORT 2 address A8 to A15 (DPH) or Port 2 MGA177 Fig.33 Read from Data Memory. 1997 Apr 15 55 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART P80CL31; P80CL51 t CY handbook, full pagewidth t LHLL t WHLH ALE PSEN t LLWL t WLWH WR t AVWL t AVLL t LLAX t QVWH t WHQX t QVWX PORT 0 PORT 2 A0 to A7 data output address A8 to A15 (DPH) or Port 2 MGA178 Fig.34 Write to Data Memory. 1997 Apr 15 56 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART one machine cycle handbook, full pagewidth S1 P1 P2 dotted lines are valid when RD or WR are active P80CL31; P80CL51 S2 P1 P2 S3 P1 P2 S4 P1 P2 one machine cycle S5 P1 P2 S6 P1 P2 S1 P1 P2 S2 P1 P2 S3 P1 P2 S4 P1 P2 S5 P1 P2 S6 P1 P2 XTAL1 INPUT ALE only active during a read from external data memory PSEN only active during a write to external data memory RD WR external program memory fetch BUS (PORT 0) inst. in BUS (PORT 0) PORT 2 PORT 0, 2, 3 OUTPUT PORT 1 OUTPUT inst. in address A8 - A15 PORT 2 read or write of external data memory address A0 - A7 inst. in address A0 - A7 inst. in address A0 - A7 inst. in address A8 - A15 address A0 - A7 address A8 - A15 address A0 - A7 inst. in address A8 - A15 address A0 - A7 address A8 - A15 address A0 - A7 data output or data input address A8 - A15 or Port 2 output address A8 - A15 old data new data old data new data PORT 0, 2, 3 INPUT sampling time of I/O port pins during input SERIAL PORT SHIFT CLOCK (MODE 0) MGD681 Fig.35 Instruction cycle timing. 1997 Apr 15 57 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART handbook, halfpage 0.7 VDD P80CL31; P80CL51 0.7 VDD 0.9 VDD test points 0.4 VDD 0.3 VDD 0.3 VDD MLA586 Fig.36 AC testing input waveform. handbook, 4 columns −500 µA IIL(T) MGD682 0.5 VDD VDD IL −100 µA IIL Fig.37 Input current. 1997 Apr 15 58 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART P80CL31; P80CL51 24 P85CL000HFZ ‘PIGGY-BACK’ SPECIFICATION 24.2 The differences between the masked version and the piggy-back are described below. • No internal ROM 24.1 • 8-bit CPU, RAM, I/O in a single 40-lead package with DIP pin-out General description • Socket for up to 16 kbytes external EPROM The P85CL000HFZ is a piggy-back version with 256 bytes of RAM used for emulation of the P80CL51 and the P83CL410 microcontrollers. The P85CL000HFZ is manufactured in an advanced CMOS technology. The instruction set of the P85CL000HFZ is based on that of the 8051. The device has low power consumption and a wide supply voltage range. The P85CL000HFZ has two software selectable modes of reduced activity for further power reduction: Idle and Power-down. For timing and AC/DC characteristics, please refer to the P80CL51 specifications. 24.3 Feature differences/additional features with respect to P80CL51 • 256 bytes RAM, expandable externally to 64 kbytes • I2C-bus interface for serial transfer on two lines • On-chip oscillator: Oscillator 4 option only. Common specification/feature differences between P85CL000HFZ and P83CL410/P80CL51 PARAMETER P83CL410/P80CL51 P85CL000HFZ ‘PIGGY-BACK’ RAM size 128 256 ROM size 4K EPROM size dependent (max. 16K) Port options 1, 2, 3 1 Oscillator options Oscillator 1, 2, 3, 4, RC Oscillator 4 Mechanical dimensions standard dual in-line, small outline same pin-out as SOT129-1, but larger package size Current consumption IDD IDD (Oscillator 4) + IEPROM Voltage range full full, limited by EPROM ESD specification not tested (different package) 1997 Apr 15 59 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART P80CL31; P80CL51 25 PACKAGE OUTLINES seating plane DIP40: plastic dual in-line package; 40 leads (600 mil) SOT129-1 ME D A2 L A A1 c e Z w M b1 (e 1) b MH 21 40 pin 1 index E 1 20 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c mm 4.7 0.51 4.0 1.70 1.14 0.53 0.38 0.36 0.23 52.50 51.50 inches 0.19 0.020 0.16 0.067 0.045 0.021 0.015 0.014 0.009 2.067 2.028 D (1) e e1 L ME MH w Z (1) max. 14.1 13.7 2.54 15.24 3.60 3.05 15.80 15.24 17.42 15.90 0.254 2.25 0.56 0.54 0.10 0.60 0.14 0.12 0.62 0.60 0.69 0.63 0.01 0.089 E (1) Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT129-1 051G08 MO-015AJ 1997 Apr 15 EIAJ EUROPEAN PROJECTION ISSUE DATE 92-11-17 95-01-14 60 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART P80CL31; P80CL51 VSO40: plastic very small outline package; 40 leads SOT158-1 D E A X c y HE v M A Z 40 21 Q A2 A (A 3) A1 θ pin 1 index Lp L 1 detail X 20 w M bp e 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 2.70 0.3 0.1 2.45 2.25 0.25 0.42 0.30 0.22 0.14 15.6 15.2 7.6 7.5 0.762 12.3 11.8 2.25 1.7 1.5 1.15 1.05 0.2 0.1 0.1 0.6 0.3 0.012 0.096 0.017 0.0087 0.61 0.010 0.004 0.089 0.012 0.0055 0.60 0.30 0.29 0.03 0.48 0.46 0.067 0.089 0.059 inches 0.11 0.045 0.024 0.008 0.004 0.004 0.041 0.012 θ Notes 1. Plastic or metal protrusions of 0.4 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 92-11-17 95-01-24 SOT158-1 1997 Apr 15 EUROPEAN PROJECTION 61 o 7 0o Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART P80CL31; P80CL51 QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2 c y X A 33 23 34 22 ZE e Q E HE A A2 wM (A 3) A1 θ bp Lp pin 1 index L 12 44 1 detail X 11 wM bp e ZD v M A D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp Q v w y mm 2.10 0.25 0.05 1.85 1.65 0.25 0.40 0.20 0.25 0.14 10.1 9.9 10.1 9.9 0.8 12.9 12.3 12.9 12.3 1.3 0.95 0.55 0.85 0.75 0.15 0.15 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 θ Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 92-11-17 95-02-04 SOT307-2 1997 Apr 15 EUROPEAN PROJECTION 62 o 10 0o Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. 26 SOLDERING 26.1 Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). 26.2 26.2.1 26.3.2 DIP 26.3.2.1 SOLDERING BY DIPPING OR BY WAVE • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. • The footprint must be at an angle of 45° to the board direction and must incorporate solder thieves downstream and at the side corners. REPAIRING SOLDERED JOINTS Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. 26.3.1 26.3.2.2 VSO Wave soldering techniques can be used for all VSO packages if the following conditions are observed: QFP and VSO • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. REFLOW SOLDERING Reflow soldering techniques are suitable for all QFP and VSO packages. • The longitudinal axis of the package footprint must be parallel to the solder flow. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our “Quality Reference Manual” (order code 9397 750 00192). 1997 Apr 15 QFP If wave soldering cannot be avoided, the following conditions must be observed: The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 26.3 WAVE SOLDERING Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. 26.2.2 P80CL31; P80CL51 • The package footprint must incorporate solder thieves at the downstream end. 63 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART 26.3.2.3 P80CL31; P80CL51 A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Method (QFP and VSO) During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. 26.3.3 REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. 27 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 28 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1997 Apr 15 64 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART NOTES 1997 Apr 15 65 P80CL31; P80CL51 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART NOTES 1997 Apr 15 66 P80CL31; P80CL51 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART NOTES 1997 Apr 15 67 P80CL31; P80CL51 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com © Philips Electronics N.V. 1997 SCA54 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 457047/1200/03/pp68 Date of release: 1997 Apr 15 Document order number: 9397 750 01512