PHILIPS 74ABT833PWDH

INTEGRATED CIRCUITS
74ABT833
Octal transceiver with parity
generator/checker (3-State)
Product specification
IC23 Data Handbook
1993 Jun 21
Philips Semiconductors
Product specification
Octal transceiver with parity generator/checker
(3-State)
74ABT833
The 74ABT833 is an octal transceiver with a parity
generator/checker and is intended for bus-oriented applications.
FEATURES
• Low static and dynamic power dissipation with high speed and
When Output Enable A (OEA) is High, it will place the A outputs in a
high impedance state. Output Enable B (OEB) controls the B
outputs in the same way.
high output drive
• Open-collector ERROR output with flag register
• Output capability: +64mA/–32mA
• Latch-up protection exceeds 500mA per Jedec Std 17
• ESD protection exceeds 2000V per MIL STD 883 Method 3015
The parity generator creates an odd parity output (PARITY) when
OEB is Low. When OEA is Low, the parity of the B port, including
the PARITY input, is checked for odd parity. When an error is
detected, the error data is sent to the input of a storage register. If a
Low-to-High transition happens at the clock input (CP), the error
data is stored in the register and the Open-collector error flag
(ERROR) will go Low. The error flag register is cleared with a Low
pulse on the CLEAR input.
and 200 V per Machine Model
• Power up/down 3-State
• Live insertion/extraction permitted
If both OEA and OEB are Low, data will flow from the A bus to the B
bus and the part is forced into an error condition which creates an
inverted PARITY output. This error condition can be used by the
designer for system diagnostics.
DESCRIPTION
The 74ABT833 high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
QUICK REFERENCE DATA
SYMBOL
CONDITIONS
Tamb = 25°C; GND = 0V
PARAMETER
TYPICAL
UNIT
tPLH
tPHL
Propagation delay
An to Bn or Bn to An
CL = 50pF; VCC = 5V
3.4
ns
tPLH
tPHL
Propagation delay
An to PARITY
CL = 50pF; VCC = 5V
7.4
ns
CIN
Input capacitance
VI = 0V or VCC
4
pF
CI/O
I/O capacitance
Outputs disabled;
VO = 0V or VCC
7
pF
ICCZ
Total supply current
Outputs disabled; VCC =5.5V
50
µA
ORDERING INFORMATION
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
24-Pin Plastic DIP
PACKAGES
–40°C to +85°C
74ABT833 N
74ABT833 N
SOT222-1
24-Pin plastic SO
–40°C to +85°C
74ABT833 D
74ABT833 D
SOT137-1
24-Pin Plastic SSOP Type II
–40°C to +85°C
74ABT833 DB
74ABT833 DB
SOT340-1
24-Pin Plastic TSSOP Type I
–40°C to +85°C
74ABT833 PW
74ABT833PW DH
SOT355-1
PIN CONFIGURATION
OEA
PIN DESCRIPTION
1
24 V
CC
A0 2
23 B0
A1 3
22 B1
A2 4
21 B2
A3 5
20 B3
A4 6
19 B4
A5 7
18 B5
A6 8
17 B6
A7 9
16 B7
ERROR 10
15 PARITY
CLEAR 11
14 OEB
GND 12
13 CP
TOP VIEW
1993 Jun 21
SYMBOL
PIN NUMBER
NAME AND FUNCTION
A0 – A7
2, 3, 4, 5,
6, 7, 8, 9
A port 3-State inputs/outputs
B0 – B7
23, 22, 21, 20,
19, 18, 17, 16
B port 3-State inputs/outputs
OEA
1
Enables the A outputs when
Low
OEB
14
Enables the B outputs when
Low
PARITY
15
Parity output/input
ERROR
10
Error output (open collector)
CLEAR
11
Clears the error flag register
when Low
CP
13
Clock input
GND
12
Ground (0V)
VCC
24
Positive supply voltage
SA00212
2
853–1619 10087
Philips Semiconductors
Product specification
Octal transceiver with parity generator/checker
(3-State)
74ABT833
LOGIC SYMBOL
2
3
4
5
6
7
8
9
A0 A1 A2 A3 A4 A5 A6 A7
14
OEB
1
OEA
PARITY
15
11
CLEAR
ERROR
10
13
CP
B0 B1 B2 B3 B4 B5 B6 B7
23 22 21 20 19 18 17 16
SA00213
FUNCTION TABLE
INPUTS
OUTPUTS
OEB
OEA
An
Σ of Highs
Bn + Parity
Σ of Highs
An
Bn
PARITY
A data to B bus and generate odd parity
output
L
H
Odd
Even
(output)
(input)
An
L
H
B data to A bus and check for parity error1
H
L
(output)
X
Bn
(input)
(input)
H
H
X
X
Z
Z
Z
L
Odd
Even
An
H
L
MODE
A bus and B bus
disabled2
A data to B bus and generate inverted
parity output
L
(output)
(input)
NOTES:
1. Error checking is detailed in the Error Flag Function Table below.
2. When clocked, the error output is Low if the sum of A inputs is even or High if the sum of A inputs is odd.
ERROR FLAG FUNCTION TABLE
INPUTS
Internal node
Output
Point ”P”
Pre–state
ERRORn–1
ERROR
OUTPUT
CLEAR
CP
Bn + Parity
Σ of Highs
Sample
H
H
H
↑
↑
X
Odd
Even
X
H
L
X
H
X
L
H
L
L
Hold
H
↑
X
X
X
NC
L
X
X
X
X
H
MODE
Clear
H
L
X
NC
Z
↑
↑
=
=
=
=
=
=
=
High voltage level steady state
Low voltage level steady state
Don’t care
No change
High impedance ”off” state
Low-to-High clock transition
Not a Low-to-High clock transition
1993 Jun 21
3
Philips Semiconductors
Product specification
Octal transceiver with parity generator/checker
(3-State)
74ABT833
LOGIC DIAGRAM
8
8
A0 – A7
B0 – B7
8
OEB
PARITY
OEA
8
8
MUX
}
}
B
9
9–bit
Odd
Parity
Tree
”P”
A
Sel A/B
D
ERROR
CP
CLEAR
R
SA00214
ABSOLUTE MAXIMUM RATINGS1, 2
SYMBOL
VCC
IIK
PARAMETER
CONDITIONS
RATING
UNIT
–0.5 to +7.0
V
–18
mA
–1.2 to +7.0
V
VO < 0
–50
mA
output in Off or High state
–0.5 to +5.5
V
output in Low state
128
mA
–65 to 150
°C
DC supply voltage
DC input diode current
VI < 0
voltage3
VI
DC input
IOK
DC output diode current
voltage3
VOUT
DC output
IOUT
DC output current
Tstg
Storage temperature range
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1993 Jun 21
4
Philips Semiconductors
Product specification
Octal transceiver with parity generator/checker
(3-State)
74ABT833
RECOMMENDED OPERATING CONDITIONS
SYMBOL
VCC
PARAMETER
LIMITS
DC supply voltage
UNIT
Min
Max
4.5
5.5
V
0
VCC
V
VI
Input voltage
VIH
High-level input voltage
VIL
Low-level input voltage
VOH
High-level output voltage, ERROR
5.5
V
IOH
High-level output current
–32
mA
IOL
Low-level output current
64
mA
0
5
ns/V
–40
+85
°C
2.0
V
0.8
∆t/∆v
Input transition rise or fall rate
Tamb
Operating free-air temperature range
V
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Min
VIK
Input clamp voltage
VCC = 4.5V; IIK = –18mA
IOH
High-level output current
ERROR ONLY
VCC = 5.5V; VOH = 5.5V; VI = VIL or VIH
Min
UNIT
Typ
Max
–0.9
–1.2
–1.2
V
20
20
µA
Max
VCC = 4.5V; IOH = –3mA; VI = VIL or VIH
2.5
3.5
2.5
V
VCC = 5.0V; IOH = –3mA; VI = VIL or VIH
3.0
4.0
3.0
V
VCC = 4.5V; IOH = –32mA; VI = VIL or VIH
2.0
VOH
High-level output voltage
All outputs except ERROR
VOL
Low-level output voltage
VCC = 4.5V; IOL = 64mA; VI = VIL or VIH
0.42
Input leakage
Control pins
VCC = 5.5V; VI = GND or 5.5V
±0.01
current
Data pins
VCC = 5.5V; VI = GND or 5.5V
±5
II
Tamb = –40°C
to +85°C
Tamb = +25°C
2.6
2.0
0.55
V
0.55
V
±1.0
±1.0
µA
±100
±100
µA
Power-off leakage current
VCC = 0.0V; VI or VO ≤ 4.5V
±5.0
±100
±100
V
Power-up/down 3-State
output current3
VCC = 2.0V; or VO = 0.5V; VI = GND or VCC;
V OE = Don’t care
±5.0
±50
±50
V
IIH + IOZH
3-State output High current
VCC = 5.5V; VO = 2.7V; VI = VIL or VIH
5.0
50
50
µA
IIL + IOZL
3-State output Low current
VCC = 5.5V; VO = 0.5V; VI = VIL or VIH
–5.0
–50
–50
µA
Output High leakage current
VCC = 5.5V; VO = 5.5V; VI = GND or VCC
5.0
50
50
µA
–80
–180
–180
mA
VCC = 5.5V; Outputs High, VI = GND or VCC
50
250
250
µA
VCC = 5.5V; Outputs Low, VI = GND or VCC
20
30
30
mA
VCC = 5.5V; Outputs 3-State;
VI = GND or VCC
50
250
250
µA
VCC = 5.5V; one input at 3.4V,
other inputs at VCC or GND
0.3
1.5
1.5
mA
IOFF
IPUIPD
ICEX
IO
Output
current1
ICCH
ICCL
Quiescent supply current
ICCZ
∆ICC
Additional supply current per
input pin2
VCC = 5.5V; VO = 2.5V
–50
–50
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. This parameter is valid for any VCC between 0V and 2.1, with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V ± 10%, a
transition of up to 100µsec is permitted. The ERROR output pin 10 is not included in this spec due to the open collector design.
1993 Jun 21
5
Philips Semiconductors
Product specification
Octal transceiver with parity generator/checker
(3-State)
74ABT833
AC CHARACTERISTICS
GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500Ω
LIMITS
SYMBOL
PARAMETER
Tamb = +25oC
VCC = +5.0V
WAVEFORMS
Tamb = –40 to +85oC
VCC = +5.0V ±10%
UNIT
Min
Typ
Max
Min
Max
2
1.2
1.0
3.4
2.6
4.8
4.0
1.2
1.0
5.3
4.5
ns
Propagation delay
An to PARITY
1
2
2.1
2.5
7.4
7.4
9.5
9.7
2.1
2.5
11.2
11.0
ns
tPLH
tPHL
Propagation delay
OEA to PARITY
1
2
2.6
3.1
6.6
6.7
8.5
8.6
2.6
3.1
10.5
10.0
ns
tPLH
Propagation delay
CLEAR to ERROR
5
1.0
2.9
4.4
1.0
5.2
ns
tPHL
Propagation delay
CP to ERROR
1
2.5
4.2
5.7
2.5
6.2
ns
tPZH
tPZL
Output enable time
OEA to An or OEB to Bn, PARITY
3
4
1.0
2.1
3.2
4.1
5.1
5.8
1.0
2.1
6.2
6.7
ns
tPHZ
tPLZ
Output disable time
OEA to An or OEB to Bn, PARITY
3
4
3.1
3.2
5.1
5.6
7.3
7.7
3.1
3.2
7.9
8.1
ns
tPLH
tPHL
Propagation delay
An to Bn or Bn to An
tPLH
tPHL
AC SETUP REQUIREMENTS
GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500Ω
LIMITS
SYMBOL
PARAMETER
WAVEFORMS
Tamb = +25oC
VCC = +5.0V
Tamb = –40 to +85oC
VCC = +5.0V ±10%
UNIT
Min
Typ
Min
6
9.8
8.1
6.9
4.0
9.8
8.1
ns
Hold time, High or Low
Bn or PARITY to CP
6
0.0
0.0
–3.7
–6.7
0.0
0.0
ns
tw(H)
tw(L)
Pulse width, High or Low
CP
6
3.0
3.0
1.5
1.0
3.0
3.0
ns
tw(L)
Pulse width, Low
CLEAR
5
3.0
1.0
3.0
ns
Recovery time
CLEAR to CP
5
2.0
–0.3
2.0
ns
ts(H)
ts(L)
Setup time, High or Low
Bn or PARITY to CP
th(H)
th(L)
trec
1993 Jun 21
6
Philips Semiconductors
Product specification
Octal transceiver with parity generator/checker
(3-State)
74ABT833
AC WAVEFORMS
VM = 1.5V, VIN = GND to 3.0V
INPUT
VM
INPUT
VM
tPHL
tPLH
VM
OUTPUT
VM
VM
tPLH
VM
tPHL
VM
OUTPUT
VM
SA00216
SA00217
Waveform 1. Propagation Delay For Inverting Output
OEA, OEB
Waveform 2. Propagation Delay For Non-Inverting Output
VM
VM
OEA, OEB
tPHZ
tPZH
VM
VM
tPZL
tPLZ
VOH –0.3V
VM
OUTPUT
VM
OUTPUT
VOL +0.3V
0V
0V
SA00238
SA00239
Waveform 3. 3-State Output Enable Time to High Level and
Output Disable Time from High Level
CLEAR
VM
Waveform 4. 3-State Output Enable Time to Low Level and
Output Disable Time from Low Level
VM
Bn,
PARITY
tw(L)
tREC
ÉÉÉ ÉÉÉÉÉÉÉ
ÉÉÉ
ÉÉÉ ÉÉÉÉÉÉÉ
ÉÉÉ
ÉÉÉ ÉÉÉÉÉÉÉ
ÉÉÉ
VM
VM
ts(H)
VM
th(H)
ts(L)
tw(H)
VM
CP
tPLH
ERROR
VM
ÉÉÉ
ÉÉÉ
ÉÉÉ
CP
th(L)
tw(L)
VM
VM
NOTE: The shaded areas indicate when the input is permitted to change
for predictable output performance.
SA00205
NOTE: The shaded areas indicate when the input is permitted to change
for predictable output performance.
SA00240
Waveform 6. Data Setup and Hold Times and Clock Pulse Width
Waveform 5. CLEAR Pulse Width, CLEAR to ERROR Delay and
CLEAR to Clock Recovery Time
1993 Jun 21
VM
VM
7
Philips Semiconductors
Product specification
Octal transceiver with parity generator/checker
(3-State)
74ABT833
TYPICAL PROPAGATION DELAYS VERSUS LOAD FOR OPEN COLLECTOR OUTPUTS
18
16
14
Propagation delay (ns)
12
tPLH
10
8
6
4
tPHL
2
0
0
100
200
300
400
500
600
Load resistor (Ω)
NOTE:
When using Open-Collector parts, the value of the pull–up resistor greatly affects the value of the tPLH. For example, changing the specified pull-up resistor value from
500Ω to 100Ω will improve the tPLH over 300% with only a slight change in the tPHL. However, if the value of the pull-up resistor is changed, the user must make certain
that the total IOL current through the resistor and the total IIL’s of the receivers does not exceed the IOL maximum specification.
SA00241
TEST CIRCUIT AND WAVEFORM
VCC
VX
VOUT
VIN
PULSE
GENERATOR
tW
90%
90%
VM
NEGATIVE
PULSE
VM
10%
RX
10%
0V
D.U.T
tTLH (tR)
tTHL (tF)
RT
tTLH (tR)
RL
CL
tTHL (tF)
90%
POSITIVE
PULSE
Test Circuit for 3-State Outputs
AMP (V)
90%
VM
VM
10%
10%
tW
SWITCH POSITION
LOAD VALUES
TEST
SWITCH
OUTPUT
RX
tPLZ
closed
ERROR
100Ω VCC
tPZL
closed
All other
500Ω 7.0V
All other
open
AMP (V)
0V
VM = 1.5V
Input Pulse Definition
VX
INPUT PULSE REQUIREMENTS
DEFINITIONS
FAMILY
RL = Load resistor; see AC CHARACTERISTICS for value.
CL = Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
74ABT
Amplitude
Rep. Rate
tW
tR
tF
3.0V
1MHz
500ns
2.5ns
2.5ns
RT = Termination resistance should be equal to ZOUT of
pulse generators.
SA00242
1993 Jun 21
8
Philips Semiconductors
Product specification
Octal transceiver with parity generator/checker
(3-State)
DIP24: plastic dual in-line package; 24 leads (300 mil)
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
1993 Jun 21
9
74ABT833
SOT222-1
SOT137-1
SOT340-1
SOT355-1
Philips Semiconductors
Product specification
Octal transceiver with parity generator/checker
(3-State)
NOTES
1993 Jun 21
10
74ABT833
Philips Semiconductors
Product specification
Octal transceiver with parity generator/checker
(3-State)
74ABT833
DEFINITIONS
Data Sheet Identification
Product Status
Definition
Objective Specification
Formative or in Design
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
Preliminary Specification
Preproduction Product
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Product Specification
Full Production
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Philips Semiconductors and Philips Electronics North America Corporation
register eligible circuits under the Semiconductor Chip Protection Act.
 Copyright Philips Electronics North America Corporation 1995
All rights reserved. Printed in U.S.A.