PHILIPS N74F552D

INTEGRATED CIRCUITS
74F552
Octal registered transceiver with parity
and flags (3-State)
Product specification
IC15 Data Handbook
1991 Jan 02
Philips Semiconductors
Product specification
Octal registered transceiver with parity and flags (3-State)
FEATURES
74F552
PIN CONFIGURATION
• 8-bit bidirectional I/O port with handshake
• Register status flag flip-flops
• Separate clock enable and output enable
• Parity generation and parity check
• B outputs and parity output sink 64mA
B4 1
28 B3
B5
2
27 B2
B6
3
26 B1
B7
4
25 B0
OEBR
5
24 FR
CPR
6
23 PARITY
CER
7
22 GND
VCC
8
21 CES
ERROR
9
20 CPS
DESCRIPTION
The 74F522 Octal Registered Transceiver contains two 8-bit
registers for temporary storage of data flowing in either direction.
Each register has its own clock (CPR, CPS) and Clock Enable
(CER, CES) inputs, as well as a flag flip-flop that is set automatically
as the register is loaded. The flag output will be reset when the
Output Enable returns to High after reading the output port. Each
register has a separate Output Enable (OEAS, OEBR) for its 3-State
buffer. The separate Clocks, Flags and Enables provide
considerable flexibility as I/O ports for demand-response data
transfer. When data is transferred from the A port to the B port, a
parity bit is generated. On the other hand, when data is transferred
from the B port to the A port, the parity of input data on B0–B7 is
checked.
FS 10
19 OEAS
A7 11
18 A0
A6 12
17 A1
A5 13
16 A2
A4 14
15 A3
SF01039
LOGIC SYMBOL (IEEE/IEC)
XCVR
TYPE
TYPICAL fMAX
74F552
6
TYPICAL SUPPLY
CURRENT
(TOTAL)
85MHz
7
5
120mA
20
1C2
5,6
EN1’
5,6
23
EN6
6C4
21
EN3
19
EN6
6
Z7
9
6,7
10
5
14
ORDERING INFORMATION
COMMERCIAL RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C
DESCRIPTION
28-Pin Plastic DIP
(600mil)
N74F552N
28-Pin Plastic SOL
N74F552D
18
SOT117-2
SOT136-1
LOGIC SYMBOL
18
A0
6
CPR
17 16
A1 A2
15
A3
14
A4
13
A5
12
A6
A7
PARITY
CES
FS
10
20
CPS
FR
24
19
OEAS
1991 Jan 02
25
ERROR
26
17
26
16
27
15
28
14
1
13
2
12
3
11
4
23
CER
VCC = Pin 8
GND = Pin 22
25
SF01040
7
OEBR
B0 B1
1,2,6
11
21
5
3,4,6
PKG DWG #
B2
B3
B4
B5
B6
B7
27
28
1
2
3
4
9
SF01041
2
853–1098 01347
Philips Semiconductors
Product specification
Octal registered transceiver with parity and flags (3-State)
74F552
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F(U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
A0–A7
A Data inputs
3.5/1.0
70µA/0.6mA
B0–B7
B Data inputs
3.5/1.0
70µA/0.6mA
CPR
R registers clock input (active rising edge)
1.0/1.0
20µA/0.6mA
CPS
S registers clock input (active rising edge)
1.0/1.0
20µA/0.6mA
CER
R registers clock Enable input (active Low)
1.0/1.0
20µA/0.6mA
CES
S registers clock Enable input (active Low)
1.0/1.0
20µA/0.6mA
OEBR
A-to-B Output Enable input (active Low)
and clear FS output (active Low)
1.0/2.0
20µA/1.2mA
OEAS
B-to-A Output Enable input (active Low)
and clear FR output (active Low)
1.0/2.0
20µA/1.2mA
Parity bit transceiver input
3.5/1.0
70µA/0.6mA
750/106.7
15mA/64mA
PARITY
Parity bit transceiver output
ERROR
Parity check output (active Low)
50/33.3
1.0mA/20mA
A0–A7
A Data outputs
150/40
3.0mA/24mA
B0–B7
B Data outputs
750/106.7
15mA/64mA
FR
A-to-B Status Flag output (active High)
50/33.3
1.0mA/20mA
FS
B-to-A Status Flag output (active High)
50/33.3
1.0mA/20mA
NOTE: One (1.0) FAST Unit Load is defined as: 20µA in the High state and 0.6mA in the Low state.
FUNCTIONAL DESCRIPTION
R or S REGISTER FUNCTION TABLE
Data applied to the A inputs are entered and stored on the rising
edge of the CPR clock pulse, provided that the CER is Low;
simultaneously, the status flip-flop is set and the A-to-B flag (FR)
output goes High. As the CER returns to High, the data will be held
in R register. This data entered from the A inputs will appear at the B
port I/O pins after the OEBR has gone Low. When OEBR is Low, a
parity bit appears at the PARITY pin, which will be set High when
there is an even number of 1s or all 0s at the Q outputs of the R
register. After the data is assimilated, the receiving system clears
the flag FR, by changing the signal at the OEBR pin from Low to
High. Data flow from B-to-A proceeds in the same manner described
for A-to-B flow. A Low at the CES pin and a Low-to-High transition at
the CPS pin enters the B input data and the parity input data into the
S register and the parity register respectively and set the flag output
FS to High. A Low signal at the OEAS pin enables the A port I/O
pins and a Low-to-High transition of the OEAS signal clears the FS
flag. When OEAS is Low, the parity check output ERROR will be
High if there is an odd number of 1s at the Q outputs of the S
register and the parity register.
INPUTS
An or Bn
CPX
CEX
INTERNAL Q
OPERATING
MODE
X
X
H
NC
Hold data
L
H
↑
↑
L
L
L
H
Load data
NC
Keep old data
H =
L =
NC=
X =
X =
↑ =
↑ =
X
↑
L
High voltage level
Low voltage level
No change
Don’t care
R or S for CPX and CEX
Low-to-High transition
Not Low-to-High transition
OUTPUT CONTROL TABLE
INPUT
3
OUTPUTS
OEXX
INTERNAL Q
An or Bn
OPERATING
MODE
H
X
Z
Disable outputs
L
H
Enable outpus
H =
L =
X =
XX=
Z =
1991 Jan 02
OUTPUTS
L
L
L
H
High voltage level
Low voltage level
Don’t care
AS or BR
High impedance “off” state
Philips Semiconductors
Product specification
Octal registered transceiver with parity and flags (3-State)
R or S FLAG FUNCTION TABLE
INPUTS
CEX
CPX
OUTPUTS
OEXX
FR or FS
PARITY GENERATION FUNCTION TABLE
INPUTS
OPERATING
MODE
H
X
↑
NC
Hold flag
L
↑
↑
H
Set flag
L
Clear flag
X
X
↑
H = High voltage level
L = Low voltage level
NC= No change
X = Don’t care
X = R or S for CPX and CEX
XX= AS or BR
↑ = Low-to-High transition
↑ = Not Low-to-High transition
74F552
OUTPUTS
OEBR
CPR
Number of Highs
in the Q outputs
of the R register
H
X
X
H
L
X
Z
↑
L
L
=
=
=
=
=
↑
0,2,4,6,8
↑
1,3,5,7
High voltage level
Low voltage level
Don’t care
High impedance “off” state
Low-to-High transition
PARITY
OPERATING
MODE
Z
Hold flag
H
L
Load data
PARITY CHECK FUNCTION TABLE
INPUTS
H
L
X
↑
=
=
=
=
OUTPUTS
OEAS
CPS
PARITY
Number of Highs in the Q outputs
of the R register
ERROR
H
L
L
L
L
X
↑
↑
↑
↑
X
L
L
H
H
X
0,2,4,6,8
1,3,5,7
0,2,4,6,8
1,3,5,7
H
L
H
H
L
High voltage level
Low voltage level
Don’t care
Low-to-High transition
1991 Jan 02
4
OPERATING MODE
Parity check
Philips Semiconductors
Product specification
Octal registered transceiver with parity and flags (3-State)
74F552
LOGIC DIAGRAM
CES
21
CPS 20
DETAIL A
DETAIL B
CER 7
CPR 6
D
Q
CP
Q
Q
A0 18
Q
23
D
SEL
SEL
25
CP
PARITY
B0
DETAIL B
26
DETAIL A
B1
DETAIL B
A1 17
27
DETAIL A
A2
B2
D
O
SEL
SEL
CP Q
16
28
DETAIL A
B3
DETAIL B
A3 15
1
DETAIL A
B4
A4 14
2
B5
DETAIL A
A5
9
13
ERROR
DETAIL A
3
A6 12
4
DETAIL A
A7
B6
DETAIL B
B7
11
OEBR 5
D
Q
24
CP
FR
CLR Q
OEAS
19
D
Q
CP
CLR Q
VCC =
GND =
Pin 8
Pin 22
1991 Jan 02
10
FS
SF01042
5
Philips Semiconductors
Product specification
Octal registered transceiver with parity and flags (3-State)
74F552
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
PARAMETER
RATING
UNIT
–0.5 to +7.0
V
VCC
Supply voltage
VIN
Input voltage
–0.5 to +7.0
V
IIN
Input current
–30 to +VCC
mA
VOUT
Voltage applied to output in High output state
IOUT
Current applied to output in Low output state
Tamb
Operating free-air temperature range
Tstg
Storage temperature
–0.5 to +VCC
V
FR, FS, ERROR
40
mA
A0–A7
48
mA
B0–B7, PARITY
128
mA
0 to +70
°C
–65 to +150
°C
RECOMMENDED OPERATING CONDITIONS
SYMBOL
LIMITS
PARAMETER
MIN
NOM
MAX
5.0
5.5
VCC
Supply voltage
4.5
VIH
High-level input voltage
2.0
VIL
Low-level input voltage
IIK
Input clamp current
IOH
IOL
Tamb
1991 Jan 02
High-level output current
Low-level output current
Operating free-air temperature range
V
V
0.8
V
–18
mA
FR, FS, ERROR
–1
mA
A0–A7
–3
mA
B0–B7, PARITY
–15
mA
FR, FS, ERROR
20
mA
A0–A7
24
mA
B0–B7, PARITY
64
mA
70
°C
0
6
UNIT
Philips Semiconductors
Product specification
Octal registered transceiver with parity and flags (3-State)
74F552
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
SYMBOL
TEST CONDITIONSNO TAG
PARAMETER
MIN
FR FS,
FR,
FS ERROR
VOH
O
High-level
g
output
voltage
IOH
1mA
O = –1mA
VCC = MIN,
VIL = MAX
MAX,
VIH = MIN
A0 A7
A0–A7
B0 B7 PARITY
B0–B7,
IOH
3mA
O = –3mA
IOH
15mA
O = –15mA
FR FS.
FR.
FS ERROR
VOL
O
Low-level output
voltage
A0 A7
A0–A7
VIK
Input clamp voltage
II
Input current at
maximum input
voltage
IIH
High-level input
current
IIL
Low-level input
current
IOZH+IIH
Off-state output current
High-level voltage applied
IOZL+IIL
Off-state output current
Low-level voltage applied
IOS
Short-circuit
output
currentNO TAG
Supply current
(total)
±5%VCC
2.7
±10%VCC
2.4
±5%VCC
2.7
±10%VCC
2.0
V
±5%VCC
2.0
V
3.4
V
V
3.3
V
0.50
V
±5%VCC
0.30
0.50
V
±10%VCC
0.35
0.50
V
±5%VCC
0.35
0.50
V
IOL = 48mA
±10%VCC
0.38
0.55
V
IOL = 64mA
±5%VCC
0.42
0.55
V
–0.73
–1.2
V
VCC = MIN, II = IIK
others
VCC = MAX, VI = 7.0V
100
µA
A0–A7, B0–B7,
PARITY
VCC = 5.5V, VI = 5.5V
1
mA
VCC = MAX, VI = 2.7V
20
µA
–0.6
mA
–1.2
mA
VCC = MAX, VO = 2.7V
70
µA
VCC = MAX, VO = 0.5V
–600
µA
–60
–150
mA
–100
–225
mA
others except
A0–A7, B0–B7,
PARITY
others
OEAS, OEBA
A0–A7,
B0–B7
B0–B7,
PARITY
A0–A7, FS, FR,
ERROR
VCC = MAX,
MAX VI = 0
0.5V
5V
VCC = MAX
B0–B7, PARITY
ICCH
ICC
V
0.30
IOL
O = 24mA
B0 B7 PARITY
B0–B7,
2.5
UNIT
MAX
±10%VCC
IOL
O = 20mA
VCC = MIN,
VIL = MAX,
MAX
VIH = MIN
±10%VCC
TYP
NO TAG
ICCL
VCC = MAX
ICCZ
115
170
mA
125
185
mA
120
180
mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value under the recommended operating conditions for the applicable type.
2. All typical values are at VCC = 5V, Tamb = 25°C.
3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, IOS should be performed last.
1991 Jan 02
7
Philips Semiconductors
Product specification
Octal registered transceiver with parity and flags (3-State)
74F552
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
Tamb = +25°C
VCC = +5.0V
CL = 50pF, RL = 500Ω
TEST
CONDITIONS
MAX
Tamb = 0°C to +70°C
VCC = +5.0V ± 10%
CL = 50pF, RL = 500Ω
MIN
UNIT
MIN
TYP
fMAX
Maximum Clock Frequency
Waveform 1
70
85
MAX
tPLH
tPHL
Propagation delay
CPS to An or CPR to Bn
Waveform 1
3.5
4.0
5.0
6.0
8.0
9.0
3.0
3.5
8.5
9.0
ns
ns
tPLH
Propagation delay
CPS to FS or CPR to FR
Waveform 1
3.0
5.0
7.5
2.5
8.5
ns
tPHL
Propagation delay
OEAS to FS or OEBR to FR
Waveform 2
4.0
6.0
8.5
3.5
9.0
ns
tPLH
tPHL
Propagation delay
CPS to ERROR
Waveform 4
6.5
7.5
13.0
11.5
16.5
15.0
6.0
7.0
18.0
16.0
ns
ns
tPLH
tPHL
Propagation delay
CPR to PARITY
Waveform 4
6.5
10.5
8.5
13.5
11.0
17.0
5.5
10.0
12.5
18.0
ns
ns
tPLH
tPHL
Propagation delay
OEAS to ERROR
Waveform
NO TAG
3.5
3.0
5.5
5.0
8.0
7.0
3.0
2.5
8.5
8.0
ns
ns
tPZH
tPZL
Output Enable time
OEAS to An or OEBR to Bn
Waveform
NO TAG
Waveform
NO TAG
2.5
4.0
4.0
6.5
7.0
9.5
2.0
4.0
8.0
10.5
ns
ns
tPHZ
tPLZ
Output Disable time
OEAS to An or OEBR to Bn
Waveform
NO TAG
Waveform
NO TAG
2.0
2.0
4.0
3.5
7.0
7.0
1.5
1.5
8.5
7.5
ns
ns
tPZH
tPZL
Output Enable time
OEBR to PARITY
Waveform
NO TAG
Waveform
NO TAG
2.0
4.0
4.0
5.5
7.0
8.0
2.0
3.0
7.5
9.0
ns
ns
tPHZ
tPLZ
Output Disable time
OEBR to PARITY
Waveform
NO TAG
Waveform
NO TAG
2.0
2.0
4.0
4.0
7.0
7.5
2.0
2.0
7.5
8.0
ns
ns
60
MHz
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
Tamb = +25°C
VCC = +5.0V
CL = 50pF, RL = 500Ω
TEST
CONDITIONS
MIN
TYP
MAX
Tamb = 0°C to +70°C
VCC = +5.0V ± 10%
CL = 50pF, RL = 500Ω
MIN
UNIT
MAX
ts(H)
ts(L)
Setup time, High or Low
An or Bn or PARITY to CPS or CPR
Waveform 5
7.5
4.5
8.5
5.5
ns
th(H)
th(L)
Hold time, High or Low
An or Bn or PARITY to CPS or CPR
Waveform 5
0
0
0
0
ns
ts(H)
ts(L)
Setup time, High or Low
CES to CPS or CER to CPR
Waveform 5
7.0
7.0
7.5
7.5
ns
th(H)
th(L)
Hold time, High or Low
CES to CPS or CER to CPR
Waveform 5
0
0
0
0
ns
tw(H)
tw(L)
CPS or CPR Pulse width,
High or Low
Waveform 1
5.0
6.5
6.5
7.5
ns
tREC
Recovery time OEBR to CPR
or OEAS to CPS
Waveform 6
14.5
16.5
ns
1991 Jan 02
8
Philips Semiconductors
Product specification
Octal registered transceiver with parity and flags (3-State)
74F552
AC WAVEFORMS
For all waveforms, VM = 1.5V.
The shaded areas indicate when the input is permitted ot change for predictable output.
1/fMAX
tW(H)
CPS,
CPR
VM
OEAS, OEBR
VM
VM
tW(L)
tPHL
tPLH
tPHL
An, Bn
FS, FR
FS, FR
VM
VM
VM
SF01043
SF01044
Waveform 2. Propagation Delay, Output Enable to Flag Output
Waveform 1. Propagation Delay, Clock Input to Output and
Maximum Clock Frequency
OEAS
VM
CPS,
CPR
VM
tPHL
VM
VM
tPLH
tPLH
ERROR
VM
PARITY
VM
VM
tPHL
VM
tPLH
VM
ERROR
VM
tPHL
SF01045
SF01046
Waveform 3. Propagation Delay, Output Enable to ERROR
An, Bn
CES, CER
PARITY
VM
VM
VM
VM
ts(L)
th(H)
ts(H)
th(L)
Waveform 4. Propagation Delay, Clock to PARITY and ERROR
OEAS, OEBR
VM
tREC
VM
CPS, CPR
CPS,
CPR
VM
VM
SF01047
SF01048
Waveform 5. Data Setup and Hold Times
OEAS, OEBR
VM
OEAS, OEBR
VM
tPZH
An, Bn
PARITY
Waveform 6. Recovery Time from Output Enable to Clock
tPHZ
VOH -0.3V
VM
tPZL
An, Bn
PARITY
VM
0V
tPLZ
VM
VOL +0.3V
SF01050
SF01049
Waveform 7. 3-State Output Enable Time to High Level
and Output Disable Time from High Level
1991 Jan 02
VM
Waveform 8. 3-State Output Enable Time to Low Level
and Output Disable Time from Low Level
9
Philips Semiconductors
Product specification
Octal registered transceiver with parity and flags (3-State)
74F552
TEST CIRCUIT AND WAVEFORM
VCC
7.0V
VIN
RL
VOUT
PULSE
GENERATOR
tw
90%
NEGATIVE
PULSE
VM
CL
AMP (V)
VM
10%
D.U.T.
RT
90%
10%
tTHL (tf )
tTLH (tr )
tTLH (tr )
tTHL (tf )
0V
RL
AMP (V)
90%
90%
Test Circuit for 3-State Outputs
POSITIVE
PULSE
VM
VM
10%
TEST
tPLZ
tPZL
All other
SWITCH
closed
closed
open
DEFINITIONS:
RL = Load resistor;
see AC electrical characteristics for value.
CL = Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
RT = Termination resistance should be equal to ZOUT of
pulse generators.
10%
tw
SWITCH POSITION
0V
Input Pulse Definition
INPUT PULSE REQUIREMENTS
family
amplitude VM
74F
3.0V
1.5V
rep. rate
tw
tTLH
tTHL
1MHz
500ns
2.5ns
2.5ns
SF00777
1991 Jan 02
10
Philips Semiconductors
Product specification
Octal registered transceiver with parity and flags (3-State)
DIP28: plastic dual in-line package; 28 leads (600 mil); long body
1991 Jan 02
11
74F552
SOT117-2
Philips Semiconductors
Product specification
Octal registered transceiver with parity and flags (3-State)
SO28: plastic small outline package; 28 leads; body width 7.5mm
1991 Jan 02
12
74F552
SOT136-1
Philips Semiconductors
Product specification
Octal registered transceiver with parity and flags (3-State)
NOTES
1991 Jan 02
13
74F552
Philips Semiconductors
Product specification
Octal registered transceiver with parity and flags (3-State)
74F552
Data sheet status
Data sheet
status
Product
status
Definition [1]
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
 Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
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Date of release: 10-98
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