74AVCH2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state Rev. 01 — 3 July 2007 Product data sheet 1. General description The 74AVCH2T45 is a dual bit, dual supply transceiver that enables bidirectional level translation. It features two data input-output ports (nA and nB), a direction control input (DIR) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 0.8 V and 3.6 V making the device suitable for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins nA and DIR are referenced to VCC(A) and pins nB are referenced to VCC(B). A HIGH on DIR allows transmission from nA to nB and a LOW on DIR allows transmission from nB to nA. The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both A and B are in the high-impedance OFF-state. The 74AVCH2T45 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors. 2. Features n Wide supply voltage range: u VCC(A): 0.8 V to 3.6 V u VCC(B): 0.8 V to 3.6 V n High noise immunity n Complies with JEDEC standards: u JESD8-12 (0.8 V to 1.3 V) u JESD8-11 (0.9 V to 1.65 V) u JESD8-7 (1.2 V to 1.95 V) u JESD8-5 (1.8 V to 2.7 V) u JESD8-B (2.7 V to 3.6 V) n ESD protection: u HBM JESD22-A114E Class 3B exceeds 8000 V u MM JESD22-A115-A exceeds 200 V u CDM JESD22-C101C exceeds 1000 V n Maximum data rates: u 500 Mbps (1.8 V to 3.3 V translation) u 320 Mbps (< 1.8 V to 3.3 V translation) u 320 Mbps (translate to 2.5 V or 1.8 V) 74AVCH2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state n n n n n n n n u 280 Mbps (translate to 1.5 V) u 240 Mbps (translate to 1.2 V) Suspend mode Bus hold on data inputs Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of VCC IOFF circuitry provides partial Power-down mode operation SOT765-1 and SOT833-1 package options Specified from −40 °C to +85 °C and −40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description 74AVCH2T45DC −40 °C to +125 °C VSSOP8 plastic very thin shrink small outline package; 8 leads; SOT765-1 body width 2.3 mm Version 74AVCH2T45GT −40 °C to +125 °C XSON8 plastic extremely thin small outline package; no leads; SOT833-1 8 terminals; body 1 × 1.95 × 0.5 mm 4. Marking Table 2. Marking Type number Marking code 74AVCH2T45DC K45 74AVCH2T45GT K45 5. Functional diagram DIR 5 DIR 1A 2 1A 7 1B 1B 2A 3 2A 6 2B 2B VCC(A) VCC(B) VCC(A) 001aag577 Fig 1. Logic symbol 001aag578 Fig 2. Logic diagram 74AVCH2T45_1 Product data sheet VCC(B) © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 2 of 29 74AVCH2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state 6. Pinning information 6.1 Pinning 74AVCH2T45 VCC(A) 1 8 VCC(B) 1A 2 7 1B 2A 3 6 2B GND 4 5 DIR 74AVCH2T45 VCC(A) 1 8 VCC(B) 1A 2 7 1B 2A 3 6 2B GND 4 5 DIR 001aag584 Transparent top view 001aag583 Fig 3. Pin configuration SOT765-1 (VSSOP8) Fig 4. Pin configuration SOT833-1 (XSON8) 6.2 Pin description Table 3. Pin description Symbol Pin Description VCC(A) 1 supply voltage port A and DIR 1A 2 data input or output 2A 3 data input or output GND 4 ground (0 V) DIR 5 direction control 2B 6 data input or output 1B 7 data input or output VCC(B) 8 supply voltage port B 7. Functional description Table 4. Function table[1] Supply voltage Input Input/output[2] VCC(A), VCC(B) DIR[3] nA nB 0.8 V to 3.6 V L nA = nB input 0.8 V to 3.6 V H input nB = nA GND[4] X Z Z [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. [2] The input circuit of the data I/O is always active. [3] The DIR input circuit is referenced to VCC(A). [4] If at least one of VCC(A) or VCC(B) is at GND level, the device goes into suspend mode. 74AVCH2T45_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 3 of 29 74AVCH2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC(A) supply voltage port A VCC(B) supply voltage port B IIK input clamping current VI input voltage IOK output clamping current output voltage VO Conditions VI < 0 V [1] Suspend or 3-state mode Max Unit −0.5 +4.6 V −0.5 +4.6 V −50 - mA −0.5 +4.6 V mA −50 - [1][2][3] −0.5 VCCO + 0.5 V [1] −0.5 +4.6 V VO < 0 V Active mode Min IO output current VO = 0 V to VCC - ±50 mA ICC supply current ICC(A) or ICC(B) - 100 mA IGND ground current −100 - mA Tstg storage temperature −65 +150 °C - 250 mW total power dissipation Ptot [1] Tamb = −40 °C to +125 °C [4] The minimum input voltage rating and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] VCCO is the supply voltage associated with the output port. [3] VCCO + 0.5 V should not exceed 4.6 V. [4] For VSSOP8 package: above 110 °C the value of Ptot derates linearly with 8 mW/K. For XSON8 package: above 45 °C the value of Ptot derates linearly with 2.4 mW/K. 9. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter Min Max Unit VCC(A) supply voltage port A 0.8 3.6 V VCC(B) supply voltage port B 0.8 3.6 V VI input voltage 0 3.6 V 0 VCCO V 0 3.6 V −40 +125 °C - 5 ns/V output voltage VO Conditions Active mode Suspend or 3-state mode Tamb ambient temperature ∆t/∆V input transition rise and fall rate [1] VCCI =0.8 V to 3.6 V [1] VCCO is the supply voltage associated with the output port. 74AVCH2T45_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 4 of 29 74AVCH2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. Symbol Parameter Conditions Min Typ Max Unit - 0.69 - V Tamb = 25 °C HIGH-level output voltage VI = VIH VOL LOW-level output voltage VI = VIL - 0.07 - V II input leakage current DIR input; VI = GND to VCC(A); VCC(A) = VCC(B) = 0.8 V to 3.6 V - ±0.025 ±0.25 µA IBHL bus hold LOW current VI = 0.42 V; VCC(A) = VCC(B) = 1.2 V - 26 - µA IBHH bus hold HIGH current VI = 0.78 V; VCC(A) = VCC(B) = 1.2 V - −24 - µA IBHLO bus hold LOW overdrive current VI = GND to VCCI; VCC(A) = VCC(B) = 1.2 V [1] - 28 - µA IBHHO bus hold HIGH overdrive current VI = GND to VCCI; VCC(A) = VCC(B) = 1.2 V [1] - −26 - µA IOZ OFF-state output current A or B port; VO = GND or VCCO; VCC(A) = VCC(B) = 0.8 V to 3.6 V [2] - ±0.5 ±2.5 µA IOFF power-off leakage current A port; VI or VO = 0 V to 3.6 V; VCC(A) = 0 V; VCC(B) = 0.8 V to 3.6 V - ±0.1 ±1.0 µA B port; VI or VO = 0 V to 3.6 V; VCC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V - ±0.1 ±1.0 µA - 1.0 - pF - 4.0 - pF VCCI = 0.8 V 0.70 × VCCI - - V VCCI = 1.1 V to 1.95 V 0.65 × VCCI - - V VCCI = 2.3 V to 2.7 V 1.6 - - V 2.0 - - V VCCI = 0.8 V 0.70 × VCC(A) - - V VCCI = 1.1 V to 1.95 V 0.65 × VCC(A) - - V VCCI = 2.3 V to 2.7 V 1.6 - - V VCCI = 3.0 V to 3.6 V 2.0 - - V VOH IO = −1.5 mA; VCC(A) = VCC(B) = 0.8 V IO = 1.5 mA; VCC(A) = VCC(B) = 0.8 V CI input capacitance DIR input; VI = GND or 3.3 V; VCC(A) = VCC(B) = 3.3 V CI/O input/output capacitance A and B port; suspend mode; VO = VCCO or GND; VCC(A) = VCC(B) = 3.3 V [2] data input [1] Tamb = −40 °C to +85 °C VIH HIGH-level input voltage VCCI = 3.0 V to 3.6 V [1] DIR input 74AVCH2T45_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 5 of 29 74AVCH2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. Symbol Parameter VIL LOW-level input voltage Conditions Min Typ Max Unit VCCI = 0.8 V - - 0.30 × VCCI V VCCI = 1.1 V to 1.95 V - - 0.35 × VCCI V VCCI = 2.3 V to 2.7 V - - 0.7 V - - 0.9 V VCCI = 0.8 V - - 0.30 × VCC(A) V VCCI = 1.1 V to 1.95 V - - 0.35 × VCC(A) V VCCI = 2.3 V to 2.7 V - - 0.7 V VCCI = 3.0 V to 3.6 V - - 0.9 V VCCO − 0.1 - - V [1] data input VCCI = 3.0 V to 3.6 V [1] DIR input VOH VOL HIGH-level output voltage LOW-level output voltage VI = VIH IO = −100 µA; VCC(A) = VCC(B) = 0.8 V to 3.6 V [2] IO = −3 mA; VCC(A) = VCC(B) = 1.1 V 0.85 - - V IO = −6 mA; VCC(A) = VCC(B) = 1.4 V 1.05 - - V IO = −8 mA; VCC(A) = VCC(B) = 1.65 V 1.2 - - V IO = −9 mA; VCC(A) = VCC(B) = 2.3 V 1.75 - - V IO = −12 mA; VCC(A) = VCC(B) = 3.0 V 2.3 - - V IO = 100 µA; VCC(A) = VCC(B) = 0.8 V to 3.6 V - - 0.1 V IO = 3 mA; VCC(A) = VCC(B) = 1.1 V - - 0.25 V IO = 6 mA; VCC(A) = VCC(B) = 1.4 V - - 0.35 V IO = 8 mA; VCC(A) = VCC(B) = 1.65 V - - 0.45 V IO = 9 mA; VCC(A) = VCC(B) = 2.3 V - - 0.55 V IO = 12 mA; VCC(A) = VCC(B) = 3.0 V VI = VIL - - 0.7 V II input leakage current DIR input; VI = GND to VCC(A); VCC(A) = VCC(B) = 0.8 V to 3.6 V - - ±1.0 µA IBHL bus hold LOW current VI = 0.49 V; VCC(A) = VCC(B) = 1.4 V 15 - - µA IBHH bus hold HIGH current VI = 0.58 V; VCC(A) = VCC(B) = 1.65 V 25 - - µA VI = 0.70 V; VCC(A) = VCC(B) = 2.3 V 45 - - µA VI = 0.80 V; VCC(A) = VCC(B) = 3.0 V 100 - - µA VI = 0.91 V; VCC(A) = VCC(B) = 1.4 V −15 - - µA VI = 1.07 V; VCC(A) = VCC(B) = 1.65 V −25 - - µA VI = 1.60 V; VCC(A) = VCC(B) = 2.3 V −45 - - µA VI = 2.00 V; VCC(A) = VCC(B) = 3.0 V −100 - - µA 74AVCH2T45_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 6 of 29 74AVCH2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. Symbol Parameter IBHLO bus hold LOW overdrive current Conditions Min Typ Max Unit VCC(A) = VCC(B) = 1.6 V 125 - - µA VCC(A) = VCC(B) = 1.95 V 200 - - µA VCC(A) = VCC(B) = 2.7 V 300 - - µA 500 - - µA VCC(A) = VCC(B) = 1.6 V −125 - - µA VCC(A) = VCC(B) = 1.95 V −200 - - µA VCC(A) = VCC(B) = 2.7 V −300 - - µA [1] VI = GND to VCCI VCC(A) = VCC(B) = 3.6 V IBHHO bus hold HIGH overdrive current [1] VI = GND to VCCI −500 - - µA - - ±5.0 µA A port; VI or VO = 0 V to 3.6 V; VCC(A) = 0 V; VCC(B) = 0.8 V to 3.6 V - - ±5.0 µA B port; VI or VO = 0 V to 3.6 V; VCC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V - - ±5.0 µA VCC(A) = VCC(B) = 3.6 V IOZ OFF-state output current A or B port; VO = GND or VCCO; VCC(A) = VCC(B) = 0.8 V to 3.6 V IOFF power-off leakage current ICC supply current A port; VI = GND or VCCI; IO = 0 A [2] [1] VCC(A) = VCC(B) = 0.8 V to 3.6 V - - 8.0 µA VCC(A) = 3.6 V; VCC(B) = 0 V - - 8.0 µA −2 0 - µA VCC(A) = 0 V; VCC(B) = 3.6 V B port; VI = GND or VCCI; IO = 0 A [1] VCC(A) = VCC(B) = 0.8 V to 3.6 V - - 8 µA VCC(A) = 3.6 V; VCC(B) = 0 V −2 0 - µA - - 8 µA - - 16 µA VCCI = 0.8 V 0.70 × VCCI - - V VCCI = 1.1 V to 1.95 V 0.65 × VCCI - - V VCCI = 2.3 V to 2.7 V 1.6 - - V 2.0 - - V VCCI = 0.8 V 0.70 × VCC(A) - - V VCCI = 1.1 V to 1.95 V 0.65 × VCC(A) - - V VCCI = 2.3 V to 2.7 V 1.6 - - V VCCI = 3.0 V to 3.6 V 2.0 - - V VCC(A) = 0 V; VCC(B) = 3.6 V A plus B port (ICC(A) + ICC(B)); IO = 0 A; VI = GND or VCCI; VCC(A) = VCC(B) = 0.8 V to 3.6 V [1] data input [1] Tamb = −40 °C to +125 °C VIH HIGH-level input voltage VCCI = 3.0 V to 3.6 V [1] DIR input 74AVCH2T45_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 7 of 29 74AVCH2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. Symbol Parameter VIL LOW-level input voltage Conditions Min Typ Max Unit VCCI = 0.8 V - - 0.30 × VCCI V VCCI = 1.1 V to 1.95 V - - 0.35 × VCCI V VCCI = 2.3 V to 2.7 V - - 0.7 V - - 0.9 V VCCI = 0.8 V - - 0.30 × VCC(A) V VCCI = 1.1 V to 1.95 V - - 0.35 × VCC(A) V VCCI = 2.3 V to 2.7 V - - 0.7 V VCCI = 3.0 V to 3.6 V - - 0.9 V VCCO − 0.1 - - V [1] data input VCCI = 3.0 V to 3.6 V [1] DIR input VOH VOL HIGH-level output voltage LOW-level output voltage VI = VIH IO = −100 µA; VCC(A) = VCC(B) = 0.8 V to 3.6 V [2] IO = −3 mA; VCC(A) = VCC(B) = 1.1 V 0.85 - - V IO = −6 mA; VCC(A) = VCC(B) = 1.4 V 1.05 - - V IO = −8 mA; VCC(A) = VCC(B) = 1.65 V 1.2 - - V IO = −9 mA; VCC(A) = VCC(B) = 2.3 V 1.75 - - V IO = −12 mA; VCC(A) = VCC(B) = 3.0 V 2.3 - - V IO = 100 µA; VCC(A) = VCC(B) = 0.8 V to 3.6 V - - 0.1 V IO = 3 mA; VCC(A) = VCC(B) = 1.1 V - - 0.25 V IO = 6 mA; VCC(A) = VCC(B) = 1.4 V - - 0.35 V IO = 8 mA; VCC(A) = VCC(B) = 1.65 V - - 0.45 V IO = 9 mA; VCC(A) = VCC(B) = 2.3 V - - 0.55 V IO = 12 mA; VCC(A) = VCC(B) = 3.0 V VI = VIL - - 0.7 V II input leakage current DIR input; VI = GND to VCC(A); VCC(A) = VCC(B) = 0.8 V to 3.6 V - - ±1.5 µA IBHL bus hold LOW current VI = 0.49 V; VCC(A) = VCC(B) = 1.4 V 15 - - µA IBHH bus hold HIGH current VI = 0.58 V; VCC(A) = VCC(B) = 1.65 V 25 - - µA VI = 0.70 V; VCC(A) = VCC(B) = 2.3 V 45 - - µA VI = 0.80 V; VCC(A) = VCC(B) = 3.0 V 90 - - µA VI = 0.91 V; VCC(A) = VCC(B) = 1.4 V −15 - - µA VI = 1.07 V; VCC(A) = VCC(B) = 1.65 V −25 - - µA VI = 1.60 V; VCC(A) = VCC(B) = 2.3 V −45 - - µA VI = 2.00 V; VCC(A) = VCC(B) = 3.0 V −100 - - µA 74AVCH2T45_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 8 of 29 74AVCH2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. Symbol Parameter IBHLO bus hold LOW overdrive current Conditions Min Typ Max Unit VCC(A) = VCC(B) = 1.6 V 125 - - µA VCC(A) = VCC(B) = 1.95 V 200 - - µA VCC(A) = VCC(B) = 2.7 V 300 - - µA 500 - - µA VCC(A) = VCC(B) = 1.6 V −125 - - µA VCC(A) = VCC(B) = 1.95 V −200 - - µA VCC(A) = VCC(B) = 2.7 V −300 - - µA [1] VI = GND to VCCI VCC(A) = VCC(B) = 3.6 V IBHHO bus hold HIGH overdrive current [1] VI = GND to VCCI −500 - - µA - - ±7.5 µA A port; VI or VO = 0 V to 3.6 V; VCC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V - - ±35 µA B port; VI or VO = 0 V to 3.6 V; VCC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V - - ±35 µA VCC(A) = VCC(B) = 3.6 V IOZ OFF-state output current A or B port; VO = GND or VCCO; VCC(A) = VCC(B) = 0.8 V to 3.6 V IOFF power-off leakage current supply current ICC A port; VI = GND or VCCI; IO = 0 A [2] [1] VCC(A) = VCC(B) = 0.8 V to 3.6 V - - 11.5 µA VCC(A) = 3.6 V; VCC(B) = 0 V - - 11.5 µA −8 0 - µA VCC(A) = 0 V; VCC(B) = 3.6 V B port; VI = GND or VCCI; IO = 0 A [1] VCC(A) = VCC(B) = 0.8 V to 3.6 V - - 11.5 µA VCC(A) = 3.6 V; VCC(B) = 0 V −8 0 - µA - - 11.5 µA - - 23 µA VCC(A) = 0 V; VCC(B) = 3.6 V A plus B port (ICC(A) + ICC(B)); IO = 0 A; VI = GND or VCCI; VCC(A) = VCC(B) = 0.8 V to 3.6 V [1] VCCI is the supply voltage associated with the data input port. [2] VCCO is the supply voltage associated with the output port. 74AVCH2T45_1 Product data sheet [1] © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 9 of 29 74AVCH2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7. Symbol Parameter 25 °C Conditions −40 °C to +125 °C Unit Min Typ[1] Max Min Max (85 °C) Max (125 °C) VCC(B) = 0.8 V - 15.8 - - - - ns VCC(B) = 1.1 V to 1.3 V - 8.4 - - - - ns VCC(B) = 1.4 V to 1.6 V - 8.0 - - - - ns VCC(B) = 1.65 V to 1.95 V - 8.0 - - - - ns VCC(B) = 2.3 V to 2.7 V - 8.7 - - - - ns - 9.5 - - - - ns VCC(B) = 0.8 V - 15.8 - - - - ns VCC(B) = 1.1 V to 1.3 V - 12.7 - - - - ns VCC(A) = 0.8 V tpd [2] propagation delay A to B; see Figure 5 VCC(B) = 3.0 V to 3.6 V [2] B to A; see Figure 5 VCC(B) = 1.4 V to 1.6 V - 12.4 - - - - ns VCC(B) = 1.65 V to 1.95 V - 12.2 - - - - ns VCC(B) = 2.3 V to 2.7 V - 12.0 - - - - ns - 11.8 - - - - ns VCC(B) = 0.8 V - 12.2 - - - - ns VCC(B) = 1.1 V to 1.3 V - 12.2 - - - - ns VCC(B) = 1.4 V to 1.6 V - 12.2 - - - - ns VCC(B) = 1.65 V to 1.95 V - 12.2 - - - - ns VCC(B) = 2.3 V to 2.7 V - 12.2 - - - - ns - 12.2 - - - - ns VCC(B) = 0.8 V - 11.7 - - - - ns VCC(B) = 1.1 V to 1.3 V - 7.9 - - - - ns VCC(B) = 1.4 V to 1.6 V - 7.6 - - - - ns VCC(B) = 1.65 V to 1.95 V - 8.2 - - - - ns VCC(B) = 2.3 V to 2.7 V - 8.7 - - - - ns VCC(B) = 3.0 V to 3.6 V - 10.2 - - - - ns VCC(B) = 3.0 V to 3.6 V tdis disable time DIR to A; see Figure 6 [3] VCC(B) = 3.0 V to 3.6 V DIR to B; see Figure 6 [3] 74AVCH2T45_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 10 of 29 74AVCH2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7. Symbol Parameter ten enable time 25 °C Conditions −40 °C to +125 °C Unit Min Typ[1] Max Min Max (85 °C) Max (125 °C) VCC(B) = 0.8 V - 27.5 - - - - ns VCC(B) = 1.1 V to 1.3 V - 20.6 - - - - ns VCC(B) = 1.4 V to 1.6 V - 20.0 - - - - ns VCC(B) = 1.65 V to 1.95 V - 20.4 - - - - ns VCC(B) = 2.3 V to 2.7 V - 20.7 - - - - ns - 22.0 - - - - ns VCC(B) = 0.8 V - 28.0 - - - - ns VCC(B) = 1.1 V to 1.3 V - 20.6 - - - - ns VCC(B) = 1.4 V to 1.6 V - 20.2 - - - - ns VCC(B) = 1.65 V to 1.95 V - 20.2 - - - - ns VCC(B) = 2.3 V to 2.7 V - 20.9 - - - - ns VCC(B) = 3.0 V to 3.6 V - 21.7 - - - - ns VCC(B) = 0.8 V - 12.7 - - - - ns VCC(B) = 1.1 V to 1.3 V - - - 1.0 9.0 9.9 ns VCC(B) = 1.4 V to 1.6 V - - - 0.7 6.8 7.5 ns VCC(B) = 1.65 V to 1.95 V - - - 0.6 6.1 6.8 ns VCC(B) = 2.3 V to 2.7 V - - - 0.5 5.7 6.3 ns VCC(B) = 3.0 V to 3.6 V - - - 0.5 6.1 6.8 ns VCC(B) = 0.8 V - 8.4 - - - - ns VCC(B) = 1.1 V to 1.3 V - - - 1.0 9.0 9.9 ns VCC(B) = 1.4 V to 1.6 V - - - 0.8 8.0 8.8 ns VCC(B) = 1.65 V to 1.95 V - - - 0.7 7.7 8.5 ns VCC(B) = 2.3 V to 2.7 V - - - 0.6 7.2 8.0 ns VCC(B) = 3.0 V to 3.6 V - - - 0.5 7.1 7.9 ns DIR to A; see Figure 6 [4][5] VCC(B) = 3.0 V to 3.6 V DIR to B; see Figure 6 [4][5] VCC(A) = 1.1 V to 1.3 V tpd [2] propagation delay A to B; see Figure 5 [2] B to A; see Figure 5 74AVCH2T45_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 11 of 29 74AVCH2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7. Symbol Parameter tdis disable time 25 °C Conditions Max Min Max (85 °C) Max (125 °C) - 4.9 - - - - ns - - - 2.2 8.8 9.7 ns VCC(B) = 0.8 V - 9.2 - - - - ns VCC(B) = 1.1 V to 1.3 V - - - 2.2 8.4 9.2 ns VCC(B) = 1.4 V to 1.6 V - - - 1.8 6.7 7.4 ns VCC(B) = 1.65 V to 1.95 V - - - 2.0 6.9 7.6 ns VCC(B) = 2.3 V to 2.7 V - - - 1.7 6.2 6.9 ns VCC(B) = 3.0 V to 3.6 V - - - 2.4 7.2 8.0 ns VCC(B) = 0.8 V - 17.6 - - - - ns VCC(B) = 1.1 V to 1.3 V - - - - 17.4 19.1 ns VCC(B) = 1.4 V to 1.6 V - - - - 14.7 16.2 ns VCC(B) = 1.65 V to 1.95 V - - - - 14.6 16.1 ns VCC(B) = 2.3 V to 2.7 V - - - - 13.4 14.9 ns - - - - 14.3 15.9 ns VCC(B) = 0.8 V - 17.6 - - - - ns VCC(B) = 1.1 V to 1.3 V - - - - 17.8 19.6 ns DIR to A; see Figure 6 [3] VCC(B) = 1.1 V to 3.6 V DIR to B; see Figure 6 enable time DIR to A; see Figure 6 [3] [4][5] VCC(B) = 3.0 V to 3.6 V DIR to B; see Figure 6 [4][5] VCC(B) = 1.4 V to 1.6 V - - - - 15.6 17.2 ns VCC(B) = 1.65 V to 1.95 V - - - - 14.9 16.5 ns VCC(B) = 2.3 V to 2.7 V - - - - 14.5 16.0 ns VCC(B) = 3.0 V to 3.6 V - - - - 14.9 16.5 ns 74AVCH2T45_1 Product data sheet Unit Min VCC(B) = 0.8 V ten −40 °C to +125 °C Typ[1] © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 12 of 29 74AVCH2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7. Symbol Parameter 25 °C Conditions −40 °C to +125 °C Unit Min Typ[1] Max Min Max (85 °C) Max (125 °C) VCC(B) = 0.8 V - 12.4 - - - - ns VCC(B) = 1.1 V to 1.3 V - - - 1.0 8.0 8.8 ns VCC(A) = 1.4 V to 1.6 V tpd [2] propagation delay A to B; see Figure 5 VCC(B) = 1.4 V to 1.6 V - - - 0.7 5.4 6.0 ns VCC(B) = 1.65 V to 1.95 V - - - 0.6 4.6 5.1 ns VCC(B) = 2.3 V to 2.7 V - - - 0.5 3.7 4.1 ns - - - 0.5 3.5 3.9 ns VCC(B) = 0.8 V - 8.0 - - - - ns VCC(B) = 1.1 V to 1.3 V - - - 1.0 6.8 7.5 ns VCC(B) = 1.4 V to 1.6 V - - - 0.8 5.4 6.0 ns VCC(B) = 1.65 V to 1.95 V - - - 0.7 5.1 5.7 ns VCC(B) = 2.3 V to 2.7 V - - - 0.6 4.7 5.2 ns - - - 0.5 4.5 5.0 ns VCC(B) = 0.8 V - 3.8 - - - - ns VCC(B) = 1.1 V to 3.6 V - - - 1.6 6.3 7.0 ns VCC(B) = 0.8 V - 9.0 - - - - ns VCC(B) = 1.1 V to 1.3 V - - - 2.0 7.6 8.3 ns VCC(B) = 1.4 V to 1.6 V - - - 1.8 5.9 6.5 ns VCC(B) = 1.65 V to 1.95 V - - - 1.6 6.0 6.6 ns VCC(B) = 2.3 V to 2.7 V - - - 1.2 4.8 5.3 ns VCC(B) = 3.0 V to 3.6 V - - - 1.7 5.5 6.1 ns VCC(B) = 3.0 V to 3.6 V [2] B to A; see Figure 5 VCC(B) = 3.0 V to 3.6 V tdis disable time DIR to A; see Figure 6 DIR to B; see Figure 6 [3] [3] 74AVCH2T45_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 13 of 29 74AVCH2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7. Symbol Parameter ten enable time 25 °C Conditions −40 °C to +125 °C Unit Min Typ[1] Max Min Max (85 °C) Max (125 °C) VCC(B) = 0.8 V - 17.0 - - - - ns VCC(B) = 1.1 V to 1.3 V - - - - 14.4 15.8 ns VCC(B) = 1.4 V to 1.6 V - - - - 11.3 12.5 ns VCC(B) = 1.65 V to 1.95 V - - - - 11.1 12.3 ns VCC(B) = 2.3 V to 2.7 V - - - - 9.5 10.5 ns - - - - 10.0 11.1 ns VCC(B) = 0.8 V - 16.2 - - - - ns VCC(B) = 1.1 V to 1.3 V - - - - 14.3 15.8 ns VCC(B) = 1.4 V to 1.6 V - - - - 11.7 13.0 ns VCC(B) = 1.65 V to 1.95 V - - - - 10.9 12.7 ns VCC(B) = 2.3 V to 2.7 V - - - - 10.0 11.1 ns VCC(B) = 3.0 V to 3.6 V - - - - 9.8 10.9 ns VCC(B) = 0.8 V - 12.2 - - - - ns VCC(B) = 1.1 V to 1.3 V - - - 1.0 7.7 8.5 ns VCC(B) = 1.4 V to 1.6 V - - - 0.6 5.1 5.7 ns VCC(B) = 1.65 V to 1.95 V - - - 0.5 4.3 4.8 ns VCC(B) = 2.3 V to 2.7 V - - - 0.5 3.4 3.8 ns VCC(B) = 3.0 V to 3.6 V - - - 0.5 3.1 3.5 ns VCC(B) = 0.8 V - 8.0 - - - - ns VCC(B) = 1.1 V to 1.3 V - - - 1.0 6.1 6.8 ns VCC(B) = 1.4 V to 1.6 V - - - 0.7 4.6 5.1 ns VCC(B) = 1.65 V to 1.95 V - - - 0.5 4.4 4.9 ns VCC(B) = 2.3 V to 2.7 V - - - 0.5 3.9 4.3 ns VCC(B) = 3.0 V to 3.6 V - - - 0.5 3.7 4.1 ns DIR to A; see Figure 6 [4][5] VCC(B) = 3.0 V to 3.6 V DIR to B; see Figure 6 [4][5] VCC(A) = 1.65 V to 1.95 V tpd [2] propagation delay A to B; see Figure 5 [2] B to A; see Figure 5 74AVCH2T45_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 14 of 29 74AVCH2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7. Symbol Parameter tdis disable time 25 °C Conditions Max Min Max (85 °C) Max (125 °C) - 3.7 - - - - ns - - - 1.6 5.5 6.1 ns VCC(B) = 0.8 V - 8.8 - - - - ns VCC(B) = 1.1 V to 1.3 V - - - 1.8 7.8 8.6 ns VCC(B) = 1.4 V to 1.6 V - - - 1.8 5.7 6.3 ns VCC(B) = 1.65 V to 1.95 V - - - 1.4 5.8 6.4 ns VCC(B) = 2.3 V to 2.7 V - - - 1.0 4.5 5.0 ns VCC(B) = 3.0 V to 3.6 V - - - 1.5 5.2 5.8 ns VCC(B) = 0.8 V - 16.8 - - - - ns VCC(B) = 1.1 V to 1.3 V - - - - 13.9 15.4 ns VCC(B) = 1.4 V to 1.6 V - - - - 10.3 11.4 ns VCC(B) = 1.65 V to 1.95 V - - - - 10.2 11.3 ns VCC(B) = 2.3 V to 2.7 V - - - - 8.4 9.3 ns - - - - 8.9 9.9 ns VCC(B) = 0.8 V - 15.9 - - - - ns VCC(B) = 1.1 V to 1.3 V - - - - 13.2 14.6 ns DIR to A; see Figure 6 [3] VCC(B) = 1.1 V to 3.6 V DIR to B; see Figure 6 enable time DIR to A; see Figure 6 [3] [4][5] VCC(B) = 3.0 V to 3.6 V DIR to B; see Figure 6 [4][5] VCC(B) = 1.4 V to 1.6 V - - - - 10.6 11.8 ns VCC(B) = 1.65 V to 1.95 V - - - - 9.8 10.9 ns VCC(B) = 2.3 V to 2.7 V - - - - 8.9 9.9 ns VCC(B) = 3.0 V to 3.6 V - - - - 8.6 9.6 ns 74AVCH2T45_1 Product data sheet Unit Min VCC(B) = 0.8 V ten −40 °C to +125 °C Typ[1] © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 15 of 29 74AVCH2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7. Symbol Parameter 25 °C Conditions −40 °C to +125 °C Unit Min Typ[1] Max Min Max (85 °C) Max (125 °C) VCC(B) = 0.8 V - 12.0 - - - - ns VCC(B) = 1.1 V to 1.3 V - - - 1.0 7.2 8.0 ns VCC(A) = 2.3 V to 2.7 V tpd [2] propagation delay A to B; see Figure 5 VCC(B) = 1.4 V to 1.6 V - - - 0.5 4.7 5.2 ns VCC(B) = 1.65 V to 1.95 V - - - 0.5 3.9 4.3 ns VCC(B) = 2.3 V to 2.7 V - - - 0.5 3.0 3.3 ns - - - 0.5 2.6 2.9 ns VCC(B) = 0.8 V - 8.7 - - - - ns VCC(B) = 1.1 V to 1.3 V - - - 1.0 5.7 6.3 ns VCC(B) = 1.4 V to 1.6 V - - - 0.6 3.8 4.2 ns VCC(B) = 1.65 V to 1.95 V - - - 0.5 3.4 3.8 ns VCC(B) = 2.3 V to 2.7 V - - - 0.5 3.0 3.3 ns - - - 0.5 2.8 3.1 ns VCC(B) = 0.8 V - 2.8 - - - - ns VCC(B) = 1.1 V to 3.6 V - - - 1.5 4.2 4.7 ns VCC(B) = 0.8 V - 8.7 - - - - ns VCC(B) = 1.1 V to 1.3 V - - - 1.7 7.3 8.0 ns VCC(B) = 1.4 V to 1.6 V - - - 2.0 5.2 5.8 ns VCC(B) = 1.65 V to 1.95 V - - - 1.5 5.1 5.7 ns VCC(B) = 2.3 V to 2.7 V - - - 0.6 4.2 4.7 ns VCC(B) = 3.0 V to 3.6 V - - - 1.1 4.8 5.3 ns VCC(B) = 3.0 V to 3.6 V [2] B to A; see Figure 5 VCC(B) = 3.0 V to 3.6 V tdis disable time DIR to A; see Figure 6 DIR to B; see Figure 6 [3] [3] 74AVCH2T45_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 16 of 29 74AVCH2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7. Symbol Parameter ten enable time 25 °C Conditions −40 °C to +125 °C Unit Min Typ[1] Max Min Max (85 °C) Max (125 °C) VCC(B) = 0.8 V - 17.4 - - - - ns VCC(B) = 1.1 V to 1.3 V - - - - 13.0 14.3 ns VCC(B) = 1.4 V to 1.6 V - - - - 9.0 10.0 ns VCC(B) = 1.65 V to 1.95 V - - - - 8.5 9.5 ns VCC(B) = 2.3 V to 2.7 V - - - - 7.2 8.0 ns - - - - 7.6 8.4 ns VCC(B) = 0.8 V - 14.8 - - - - ns VCC(B) = 1.1 V to 1.3 V - - - - 11.4 12.7 ns VCC(B) = 1.4 V to 1.6 V - - - - 8.9 9.9 ns VCC(B) = 1.65 V to 1.95 V - - - - 8.1 9.0 ns VCC(B) = 2.3 V to 2.7 V - - - - 7.2 8.0 ns VCC(B) = 3.0 V to 3.6 V - - - - 6.8 7.6 ns VCC(B) = 0.8 V - 11.8 - - - - ns VCC(B) = 1.1 V to 1.3 V - - - 1.0 7.1 7.9 ns VCC(B) = 1.4 V to 1.6 V - - - 0.5 4.5 5.0 ns VCC(B) = 1.65 V to 1.95 V - - - 0.5 3.7 4.1 ns VCC(B) = 2.3 V to 2.7 V - - - 0.5 2.8 3.1 ns VCC(B) = 3.0 V to 3.6 V - - - 0.5 2.4 2.7 ns VCC(B) = 0.8 V - 9.5 - - - - ns VCC(B) = 1.1 V to 1.3 V - - - 1.0 6.1 6.8 ns VCC(B) = 1.4 V to 1.6 V - - - 0.6 3.6 4.0 ns VCC(B) = 1.65 V to 1.95 V - - - 0.5 3.1 3.5 ns VCC(B) = 2.3 V to 2.7 V - - - 0.5 2.6 2.9 ns VCC(B) = 3.0 V to 3.6 V - - - 0.5 2.4 2.7 ns DIR to A; see Figure 6 [4][5] VCC(B) = 3.0 V to 3.6 V DIR to B; see Figure 6 [4][5] VCC(A) = 3.0 V to 3.6 V tpd [2] propagation delay A to B; see Figure 5 [2] B to A; see Figure 5 74AVCH2T45_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 17 of 29 74AVCH2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7. Symbol Parameter tdis disable time 25 °C Conditions Max Min Max (85 °C) Max (125 °C) - 3.4 - - - - ns - - - 1.5 4.7 5.2 ns VCC(B) = 0.8 V - 8.6 - - - - ns VCC(B) = 1.1 V to 1.3 V - - - 1.7 7.2 7.9 ns VCC(B) = 1.4 V to 1.6 V - - - 0.7 5.5 6.1 ns VCC(B) = 1.65 V to 1.95 V - - - 0.6 5.5 6.1 ns VCC(B) = 2.3 V to 2.7 V - - - 0.7 4.1 4.6 ns VCC(B) = 3.0 V to 3.6 V - - - 1.7 4.7 5.2 ns VCC(B) = 0.8 V - 18.1 - - - - ns VCC(B) = 1.1 V to 1.3 V - - - - 13.3 14.7 ns VCC(B) = 1.4 V to 1.6 V - - - - 9.1 10.1 ns VCC(B) = 1.65 V to 1.95 V - - - - 8.6 9.6 ns VCC(B) = 2.3 V to 2.7 V - - - - 6.7 7.5 ns - - - - 7.1 7.9 ns VCC(B) = 0.8 V - 15.2 - - - - ns VCC(B) = 1.1 V to 1.3 V - - - - 11.8 13.1 ns DIR to A; see Figure 6 [3] VCC(B) = 1.1 V to 3.6 V DIR to B; see Figure 6 enable time DIR to A; see Figure 6 [3] [4][5] VCC(B) = 3.0 V to 3.6 V DIR to B; see Figure 6 [4][5] VCC(B) = 1.4 V to 1.6 V - - - - 9.2 10.2 ns VCC(B) = 1.65 V to 1.95 V - - - - 8.4 9.3 ns VCC(B) = 2.3 V to 2.7 V - - - - 7.5 8.3 ns VCC(B) = 3.0 V to 3.6 V - - - - 7.1 7.9 ns 74AVCH2T45_1 Product data sheet Unit Min VCC(B) = 0.8 V ten −40 °C to +125 °C Typ[1] © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 18 of 29 74AVCH2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7. Symbol Parameter 25 °C Conditions −40 °C to +125 °C Unit Min Typ[1] Max Min Max (85 °C) Max (125 °C) VCC(A) = VCC(B) = 0.8 V - 1 - - - - pF VCC(A) = VCC(B) = 1.2 V - 2 - - - - pF VCC(A) = VCC(B) = 1.5 V - 2 - - - - pF VCC(A) = VCC(B) = 1.8 V - 2 - - - - pF VCC(A) = VCC(B) = 2.5 V - 2 - - - - pF - 2 - - - - pF VCC(A) = VCC(B) = 0.8V - 9 - - - - pF VCC(A) = VCC(B) = 1.2 V - 11 - - - - pF VCC(A) = VCC(B) = 1.5 V - 11 - - - - pF VCC(A) = VCC(B) = 1.8 V - 12 - - - - pF VCC(A) = VCC(B) = 2.5 V - 14 - - - - pF VCC(A) = VCC(B) = 3.3 V - 17 - - - - pF Power dissipation capacitance power dissipation capacitance CPD A port: (direction A to B); B port: (direction B to A) [6][7] VCC(A) = VCC(B) = 3.3 V A port: (direction B to A); B port: (direction A to B) [1] All typical values are measured at nominal VCC(A) and VCC(B). [2] tpd is the same as tPLH and tPHL. [3] tdis is the same as tPLZ and tPHZ. [4] ten is the same as tPZL and tPZH. [6][7] [5] The enable time is a calculated value using the formula shown in Section 13.4 “Enable times”. [6] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. [7] fi = 10 MHz; VI = GND to VCC; tr = tf = 1 ns; CL = 0 pF; RL = ∞ Ω. 74AVCH2T45_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 19 of 29 74AVCH2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state 12. Waveforms VI VM A, B input GND t PLH t PHL VOH B, A output VM 001aae967 VOL Measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output load. Fig 5. The data input (A, B) to output (B, A) propagation delay times VI DIR input VM GND t PLZ output LOW-to-OFF OFF-to-LOW t PZL VCCO VM VX VOL t PHZ VOH t PZH VY output HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs disabled outputs enabled 001aae968 Measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output load. Fig 6. Enable and disable times Table 9. Measurement points Supply voltage Input[1] Output[2] VCC(A), VCC(B) VM VM VX VY 1.1 V to 1.6 V 0.5 × VCCI 0.5 × VCCO VOL + 0.1 V VOH − 0.1 V 1.65 V to 2.7 V 0.5 × VCCI 0.5 × VCCO VOL + 0.15 V VOH − 0.15 V 3.0 V to 3.6 V 0.5 × VCCI 0.5 × VCCO VOL + 0.3 V VOH − 0.3 V [1] VCCI is the supply voltage associated with the data input port. [2] VCCO is the supply voltage associated with the output port. 74AVCH2T45_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 20 of 29 74AVCH2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VEXT VCC VI PULSE GENERATOR RL VO DUT RT CL RL 001aae331 Test data is given in Table 10. RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance. VEXT = External voltage for measuring switching times. Fig 7. Load circuitry for switching times Table 10. Test data Supply voltage Input VCC(A), VCC(B) VI[1] ∆t/∆V[2] Load CL RL tPLH, tPHL tPZH, tPHZ tPZL, tPLZ[3] 1.1 V to 1.6 V VCCI ≤ 1.0 ns/V 15 pF 2 kΩ open GND 2 × VCCO 1.65 V to 2.7 V VCCI ≤ 1.0 ns/V 15 pF 2 kΩ open GND 2 × VCCO 3.0 V to 3.6 V VCCI ≤ 1.0 ns/V 15 pF 2 kΩ open GND 2 × VCCO [1] VCCI is the supply voltage associated with the data input port. [2] dV/dt ≥ 1.0 V/ns [3] VCCO is the supply voltage associated with the output port. VEXT 74AVCH2T45_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 21 of 29 74AVCH2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state 13. Application information 13.1 Unidirectional logic level-shifting application The circuit given in Figure 8 is an example of the 74AVCH2T45 being used in an unidirectional logic level-shifting application. VCC1 VCC(A) VCC1 VCC2 74AVCH2T45 1A 2A GND VCC1 1 8 2 7 3 6 4 5 VCC(B) VCC2 1B 2B DIR VCC2 system-2 system-1 001aag585 Fig 8. Unidirectional logic level-shifting application Table 11. Unidirectional logic level-shifting application Pin Name Function Description 1 VCC(A) VCC1 supply voltage of system-1 (0.8 V to 3.6 V) 2 1A OUT1 output level depends on VCC1 voltage 3 2A OUT2 output level depends on VCC1 voltage 4 GND GND device GND 5 DIR DIR the GND (LOW level) determines B port to A port direction 6 2B IN2 input threshold value depends on VCC2 voltage 7 1B IN1 input threshold value depends on VCC2 voltage 8 VCC(B) VCC2 supply voltage of system-2 (0.8 V to 3.6 V) 74AVCH2T45_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 22 of 29 74AVCH2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state 13.2 Bidirectional logic level-shifting application Figure 9 shows the 74AVCH2T45 being used in a bidirectional logic level-shifting application. Since the device does not have an output enable (OE) pin, the system designer should take precautions to avoid bus contention between system-1 and system-2 when changing directions. VCC1 VCC1 VCC2 VCC2 74AVCH2T45 VCC(A) I/O-1 1A 2A GND 8 1 2 7 3 6 4 5 VCC(B) I/O-2 1B 2B DIR DIR CTRL DIR CTRL system-2 system-1 001aag586 Fig 9. Bidirectional logic level-shifting application Table 12 gives a sequence that will illustrate data transmission from system-1 to system-2 and then from system-2 to system-1. Table 12. Bidirectional logic level-shifting application[1] State DIR CTRL I/O-1 I/O-2 Description 1 H output input system-1 data to system-2 2 H Z Z system-2 is getting ready to send data to system-1. I/O-1 and I/O-2 are disabled. The bus-line state depends on bus hold. 3 L Z Z DIR bit is set LOW. I/O-1 and I/O-2 still are disabled. The bus-line state depends on bus hold. 4 L input output system-2 data to system-1 [1] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state. 74AVCH2T45_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 23 of 29 74AVCH2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state 13.3 Power-up considerations The device is designed such that no special power-up sequence is required other than GND being applied first. Table 13. Typical total supply current (ICC(A) + ICC(B)) VCC(A) VCC(B) Unit 0V 0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 0V 0 0.1 0.1 0.1 0.1 0.1 0.1 µA 0.8 V 0.1 0.1 0.1 0.1 0.1 0.7 2.3 µA 1.2 V 0.1 0.1 0.1 0.1 0.1 0.3 1.4 µA 1.5 V 0.1 0.1 0.1 0.1 0.1 0.1 0.9 µA 1.8 V 0.1 0.1 0.1 0.1 0.1 0.1 0.5 µA 2.5 V 0.1 0.7 0.3 0.1 0.1 0.1 0.1 µA 3.3 V 0.1 2.3 1.4 0.9 0.5 0.1 0.1 µA 13.4 Enable times Calculate the enable times for the 74AVCH2T45 using the following formulas: • ten (DIR to nA) = tdis (DIR to nB) + tpd (nB to nA) • ten (DIR to nB) = tdis (DIR to nA) + tpd (nA to nB) In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is switched until an output is expected. For example, if the 74AVCH2T45 initially is transmitting from A to B, then the DIR bit is switched, the B port of the device must be disabled before presenting it with an input. After the B port has been disabled, an input signal applied to it appears on the corresponding A port after the specified propagation delay. 74AVCH2T45_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 24 of 29 74AVCH2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state 14. Package outline VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm D E SOT765-1 A X c y HE v M A Z 5 8 Q A A2 A1 pin 1 index (A3) θ Lp 1 4 e L detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(2) e HE L Lp Q v w y Z(1) θ mm 1 0.15 0.00 0.85 0.60 0.12 0.27 0.17 0.23 0.08 2.1 1.9 2.4 2.2 0.5 3.2 3.0 0.4 0.40 0.15 0.21 0.19 0.2 0.13 0.1 0.4 0.1 8° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT765-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 02-06-07 MO-187 Fig 10. Package outline SOT765-1 (VSSOP8) 74AVCH2T45_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 25 of 29 74AVCH2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm 1 2 SOT833-1 b 4 3 4× (2) L L1 e 8 7 6 e1 5 e1 e1 8× A (2) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A (1) max A1 max b D E e e1 L L1 mm 0.5 0.04 0.25 0.17 2.0 1.9 1.05 0.95 0.6 0.5 0.35 0.27 0.40 0.32 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT833-1 --- MO-252 --- EUROPEAN PROJECTION ISSUE DATE 04-07-22 04-11-09 Fig 11. Package outline SOT833-1 (XSON8) 74AVCH2T45_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 26 of 29 74AVCH2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state 15. Abbreviations Table 14. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 16. Revision history Table 15. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AVCH2T45_1 20070703 Product data sheet - - 74AVCH2T45_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 27 of 29 74AVCH2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state 17. Legal information 17.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 17.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 18. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: [email protected] 74AVCH2T45_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 28 of 29 74AVCH2T45 NXP Semiconductors Dual-bit, dual-supply voltage level translator/transceiver; 3-state 19. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 13.1 13.2 13.3 13.4 14 15 16 17 17.1 17.2 17.3 17.4 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Application information. . . . . . . . . . . . . . . . . . 22 Unidirectional logic level-shifting application. . 22 Bidirectional logic level-shifting application. . . 23 Power-up considerations . . . . . . . . . . . . . . . . 24 Enable times . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 25 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 27 Legal information. . . . . . . . . . . . . . . . . . . . . . . 28 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 28 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Contact information. . . . . . . . . . . . . . . . . . . . . 28 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 3 July 2007 Document identifier: 74AVCH2T45_1