74LVC2T45; 74LVCH2T45 Dual supply translating transceiver; 3-state Rev. 03 — 19 January 2010 Product data sheet 1. General description The 74LVC2T45; 74LVCH2T45 are dual bit, dual supply translating transceivers with 3-state outputs that enable bidirectional level translation. They feature two data input-output ports (nA and nB), a direction control input (DIR) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 1.2 V and 5.5 V making the device suitable for translating between any of the low voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V). Pins nA and DIR are referenced to VCC(A) and pins nB are referenced to VCC(B). A HIGH on DIR allows transmission from nA to nB and a LOW on DIR allows transmission from nB to nA. The devices are fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both A port and B port are in the high-impedance OFF-state. Active bus hold circuitry in the 74LVCH2T45 holds unused or floating data inputs at a valid logic level. 2. Features Wide supply voltage range: VCC(A): 1.2 V to 5.5 V VCC(B): 1.2 V to 5.5 V High noise immunity Complies with JEDEC standards: JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8C (2.7 V to 3.6 V) JESD36 (4.5 V to 5.5 V) ESD protection: HBM JESD22-A114E Class 3A exceeds 4000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101C exceeds 1000 V Maximum data rates: 420 Mbps (3.3 V to 5.0 V translation) 210 Mbps (translate to 3.3 V)) 140 Mbps (translate to 2.5 V) 75 Mbps (translate to 1.8 V) 60 Mbps (translate to 1.5 V) 74LVC2T45; 74LVCH2T45 NXP Semiconductors Dual supply translating transceiver; 3-state Suspend mode Latch-up performance exceeds 100 mA per JESD 78 Class II ±24 mA output drive (VCC = 3.0 V) Inputs accept voltages up to 5.5 V Low power consumption: 16 μA maximum ICC IOFF circuitry provides partial Power-down mode operation Multiple package options Specified from −40 °C to +85 °C and −40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number 74LVC2T45DC Package Temperature range Name Description −40 °C to +125 °C VSSOP8 plastic very thin shrink small outline package; 8 leads; SOT765-1 body width 2.3 mm −40 °C to +125 °C XSON8 plastic extremely thin small outline package; no leads; SOT833-1 8 terminals; body 1 × 1.95 × 0.5 mm −40 °C to +125 °C XSON8U plastic extremely thin small outline package; no leads; SOT996-2 8 terminals; UTLP based; body 3 × 2 × 0.5 mm −40 °C to +125 °C XQFN8U plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 × 1.6 × 0.5 mm 74LVCH2T45DC 74LVC2T45GT 74LVCH2T45GT 74LVC2T45GD 74LVCH2T45GD 74LVC2T45GM 74LVCH2T45GM Version SOT902-1 4. Marking Table 2. Marking Type number Marking code 74LVC2T45DC V45 74LVCH2T45DC X45 74LVC2T45GT V45 74LVCH2T45GT X45 74LVC2T45GD V45 74LVCH2T45GD X45 74LVC2T45GM V45 74LVCH2T45GM X45 74LVC_LVCH2T45_3 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 03 — 19 January 2010 2 of 32 74LVC2T45; 74LVCH2T45 NXP Semiconductors Dual supply translating transceiver; 3-state 5. Functional diagram DIR 5 DIR 1A 2 1A 7 1B 1B 2A 3 2A 6 2B 2B VCC(A) VCC(B) VCC(A) VCC(B) 001aag577 Fig 1. 001aag578 Logic symbol Fig 2. Logic diagram 6. Pinning information 6.1 Pinning 74LVC2T45 74LVCH2T45 VCC(A) 1 8 VCC(B) 1A 2 7 1B 2A 3 6 2B GND 4 5 DIR 74LVC2T45 74LVCH2T45 VCC(A) 1 8 VCC(B) 1A 2 7 1B 2A 3 6 2B GND 4 5 DIR 001aai905 Transparent top view 001aai904 Fig 3. Pin configuration SOT765-1 (VSSOP8) Fig 4. Pin configuration SOT833-1 (XSON8) 74LVC_LVCH2T45_3 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 03 — 19 January 2010 3 of 32 74LVC2T45; 74LVCH2T45 NXP Semiconductors Dual supply translating transceiver; 3-state VCC(B) 74LVC2T45 74LVCH2T45 74LVC2T45 74LVCH2T45 1 8 VCC(B) 1A 2 7 1B 2A 3 6 2B GND 4 5 DIR 1 2B DIR 7 VCC(A) 2 6 1A 3 5 2A GND 4 VCC(A) 1B 8 terminal 1 index area 001aaj617 Transparent top view Fig 5. 001aai906 Transparent top view Pin configuration SOT996-2 (XSON8U) Fig 6. Pin configuration SOT902-1 (XQFN8U) 6.2 Pin description Table 3. Pin description Symbol Pin Description SOT765-1, SOT833-1 and SOT996-2 SOT902-1 VCC(A) 1 7 supply voltage A (port A and DIR) 1A 2 6 data input or output 2A 3 5 data input or output GND 4 4 ground (0 V) DIR 5 3 direction control 2B 6 2 data input or output 1B 7 1 data input or output VCC(B) 8 8 supply voltage B (port B) 7. Functional description Table 4. Function table[1] Supply voltage Input Input/output[2] VCC(A), VCC(B) DIR nA nB 1.2 V to 5.5 V L nA = nB input 1.2 V to 5.5 V H input nB = nA GND[3] X Z Z [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. [2] The input circuit of the data I/O is always active. [3] When either VCC(A) or VCC(B) is at GND level, the device goes into suspend mode. 74LVC_LVCH2T45_3 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 03 — 19 January 2010 4 of 32 74LVC2T45; 74LVCH2T45 NXP Semiconductors Dual supply translating transceiver; 3-state 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC(A) VCC(B) IIK input clamping current Conditions Min Max Unit supply voltage A −0.5 +6.5 V supply voltage B −0.5 +6.5 V −50 - mA −0.5 +6.5 V VI < 0 V [1] VI input voltage IOK output clamping current VO < 0 V VO output voltage Active mode −50 - mA [1][2][3] −0.5 VCCO + 0.5 V Suspend or 3-state mode [1] −0.5 +6.5 V [2] - ±50 mA - 100 mA −100 - mA −65 +150 °C - 250 mW IO output current VO = 0 V to VCCO ICC supply current ICC(A) or ICC(B) IGND ground current Tstg storage temperature Ptot [1] total power dissipation Tamb = −40 °C to +125 °C The minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] VCCO is the supply voltage associated with the output port. [3] VCCO + 0.5 V should not exceed 6.5 V. [4] [4] For VSSOP8 packages: above 110 °C the value of Ptot derates linearly with 8.0 mW/K. For XSON8, XSON8U and XQFN8U packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K. 9. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter VCC(A) Conditions Min Max Unit supply voltage A 1.2 5.5 V VCC(B) supply voltage B 1.2 5.5 V VI input voltage 0 5.5 V VO output voltage 0 VCCO V 0 5.5 V −40 +125 °C Active mode [1] Suspend or 3-state mode Tamb Δt/ΔV ambient temperature input transition rise and fall rate VCCI = 1.2 V - 20 ns/V VCCI = 1.4 V to 1.95 V - 20 ns/V VCCI = 2.3 V to 2.7 V - 20 ns/V VCCI = 3 V to 3.6 V - 10 ns/V VCCI = 4.5 V to 5.5 V - 5 ns/V [1] VCCO is the supply voltage associated with the output port. [2] VCCI is the supply voltage associated with the input port. 74LVC_LVCH2T45_3 Product data sheet [2] © NXP B.V. 2010. All rights reserved. Rev. 03 — 19 January 2010 5 of 32 74LVC2T45; 74LVCH2T45 NXP Semiconductors Dual supply translating transceiver; 3-state 10. Static characteristics Table 7. Typical static characteristics at Tamb = 25 °C At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VOH HIGH-level output voltage Conditions VI = VIH or VIL Min Typ Max Unit - 1.09 - V [1] - 0.07 - V - - ±1 μA [1] IO = −3 mA; VCCO = 1.2 V VOL LOW-level output voltage VI = VIH or VIL IO = 3 mA; VCCO = 1.2 V II input leakage current DIR input; VI = 0 V to 5.5 V; VCCI = 1.2 V to 5.5 V [2] IBHL bus hold LOW current A or B port; VI = 0.42 V; VCCI = 1.2 V [2] - 19 - μA A or B port; VI = 0.78 V; VCCI = 1.2 V [2] - −19 - μA - 19 - μA IBHH bus hold HIGH current IBHLO bus hold LOW overdrive current A or B port; VCCI = 1.2 V [2][3] IBHHO bus hold HIGH overdrive current A or B port; VCCI = 1.2 V [2][3] - −19 - μA IOZ OFF-state output current A or B port; VO = 0 V or VCCO; VCCO = 1.2 V to 5.5 V [1] - - ±1 μA IOFF power-off leakage current A port; VI or VO = 0 V to 5.5 V; VCC(A) = 0 V; VCC(B) = 1.2 V to 5.5 V - - ±1 μA B port; VI or VO = 0 V to 5.5 V; VCC(B) = 0 V; VCC(A) = 1.2 V to 5.5 V - - ±1 μA CI input capacitance DIR input; VI = 0 V or 3.3 V; VCC(A) = VCC(B) = 3.3 V - 2.2 - pF CI/O input/output capacitance A and B port; suspend mode; VO = 3.3 V or 0 V; VCC(A) = VCC(B) = 3.3 V - 6.0 - pF [1] VCCO is the supply voltage associated with the output port. [2] VCCI is the supply voltage associated with the data input port. [3] To guarantee the node switches, an external driver must source/sink at least IBHLO / IBHHO when the input is in the range VIL to VIH. 74LVC_LVCH2T45_3 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 03 — 19 January 2010 6 of 32 74LVC2T45; 74LVCH2T45 NXP Semiconductors Dual supply translating transceiver; 3-state Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH HIGH-level input voltage −40 °C to +85 °C Conditions −40 °C to +125 °C Unit Min Max Min Max VCCI = 1.2 V 0.8VCCI - 0.8VCCI - V VCCI = 1.4 V to 1.95 V 0.65VCCI - 0.65VCCI - V VCCI = 2.3 V to 2.7 V 1.7 - 1.7 - V VCCI = 3.0 V to 3.6 V 2.0 - 2.0 - V VCCI = 4.5 V to 5.5 V 0.7VCCI - 0.7VCCI - V VCCI = 1.2 V 0.8VCC(A) - 0.8VCC(A) - V VCCI = 1.4 V to 1.95 V 0.65VCC(A) - 0.65VCC(A) - V VCCI = 2.3 V to 2.7 V 1.7 - 1.7 - V VCCI = 3.0 V to 3.6 V 2.0 - 2.0 - V VCCI = 4.5 V to 5.5 V 0.7VCC(A) - 0.7VCC(A) - V VCCI = 1.2 V - 0.2VCCI - 0.2VCCI V VCCI = 1.4 V to 1.95 V - 0.35VCCI - 0.35VCCI V VCCI = 2.3 V to 2.7 V - 0.7 - 0.7 V VCCI = 3.0 V to 3.6 V - 0.8 - 0.8 V VCCI = 4.5 V to 5.5 V - 0.3VCCI - 0.3VCCI V VCCI = 1.2 V - 0.2VCC(A) - 0.2VCC(A) V VCCI = 1.4 V to 1.95 V - 0.35VCC(A) - 0.35VCC(A) V VCCI = 2.3 V to 2.7 V - 0.7 - VCCI = 3.0 V to 3.6 V - 0.8 - VCCI = 4.5 V to 5.5 V - 0.3VCC(A) - VCCO − 0.1 - VCCO − 0.1 - V IO = −6 mA; VCCO = 1.4 V 1.0 - 1.0 - V IO = −8 mA; VCCO = 1.65 V 1.2 - 1.2 - V IO = −12 mA; VCCO = 2.3 V 1.9 - 1.9 - V IO = −24 mA; VCCO = 3.0 V 2.4 - 2.4 - V IO = −32 mA; VCCO = 4.5 V 3.8 - 3.8 - V [2] data input DIR input VIL LOW-level input voltage [2] data input DIR input VOH HIGH-level output voltage V 0.8 V 0.3VCC(A) V VI = VIH IO = −100 μA; VCCO = 1.2 V to 4.5 V [1] 74LVC_LVCH2T45_3 Product data sheet 0.7 © NXP B.V. 2010. All rights reserved. Rev. 03 — 19 January 2010 7 of 32 74LVC2T45; 74LVCH2T45 NXP Semiconductors Dual supply translating transceiver; 3-state Table 8. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VOL LOW-level output voltage −40 °C to +85 °C Conditions Min Max Min Max IO = 100 μA; VCCO = 1.2 V to 4.5 V - 0.1 - 0.1 V IO = 6 mA; VCCO = 1.4 V - 0.3 - 0.3 V IO = 8 mA; VCCO = 1.65 V - 0.45 - 0.45 V IO = 12 mA; VCCO = 2.3 V - 0.3 - 0.3 V IO = 24 mA; VCCO = 3.0 V - 0.55 - 0.55 V IO = 32 mA; VCCO = 4.5 V - 0.55 - 0.55 V - ±2 - ±10 μA 15 - 10 - μA VI = 0.58 V; VCCI = 1.65 V 25 - 20 - μA VI = 0.70 V; VCCI = 2.3 V 45 - 45 - μA VI = 0.80 V; VCCI = 3.0 V 100 - 80 - μA 100 - 100 - μA −15 - −10 - μA VI = 1.07 V; VCCI = 1.65 V −25 - −20 - μA VI = 1.60 V; VCCI = 2.3 V −45 - −45 - μA VI = 2.00 V; VCCI = 3.0 V −100 - −80 - μA VI = 3.15 V; VCCI = 4.5 V −100 - −100 - μA 125 - 125 - μA VI = VIL input leakage current IBHL bus hold LOW A or B port current VI = 0.49 V; VCCI = 1.4 V DIR input; VI = 0 V to 5.5 V; VCCI = 1.2 V to 5.5 V [2] VI = 1.35 V; VCCI = 4.5 V IBHLO bus hold HIGH A or B port current VI = 0.91 V; VCCI = 1.4 V [2] [2][3] bus hold LOW A or B port overdrive VCCI = 1.6 V current VCCI = 1.95 V 200 - 200 - μA VCCI = 2.7 V 300 - 300 - μA VCCI = 3.6 V 500 - 500 - μA 900 - 900 - μA −125 - −125 - μA −200 - −200 - μA VCCI = 2.7 V −300 - −300 - μA VCCI = 3.6 V −500 - −500 - μA VCCI = 5.5 V −900 - −900 - μA - ±2 - ±10 μA VCCI = 5.5 V IBHHO IOZ [2][3] bus hold HIGH A or B port overdrive VCCI = 1.6 V current VCCI = 1.95 V OFF-state output current A or B port; VO = 0 V or VCCO; VCCO = 1.2 V to 5.5 V [1] 74LVC_LVCH2T45_3 Product data sheet Unit [1] II IBHH −40 °C to +125 °C © NXP B.V. 2010. All rights reserved. Rev. 03 — 19 January 2010 8 of 32 74LVC2T45; 74LVCH2T45 NXP Semiconductors Dual supply translating transceiver; 3-state Table 8. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter IOFF power-off leakage current ICC −40 °C to +85 °C Conditions −40 °C to +125 °C Unit Min Max Min Max A port; VI or VO = 0 V to 5.5 V; VCC(A) = 0 V; VCC(B) = 1.2 V to 5.5 V - ±2 - ±10 μA B port; VI or VO = 0 V to 5.5 V; VCC(B) = 0 V; VCC(A) = 1.2 V to 5.5 V - ±2 - ±10 μA VCC(A), VCC(B) = 1.2 V to 5.5 V - 8 - 8 μA VCC(A), VCC(B) = 1.65 V to 5.5 V - 3 - 3 μA VCC(A) = 5.5 V; VCC(B) = 0 V - 2 - 2 μA VCC(A) = 0 V; VCC(B) = 5.5 V −2 - −2 - μA VCC(A), VCC(B) = 1.2 V to 5.5 V - 8 - 8 μA VCC(A), VCC(B) = 1.65 V to 5.5 V - 3 - 3 μA VCC(B) = 0 V; VCC(A) = 5.5 V −2 - −2 - μA VCC(B) = 5.5 V; VCC(A) = 0 V - 2 - 2 μA VCC(A), VCC(B) = 1.2 V to 5.5 V - 16 - 16 μA VCC(A), VCC(B) = 1.65 V to 5.5 V - 4 - 4 μA - 50 - 75 μA - 50 - 75 μA - 50 - 75 μA supply current A port; VI = 0 V or VCCI; IO = 0 A [2] B port; VI = 0 V or VCCI; IO = 0 A A plus B port (ICC(A) + ICC(B)); IO = 0 A; VI = 0 V or VCCI ΔICC additional per input; supply current VCC(A), VCC(B) = 3.0 V to 5.5 V A port; A port at VCC(A) − 0.6 V; DIR at VCC(A); B port = open [4] DIR input; DIR at VCC(A) − 0.6 V; A port at VCC(A) or GND; B port = open B port; B port at VCC(B) − 0.6 V; DIR at GND; A port = open [1] VCCO is the supply voltage associated with the output port. [2] VCCI is the supply voltage associated with the data input port. [4] [3] To guarantee the node switches, an external driver must source/sink at least IBHLO / IBHHO when the input is in the range VIL to VIH. [4] For non bus hold parts only (74LVC2T45). 74LVC_LVCH2T45_3 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 03 — 19 January 2010 9 of 32 74LVC2T45; 74LVCH2T45 NXP Semiconductors Dual supply translating transceiver; 3-state 11. Dynamic characteristics Table 9. Typical dynamic characteristics at VCC(A) = 1.2 V and Tamb = 25 °C Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9; for waveforms see Figure 7 and Figure 8. Symbol Parameter Conditions 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 5.0 V tPLH LOW to HIGH propagation delay A to B 10.6 8.1 7.0 5.8 5.3 5.1 ns B to A 10.6 9.5 9.0 8.5 8.3 8.2 ns tPHL HIGH to LOW propagation delay A to B 10.1 7.1 6.0 5.3 5.2 5.4 ns B to A 10.1 8.6 8.1 7.8 7.6 7.6 ns tPHZ HIGH to OFF-state propagation delay DIR to A 9.4 9.4 9.4 9.4 9.4 9.4 ns DIR to B 12.0 9.4 9.0 7.8 8.4 7.9 ns tPLZ LOW to OFF-state propagation delay DIR to A 7.1 7.1 7.1 7.1 7.1 7.1 ns 9.5 7.8 7.7 6.9 7.6 7.0 ns tPZH OFF-state to HIGH propagation delay DIR to A [1] 20.1 17.3 16.7 15.4 15.9 15.2 ns DIR to B [1] 17.7 15.2 14.1 12.9 12.4 12.2 ns DIR to A [1] 22.1 18.0 17.1 15.6 16.0 15.5 ns DIR to B [1] 19.5 16.5 15.4 14.7 14.6 14.8 ns tPZL [1] OFF-state to LOW propagation delay VCC(B) DIR to B Unit tPZH and tPZL are calculated values using the formula shown in Section 14.4 “Enable times”. Table 10. Typical dynamic characteristics at VCC(B) = 1.2 V and Tamb = 25 °C Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9; for waveforms see Figure 7 and Figure 8. Symbol Parameter Conditions VCC(A) Unit 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 5.0 V tPLH LOW to HIGH propagation delay A to B 10.6 9.5 9.0 8.5 8.3 8.2 ns B to A 10.6 8.1 7.0 5.8 5.3 5.1 ns tPHL HIGH to LOW propagation delay A to B 10.1 8.6 8.1 7.8 7.6 7.6 ns B to A 10.1 7.1 6.0 5.3 5.2 5.4 ns tPHZ HIGH to OFF-state propagation delay DIR to A 9.4 6.5 5.7 4.1 4.1 3.0 ns DIR to B 12.0 6.1 5.4 4.6 4.3 4.0 ns tPLZ LOW to OFF-state propagation delay DIR to A 7.1 4.9 4.5 3.2 3.4 2.5 ns tPZH tPZL [1] DIR to B 9.5 7.3 6.6 5.9 5.7 5.6 ns OFF-state to HIGH propagation delay DIR to A [1] 20.1 15.4 13.6 11.7 11.0 10.7 ns DIR to B [1] 17.7 14.4 13.5 11.7 11.7 10.7 ns OFF-state to LOW propagation delay DIR to A [1] 22.1 13.2 11.4 9.9 9.5 9.4 ns DIR to B [1] 19.5 15.1 13.8 11.9 11.7 10.6 ns tPZH and tPZL are calculated values using the formula shown in Section 14.4 “Enable times”. 74LVC_LVCH2T45_3 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 03 — 19 January 2010 10 of 32 74LVC2T45; 74LVCH2T45 NXP Semiconductors Dual supply translating transceiver; 3-state Table 11. Typical power dissipation capacitance at VCC(A) = VCC(B) and Tamb = 25 °C [1][2] Voltages are referenced to GND (ground = 0 V). Symbol Parameter CPD [1] power dissipation capacitance Conditions VCC(A) and VCC(B) Unit 1.8 V 2.5 V 3.3 V 5.0 V A port: (direction A to B); B port: (direction B to A) 2 3 3 4 pF A port: (direction B to A); B port: (direction A to B) 15 16 16 18 pF CPD is used to determine the dynamic power dissipation (PD in μW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. [2] fi = 10 MHz; VI = GND to VCC; tr = tf = 1 ns; CL = 0 pF; RL = ∞ Ω. Table 12. Dynamic characteristics for temperature range −40 °C to +85 °C Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9; for wave forms see Figure 7 and Figure 8. Symbol Parameter Conditions VCC(B) Unit 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5.0 V ± 0.5 V Min Max Min Max Min Max Min Max Min Max VCC(A) = 1.4 V to 1.6 V tPLH tPHL tPHZ tPLZ tPZH tPZL LOW to HIGH propagation delay A to B 2.8 21.3 2.4 17.6 2.0 13.5 1.7 11.8 1.6 10.5 ns B to A 2.8 21.3 2.6 19.1 2.3 14.9 2.3 12.4 2.2 12.0 ns HIGH to LOW propagation delay A to B 2.6 19.3 2.2 15.3 1.8 11.8 1.7 10.9 1.7 10.8 ns B to A 2.6 19.3 2.4 17.3 2.3 13.2 2.2 11.3 2.3 11.0 HIGH to OFF-state DIR to A propagation delay DIR to B 3.0 18.7 3.0 18.7 3.0 18.7 3.0 18.7 3.0 18.7 ns 3.5 24.8 3.5 23.6 3.0 11.0 3.3 11.3 2.8 10.3 ns LOW to OFF-state propagation delay 2.4 11.4 2.4 11.4 2.4 11.4 2.4 11.4 2.4 11.4 ns 9.4 ns DIR to A DIR to B ns 2.8 18.3 3.0 17.2 2.5 9.4 3.0 10.1 2.5 OFF-state to HIGH DIR to A propagation delay DIR to B [1] - 39.6 - 36.3 - 24.3 - 22.5 - 21.4 ns [1] - 32.7 - 29.0 - 24.9 - 23.2 - 21.9 ns OFF-state to LOW propagation delay DIR to A [1] - 44.1 - 40.9 - 24.2 - 22.6 - 21.3 ns DIR to B [1] - 38.0 - 34.0 - 30.5 - 29.6 - 29.5 ns VCC(A) = 1.65 V to 1.95 V tPLH LOW to HIGH propagation delay A to B 2.6 19.1 2.2 17.7 2.2 9.3 1.7 7.2 1.4 6.8 B to A 2.4 17.6 2.2 17.7 2.3 16.0 2.1 15.5 1.9 15.1 ns tPHL HIGH to LOW propagation delay A to B 2.4 17.3 2.0 14.3 1.6 8.5 1.8 7.1 1.7 7.0 B to A 2.2 15.3 2.0 14.3 2.1 12.9 2.0 12.6 1.8 12.2 ns tPHZ HIGH to OFF-state DIR to A propagation delay DIR to B 2.9 17.1 2.9 17.1 2.9 17.1 2.9 17.1 2.9 17.1 ns 3.2 24.1 3.2 21.9 2.7 11.5 3.0 10.3 2.5 8.2 LOW to OFF-state propagation delay DIR to A 2.4 10.5 2.4 10.5 2.4 10.5 2.4 10.5 2.4 10.5 ns DIR to B 2.5 17.6 2.6 16.0 2.2 9.2 2.7 8.4 2.4 7.1 tPLZ 74LVC_LVCH2T45_3 Product data sheet ns ns ns ns © NXP B.V. 2010. All rights reserved. Rev. 03 — 19 January 2010 11 of 32 74LVC2T45; 74LVCH2T45 NXP Semiconductors Dual supply translating transceiver; 3-state Table 12. Dynamic characteristics for temperature range −40 °C to +85 °C …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9; for wave forms see Figure 7 and Figure 8. Symbol Parameter Conditions VCC(B) Unit 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5.0 V ± 0.5 V tPZH tPZL Min Max Min Max Min Max Min Max Min OFF-state to HIGH DIR to A propagation delay DIR to B [1] - 35.2 - 33.7 - 25.2 - 23.9 - Max 22.2 ns [1] - 29.6 - 28.2 - 19.8 - 17.7 - 17.3 ns OFF-state to LOW propagation delay DIR to A [1] - 39.4 - 36.2 - 24.4 - 22.9 - 20.4 ns DIR to B [1] - 34.4 - 31.4 - 25.6 - 24.2 - 24.1 ns VCC(A) = 2.3 V to 2.7 V tPLH tPHL tPHZ tPLZ tPZH tPZL LOW to HIGH propagation delay A to B 2.3 17.9 2.3 16.0 1.5 8.5 1.3 6.2 1.1 4.8 ns B to A 2.0 13.5 2.2 9.3 1.5 8.5 1.4 8.0 1.0 7.5 ns HIGH to LOW propagation delay A to B 2.3 15.8 2.1 12.9 1.4 7.5 1.3 5.4 0.9 4.6 ns B to A 1.8 11.8 1.9 8.5 1.4 7.5 1.3 7.0 0.9 6.2 ns HIGH to OFF-state DIR to A propagation delay DIR to B 2.1 8.1 2.1 8.1 2.1 8.1 2.1 8.1 2.1 8.1 ns 3.0 22.5 3.0 21.4 2.5 11.0 2.8 9.3 2.3 6.9 ns LOW to OFF-state propagation delay DIR to A 1.7 5.8 1.7 5.8 1.7 5.8 1.7 5.8 1.7 5.8 ns DIR to B 2.3 14.6 2.5 13.2 2.0 9.0 2.5 8.4 1.8 5.8 ns OFF-state to HIGH DIR to A propagation delay DIR to B [1] - 28.1 - 22.5 - 17.5 - 16.4 - 13.3 ns [1] - 23.7 - 21.8 - 14.3 - 12.0 - 10.6 ns OFF-state to LOW propagation delay DIR to A [1] - 34.3 - 29.9 - 18.5 - 16.3 - 13.1 ns DIR to B [1] - 23.9 - 21.0 - 15.6 - 13.5 - 12.7 ns 17.1 2.1 15.5 1.4 8.0 0.8 5.6 0.7 4.4 ns VCC(A) = 3.0 V to 3.6 V tPLH LOW to HIGH propagation delay A to B 2.3 B to A 1.7 11.8 1.7 7.2 1.3 6.2 0.7 5.6 0.6 5.4 ns tPHL HIGH to LOW propagation delay A to B 2.2 15.6 2.0 12.6 1.3 7.0 0.8 5.0 0.7 4.0 ns B to A 1.7 10.9 1.8 7.1 1.3 5.4 0.8 5.0 0.7 4.5 ns tPHZ HIGH to OFF-state DIR to A propagation delay DIR to B 2.3 7.3 2.3 7.3 2.3 7.3 2.3 7.3 2.7 7.3 ns 2.9 18.0 2.9 16.5 2.3 10.1 2.7 8.6 2.2 6.3 ns tPLZ LOW to OFF-state propagation delay 2.0 5.6 2.0 5.6 2.0 5.6 2.0 5.6 2.0 5.6 ns 4.9 ns tPZH tPZL DIR to A DIR to B 2.3 13.6 2.4 12.5 1.9 7.8 2.3 7.1 1.7 OFF-state to HIGH DIR to A propagation delay DIR to B [1] - 25.4 - 19.7 - 14.0 - 12.7 - 10.3 ns [1] - 22.7 - 21.1 - 13.6 - 11.2 - 10.0 ns OFF-state to LOW propagation delay DIR to A [1] - 28.9 - 23.6 - 15.5 - 13.6 - 10.8 ns DIR to B [1] - 22.9 - 19.9 - 14.3 - 12.3 - 11.3 ns VCC(A) = 4.5 V to 5.5 V tPLH tPHL tPHZ LOW to HIGH propagation delay A to B 2.2 16.6 1.9 15.1 1.0 7.5 0.7 5.4 0.5 3.9 ns B to A 1.6 10.5 1.4 6.8 1.0 4.8 0.7 4.4 0.5 3.9 ns HIGH to LOW propagation delay A to B 2.3 15.3 1.8 12.2 1.0 6.2 0.7 4.5 0.5 3.5 ns B to A 1.7 10.8 1.7 7.0 0.9 4.6 0.7 4.0 0.5 3.5 ns 1.7 5.4 1.7 5.4 1.7 5.4 1.7 5.4 1.7 5.4 ns 2.9 17.3 2.9 16.1 2.3 9.7 2.7 8.0 2.5 5.7 ns HIGH to OFF-state DIR to A propagation delay DIR to B 74LVC_LVCH2T45_3 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 03 — 19 January 2010 12 of 32 74LVC2T45; 74LVCH2T45 NXP Semiconductors Dual supply translating transceiver; 3-state Table 12. Dynamic characteristics for temperature range −40 °C to +85 °C …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9; for wave forms see Figure 7 and Figure 8. Symbol Parameter Conditions VCC(B) Unit 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5.0 V ± 0.5 V tPLZ tPZH tPZL [1] LOW to OFF-state propagation delay DIR to A DIR to B Min Max Min Max Min Max Min Max Min Max 1.4 3.7 1.4 3.7 1.3 3.7 1.0 3.7 0.9 3.7 ns 2.3 13.1 2.4 12.1 1.9 7.4 2.3 7.0 1.8 4.5 ns OFF-state to HIGH DIR to A propagation delay DIR to B [1] - 23.6 - 18.9 - 12.2 - 11.4 - 8.4 ns [1] - 20.3 - 18.8 - 11.2 - 9.1 - 7.6 ns OFF-state to LOW propagation delay DIR to A [1] - 28.1 - 23.1 - 14.3 - 12.0 - 9.2 ns DIR to B [1] - 20.7 - 17.6 - 11.6 - 9.9 - 8.9 ns tPZH and tPZL are calculated values using the formula shown in Section 14.4 “Enable times”. Table 13. Dynamic characteristics for temperature range −40 °C to +125 °C Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9; for wave forms see Figure 7 and Figure 8. Symbol Parameter Conditions VCC(B) Unit 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5.0 V ± 0.5 V Min Max Min Max Min Max Min Max Min Max VCC(A) = 1.4 V to 1.6 V tPLH LOW to HIGH propagation delay A to B 2.5 23.5 2.1 19.4 1.8 14.9 1.5 13.0 1.4 11.6 ns B to A 2.5 23.5 2.3 21.1 2.0 16.4 2.0 13.7 1.9 13.2 ns tPHL HIGH to LOW propagation delay A to B 2.3 21.3 1.9 16.9 1.6 13.0 1.5 12.0 1.5 11.9 B to A 2.3 21.3 2.1 19.1 2.0 14.6 1.9 12.5 2.0 12.1 ns 20.6 ns ns tPHZ HIGH to OFF-state DIR to A propagation delay DIR to B 2.7 20.6 2.7 20.6 2.7 20.6 2.7 20.6 2.7 3.1 27.3 3.1 26.0 2.7 12.1 2.9 12.5 2.5 11.4 tPLZ LOW to OFF-state propagation delay 2.1 12.6 2.1 12.6 2.1 12.6 2.1 12.6 2.1 12.6 ns tPZH tPZL DIR to A DIR to B ns 2.5 20.2 2.7 19.0 2.2 10.4 2.7 11.2 2.2 10.4 ns OFF-state to HIGH DIR to A propagation delay DIR to B [1] - 43.7 - 40.1 - 26.8 - 24.9 - 23.6 ns [1] - 36.1 - 32.0 - 27.5 - 25.6 - 24.2 ns OFF-state to LOW propagation delay DIR to A [1] - 48.6 - 45.1 - 26.7 - 25.0 - 23.5 ns DIR to B [1] - 41.9 - 37.5 - 33.6 - 32.6 - 32.5 ns VCC(A) = 1.65 V to 1.95 V tPLH tPHL tPHZ tPLZ tPZH LOW to HIGH propagation delay A to B 2.3 21.1 1.9 19.5 1.9 10.3 1.5 8.0 1.2 7.5 B to A 2.1 19.4 1.9 19.5 2.0 17.6 1.8 17.1 1.7 16.7 ns HIGH to LOW propagation delay A to B 2.1 19.1 1.8 15.8 1.4 9.4 1.6 7.9 1.5 7.7 B to A 1.9 16.9 1.8 15.8 1.8 14.2 1.8 13.9 1.6 13.5 ns HIGH to OFF-state DIR to A propagation delay DIR to B 2.6 18.9 2.6 18.9 2.6 18.9 2.6 18.9 2.6 18.9 ns 2.8 26.6 2.8 24.1 2.4 12.7 2.7 11.4 2.2 9.1 ns LOW to OFF-state propagation delay 2.1 11.6 2.1 11.6 2.1 11.6 2.1 11.6 2.1 11.6 ns 7.9 ns DIR to A DIR to B OFF-state to HIGH DIR to A propagation delay DIR to B ns 2.2 19.4 2.3 17.6 1.9 10.2 2.4 9.3 2.1 [1] - 38.8 - 37.1 - 27.8 - 26.4 - 24.6 ns [1] - 32.7 - 31.1 - 21.9 - 19.6 - 19.1 ns 74LVC_LVCH2T45_3 Product data sheet ns © NXP B.V. 2010. All rights reserved. Rev. 03 — 19 January 2010 13 of 32 74LVC2T45; 74LVCH2T45 NXP Semiconductors Dual supply translating transceiver; 3-state Table 13. Dynamic characteristics for temperature range −40 °C to +125 °C …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9; for wave forms see Figure 7 and Figure 8. Symbol Parameter Conditions VCC(B) Unit 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5.0 V ± 0.5 V tPZL OFF-state to LOW propagation delay Min Max Min Max Min Max Min Max Min DIR to A [1] - 43.5 - 39.9 - 26.9 - 25.3 - Max 22.6 ns DIR to B [1] - 38.0 - 34.7 - 28.3 - 26.8 - 26.6 ns VCC(A) = 2.3 V to 2.7 V tPLH tPHL tPHZ tPLZ tPZH tPZL LOW to HIGH propagation delay A to B 2.0 19.7 2.0 17.6 1.3 9.4 1.1 6.9 0.9 5.3 ns B to A 1.8 14.9 1.9 10.3 1.3 9.4 1.2 8.8 0.9 8.3 ns HIGH to LOW propagation delay A to B 2.0 17.4 1.8 14.2 1.2 8.3 1.1 6.0 0.8 5.1 ns B to A 1.6 13.0 1.7 9.4 1.2 8.3 1.1 7.7 0.8 6.9 ns HIGH to OFF-state DIR to A propagation delay DIR to B 1.8 9.0 1.8 9.0 1.8 9.0 1.8 9.0 1.8 9.0 ns 2.7 24.8 2.7 23.6 2.2 12.1 2.5 10.3 2.0 7.6 ns LOW to OFF-state propagation delay 1.5 6.4 1.5 6.4 1.5 6.4 1.5 6.4 1.5 6.4 ns 6.4 ns DIR to A DIR to B 2.0 16.1 2.2 14.6 1.8 9.9 2.2 9.3 1.6 OFF-state to HIGH DIR to A propagation delay DIR to B [1] - 31.0 - 24.9 - 19.3 - 18.1 - 14.7 ns [1] - 26.1 - 24.0 - 15.8 - 13.3 - 11.7 OFF-state to LOW propagation delay DIR to A [1] - 37.8 - 33.0 - 20.4 - 18.0 - 14.5 ns DIR to B [1] - 26.4 - 23.2 - 17.3 - 15.0 - 14.1 ns ns VCC(A) = 3.0 V to 3.6 V tPLH LOW to HIGH propagation delay A to B 2.0 18.9 1.8 17.1 1.2 8.8 0.7 6.2 0.6 4.9 ns B to A 1.5 13.0 1.5 8.0 1.1 6.9 0.6 6.2 0.5 6.0 ns tPHL HIGH to LOW propagation delay A to B 1.9 17.2 1.8 13.9 1.1 7.7 0.7 5.5 0.6 4.4 ns B to A 1.5 12.0 1.6 7.9 1.1 6.0 0.7 5.5 0.6 5.0 ns tPHZ HIGH to OFF-state DIR to A propagation delay DIR to B 2.0 8.1 2.0 8.1 2.0 8.1 2.0 8.1 2.4 8.1 ns 2.6 19.8 2.6 18.2 2.0 11.2 2.4 9.5 1.9 7.0 ns tPLZ LOW to OFF-state propagation delay 1.8 6.2 1.8 6.2 1.8 6.2 1.8 6.2 1.8 6.2 ns 2.0 15.0 2.1 13.8 1.7 8.6 2.0 7.9 1.5 5.4 ns tPZH OFF-state to HIGH DIR to A propagation delay DIR to B [1] - 28.0 - 21.8 - 15.5 - 14.1 - 11.4 ns [1] - 25.1 - 23.3 - 15.0 - 12.4 - 11.1 ns OFF-state to LOW propagation delay DIR to A [1] - 31.8 - 26.1 - 17.2 - 15.0 - 12.0 ns DIR to B [1] - 25.3 - 22.0 - 15.8 - 13.6 - 12.5 ns tPZL DIR to A DIR to B VCC(A) = 4.5 V to 5.5 V tPLH tPHL tPHZ tPLZ LOW to HIGH propagation delay A to B 1.9 18.3 1.7 16.7 0.9 8.3 0.6 6.0 0.4 4.3 ns B to A 1.4 11.6 1.2 7.5 0.9 5.3 0.6 4.9 0.4 4.3 ns HIGH to LOW propagation delay A to B 2.0 16.9 1.6 13.5 0.9 6.9 0.6 5.0 0.4 3.9 ns B to A 1.5 11.9 1.5 7.7 0.8 5.1 0.6 4.4 0.4 3.9 ns HIGH to OFF-state DIR to A propagation delay DIR to B 1.5 6.0 1.5 6.0 1.5 6.0 1.5 6.0 1.5 6.0 ns 2.6 19.1 2.6 17.8 2.0 10.7 2.4 8.8 2.2 6.3 ns LOW to OFF-state propagation delay DIR to A 1.2 4.1 1.2 4.1 1.1 4.1 0.9 4.1 0.8 4.1 ns DIR to B 2.0 14.5 2.1 13.4 1.7 8.2 2.0 7.7 1.6 5.0 ns 74LVC_LVCH2T45_3 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 03 — 19 January 2010 14 of 32 74LVC2T45; 74LVCH2T45 NXP Semiconductors Dual supply translating transceiver; 3-state Table 13. Dynamic characteristics for temperature range −40 °C to +125 °C …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9; for wave forms see Figure 7 and Figure 8. Symbol Parameter Conditions VCC(B) Unit 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5.0 V ± 0.5 V tPZH tPZL [1] Min Max Min Max Min Max Min Max Min Max OFF-state to HIGH DIR to A propagation delay DIR to B [1] - 26.1 - 20.9 - 13.5 - 12.6 - 9.3 ns [1] - 22.4 - 20.8 - 12.4 - 10.1 - 8.4 ns OFF-state to LOW propagation delay DIR to A [1] - 31.0 - 25.5 - 15.8 - 13.2 - 10.2 ns DIR to B [1] - 22.9 - 19.5 - 12.9 - 11.0 - 9.9 ns tPZH and tPZL are calculated values using the formula shown in Section 14.4 “Enable times”. 12. Waveforms VI VM nA, nB input GND tPLH tPHL VOH nB, nA output VM 001aaj644 VOL Measurement points are given in Table 14. VOL and VOH are typical output voltage levels that occur with the output load. Fig 7. The data input (A, B) to output (B, A) propagation delay times VI DIR input VM GND t PLZ output LOW-to-OFF OFF-to-LOW t PZL VCCO VM VX VOL t PHZ VOH t PZH VY output HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs disabled outputs enabled 001aae968 Measurement points are given in Table 14. VOL and VOH are typical output voltage levels that occur with the output load. Fig 8. Enable and disable times 74LVC_LVCH2T45_3 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 03 — 19 January 2010 15 of 32 74LVC2T45; 74LVCH2T45 NXP Semiconductors Dual supply translating transceiver; 3-state Table 14. Measurement points Supply voltage Input[1] Output[2] VCC(A), VCC(B) VM VM VX VY 1.2 V to 1.6 V 0.5VCCI 0.5VCCO VOL + 0.1 V VOH − 0.1 V 1.65 V to 2.7 V 0.5VCCI 0.5VCCO VOL + 0.15 V VOH − 0.15 V 3.0 V to 5.5 V 0.5VCCI 0.5VCCO VOL + 0.3 V VOH − 0.3 V [1] VCCI is the supply voltage associated with the data input port. [2] VCCO is the supply voltage associated with the output port. VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VEXT VCC VI RL VO G DUT RT CL RL 001aae331 Test data is given in Table 15. RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance. VEXT = External voltage for measuring switching times. Fig 9. Load circuitry for switching times Table 15. Test data Supply voltage Input VCC(A), VCC(B) VI[1] Δt/ΔV[2] CL RL tPLH, tPHL tPZH, tPHZ tPZL, tPLZ[3] 1.2 V to 5.5 V VCCI ≤ 1.0 ns/V 15 pF 2 kΩ open GND 2VCCO [1] Load VEXT VCCI is the supply voltage associated with the data input port. [2] dV/dt ≥ 1.0 V/ns. [3] VCCO is the supply voltage associated with the output port. 74LVC_LVCH2T45_3 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 03 — 19 January 2010 16 of 32 74LVC2T45; 74LVCH2T45 NXP Semiconductors Dual supply translating transceiver; 3-state 13. Typical propagation delay characteristics 001aai907 14 tPHL (ns) 12 001aai908 14 tPLH (ns) 12 (1) (1) 10 10 (2) 8 (2) 8 (3) 6 (3) (4) (5) (6) 6 (4) (5) (6) 4 4 2 2 0 0 0 5 10 15 20 25 30 35 CL (pF) a. HIGH to LOW propagation delay (A to B) 001aai909 14 tPHL (ns) 12 0 5 10 15 20 25 30 35 CL (pF) b. LOW to HIGH propagation delay (A to B) 001aai910 14 tPLH (ns) 12 (1) (1) 10 (2) (3) 10 8 (4) (5) (6) 8 (2) (3) (4) (5) 6 6 4 4 2 2 0 (6) 0 0 5 10 15 20 25 30 35 CL (pF) c. HIGH to LOW propagation delay (B to A) 0 5 10 15 20 25 30 35 CL (pF) d. LOW to HIGH propagation delay (B to A) (1) VCC(B) = 1.2 V. (2) VCC(B) = 1.5 V. (3) VCC(B) = 1.8 V. (4) VCC(B) = 2.5 V. (5) VCC(B) = 3.3 V. (6) VCC(B) = 5.0 V. Fig 10. Typical propagation delay versus load capacitance; Tamb = 25 °C; VCC(A) = 1.2 V 74LVC_LVCH2T45_3 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 03 — 19 January 2010 17 of 32 74LVC2T45; 74LVCH2T45 NXP Semiconductors Dual supply translating transceiver; 3-state 001aai911 14 tPHL (ns) 12 001aai912 14 tPLH (ns) 12 (1) 10 10 (1) 8 8 (2) (2) (3) 6 6 (3) (4) (5) (6) (4) 4 4 (5) 2 2 (6) 0 0 0 5 10 15 20 25 30 35 CL (pF) a. HIGH to LOW propagation delay (A to B) 001aai913 14 tPHL (ns) 12 10 0 5 10 15 20 25 30 35 CL (pF) b. LOW to HIGH propagation delay (A to B) 001aai914 14 tPLH (ns) 12 10 (1) 8 (1) 8 6 (2) (3) (4) 6 (2) (3) (4) (5) (5) (6) (6) 4 4 2 2 0 0 0 5 10 15 20 25 30 35 CL (pF) c. HIGH to LOW propagation delay (B to A) 0 5 10 15 20 25 30 35 CL (pF) d. LOW to HIGH propagation delay (B to A) (1) VCC(B) = 1.2 V. (2) VCC(B) = 1.5 V. (3) VCC(B) = 1.8 V. (4) VCC(B) = 2.5 V. (5) VCC(B) = 3.3 V. (6) VCC(B) = 5.0 V. Fig 11. Typical propagation delay versus load capacitance; Tamb = 25 °C; VCC(A) = 1.5 V 74LVC_LVCH2T45_3 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 03 — 19 January 2010 18 of 32 74LVC2T45; 74LVCH2T45 NXP Semiconductors Dual supply translating transceiver; 3-state 001aai915 14 tPHL (ns) 12 001aai916 14 tPLH (ns) 12 (1) 10 10 (1) 8 8 (2) (2) 6 6 (3) 4 (4) (5) (6) (3) (4) 4 (5) (6) 2 2 0 0 0 5 10 15 20 25 30 35 CL (pF) a. HIGH to LOW propagation delay (A to B) 001aai917 14 tPHL (ns) 12 10 0 5 10 15 20 25 30 35 CL (pF) b. LOW to HIGH propagation delay (A to B) 001aai918 14 tPLH (ns) 12 10 8 8 (1) (1) 6 4 (2) (3) (4) (5) (6) 6 (2) (3) (4) (5) (6) 4 2 2 0 0 0 5 10 15 20 25 30 35 CL (pF) c. HIGH to LOW propagation delay (B to A) 0 5 10 15 20 25 30 35 CL (pF) d. LOW to HIGH propagation delay (B to A) (1) VCC(B) = 1.2 V. (2) VCC(B) = 1.5 V. (3) VCC(B) = 1.8 V. (4) VCC(B) = 2.5 V. (5) VCC(B) = 3.3 V. (6) VCC(B) = 5.0 V. Fig 12. Typical propagation delay versus load capacitance; Tamb = 25 °C; VCC(A) = 1.8 V 74LVC_LVCH2T45_3 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 03 — 19 January 2010 19 of 32 74LVC2T45; 74LVCH2T45 NXP Semiconductors Dual supply translating transceiver; 3-state 001aai919 14 tPHL (ns) 12 10 001aai920 14 tPLH (ns) 12 (1) 10 (1) 8 8 (2) (2) 6 6 (3) (3) 4 (4) (5) (6) 4 (4) (5) (6) 2 2 0 0 0 5 10 15 20 25 30 35 CL (pF) a. HIGH to LOW propagation delay (A to B) 001aai921 14 tPHL (ns) 12 0 8 8 20 25 (2) (3) (4) (5) (6) 30 35 CL (pF) 001aai922 (1) 6 (1) 2 15 14 tPLH (ns) 12 10 4 10 b. LOW to HIGH propagation delay (A to B) 10 6 5 (2) (3) (4) (5) (6) 4 2 0 0 0 5 10 15 20 25 30 35 CL (pF) c. HIGH to LOW propagation delay (B to A) 0 5 10 15 20 25 30 35 CL (pF) d. LOW to HIGH propagation delay (B to A) (1) VCC(B) = 1.2 V. (2) VCC(B) = 1.5 V. (3) VCC(B) = 1.8 V. (4) VCC(B) = 2.5 V. (5) VCC(B) = 3.3 V. (6) VCC(B) = 5.0 V. Fig 13. Typical propagation delay versus load capacitance; Tamb = 25 °C; VCC(A) = 2.5 V 74LVC_LVCH2T45_3 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 03 — 19 January 2010 20 of 32 74LVC2T45; 74LVCH2T45 NXP Semiconductors Dual supply translating transceiver; 3-state 001aai923 14 tPHL (ns) 12 10 001aai924 14 tPLH (ns) 12 10 (1) (1) 8 8 (2) (2) 6 6 (3) (3) 4 4 (4) (5) (6) 2 (4) (5) (6) 2 0 0 0 5 10 15 20 25 30 35 CL (pF) a. HIGH to LOW propagation delay (A to B) 001aai925 14 tPHL (ns) 12 0 8 8 (2) (3) (4) (5) (6) 4 2 0 15 20 25 30 35 CL (pF) 001aai926 14 tPLH (ns) 12 10 (1) 10 b. LOW to HIGH propagation delay (A to B) 10 6 5 6 (1) 4 (2) (3) 2 (4) (5) (6) 0 0 5 10 15 20 25 30 35 CL (pF) c. HIGH to LOW propagation delay (B to A) 0 5 10 15 20 25 30 35 CL (pF) d. LOW to HIGH propagation delay (B to A) (1) VCC(B) = 1.2 V. (2) VCC(B) = 1.5 V. (3) VCC(B) = 1.8 V. (4) VCC(B) = 2.5 V. (5) VCC(B) = 3.3 V. (6) VCC(B) = 5.0 V. Fig 14. Typical propagation delay versus load capacitance; Tamb = 25 °C; VCC(A) = 3.3 V 74LVC_LVCH2T45_3 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 03 — 19 January 2010 21 of 32 74LVC2T45; 74LVCH2T45 NXP Semiconductors Dual supply translating transceiver; 3-state 001aai927 14 tPHL (ns) 12 10 001aai928 14 tPLH (ns) 12 10 (1) (1) 8 8 (2) 6 (2) 6 (3) (3) 4 4 (4) (5) (6) 2 (4) (5) (6) 2 0 0 0 5 10 15 20 25 30 35 CL (pF) a. HIGH to LOW propagation delay (A to B) 001aai929 14 tPHL (ns) 12 0 5 10 15 20 25 30 35 CL (pF) b. LOW to HIGH propagation delay (A to B) 001aai930 14 tPLH (ns) 12 10 10 8 8 6 (1) 6 4 (2) (3) 4 (2) (3) 2 (4) (5) (6) 2 (4) (5) (6) 0 (1) 0 0 5 10 15 20 25 30 35 CL (pF) c. HIGH to LOW propagation delay (B to A) 0 5 10 15 20 25 30 35 CL (pF) d. LOW to HIGH propagation delay (B to A) (1) VCC(B) = 1.2 V. (2) VCC(B) = 1.5 V. (3) VCC(B) = 1.8 V. (4) VCC(B) = 2.5 V. (5) VCC(B) = 3.3 V. (6) VCC(B) = 5.0 V. Fig 15. Typical propagation delay versus load capacitance; Tamb = 25 °C; VCC(A) = 5 V 74LVC_LVCH2T45_3 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 03 — 19 January 2010 22 of 32 74LVC2T45; 74LVCH2T45 NXP Semiconductors Dual supply translating transceiver; 3-state 14. Application information 14.1 Unidirectional logic level-shifting application The circuit given in Figure 16 is an example of the 74LVC2T45; 74LVCH2T45 being used in an unidirectional logic level-shifting application. VCC1 VCC1 VCC2 VCC(A) 1A 1 8 2 7 4 5 VCC(B) VCC2 1B 74LVC2T45 2A 2B 3 74LVCH2T45 6 VCC1 GND DIR system-1 VCC2 system-2 001aai931 Fig 16. Unidirectional logic level-shifting application Table 16. Description of unidirectional logic level-shifting application Pin Name Function Description 1 VCC(A) VCC1 supply voltage of system-1 (1.2 V to 5.5 V) 2 1A OUT output level depends on VCC1 voltage 3 2A OUT output level depends on VCC1 voltage 4 GND GND device GND 5 DIR DIR the GND (LOW level) determines B port to A port direction 6 2B IN input threshold value depends on VCC2 voltage 7 1B IN input threshold value depends on VCC2 voltage 8 VCC(B) VCC2 supply voltage of system-2 (1.2 V to 5.5 V) 14.2 Bidirectional logic level-shifting application Figure 17 shows the 74LVC2T45; 74LVCH2T45 being used in a bidirectional logic level-shifting application. Since the device does not have an output enable pin, the system designer should take precautions to avoid bus contention between system-1 and system-2 when changing directions. 74LVC_LVCH2T45_3 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 03 — 19 January 2010 23 of 32 74LVC2T45; 74LVCH2T45 NXP Semiconductors Dual supply translating transceiver; 3-state VCC1 VCC1 I/O-1 VCC(A) PULL-UP/DOWN VCC2 VCC2 1A 2A GND 1 8 2 7 4 5 VCC(B) PULL-UP/DOWN I/O-2 1B 74LVC2T45 2B 3 74LVCH2T45 6 DIR DIR CTRL DIR CTRL system-2 system-1 001aai932 Pull-up or pull-down only needed for 74LVC2T45. Fig 17. Bidirectional logic level-shifting application Table 17 gives a sequence that will illustrate data transmission from system-1 to system-2 and then from system-2 to system-1. Description of bidirectional logic level-shifting application[1] Table 17. State DIR CTRL I/O-1 I/O-2 Description 1 H output input system-1 data to system-2 2 H Z Z system-2 is getting ready to send data to system-1. I/O-1 and I/O-2 are disabled. The bus-line state depends on bus hold 3 L Z Z DIR bit is set LOW. I/O-1 and I/O-2 still are disabled. The bus-line state depends on bus hold 4 L input output system-2 data to system-1 [1] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state. 14.3 Power-up considerations The device is designed such that no special power-up sequence is required other than GND being applied first. Table 18. Typical total supply current (ICC(A) + ICC(B)) VCC(A) VCC(B) Unit 0V 1.8 V 2.5 V 3.3 V 5.0 V 0V 0 <1 <1 <1 <1 μA 1.8 V <1 <2 <2 <2 2 μA 2.5 V <1 <2 <2 <2 <2 μA 3.3 V <1 <2 <2 <2 <2 μA 5.0 V <1 2 <2 <2 <2 μA 74LVC_LVCH2T45_3 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 03 — 19 January 2010 24 of 32 NXP Semiconductors 74LVC2T45; 74LVCH2T45 Dual supply translating transceiver; 3-state 14.4 Enable times Calculate the enable times for the 74LVC2T45; 74LVCH2T45 using the following formulas: • • • • tPZH (DIR to A) = tPLZ (DIR to B) + tPLH (B to A) tPZL (DIR to A) = tPHZ (DIR to B) + tPHL (B to A) tPZH (DIR to B) = tPLZ (DIR to A) + tPLH (A to B) tPZL (DIR to B) = tPHZ (DIR to A) + tPHL (A to B) In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is switched until an output is expected. For example, if the 74LVC2T45; 74LVCH2T45 initially is transmitting from A to B, then the DIR bit is switched, the B port of the device must be disabled before presenting it with an input. After the B port has been disabled, an input signal applied to it appears on the corresponding A port after the specified propagation delay. 74LVC_LVCH2T45_3 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 03 — 19 January 2010 25 of 32 74LVC2T45; 74LVCH2T45 NXP Semiconductors Dual supply translating transceiver; 3-state 15. Package outline VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm D E SOT765-1 A X c y HE v M A Z 5 8 Q A A2 A1 pin 1 index (A3) θ Lp 1 4 e L detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(2) e HE L Lp Q v w y Z(1) θ mm 1 0.15 0.00 0.85 0.60 0.12 0.27 0.17 0.23 0.08 2.1 1.9 2.4 2.2 0.5 3.2 3.0 0.4 0.40 0.15 0.21 0.19 0.2 0.13 0.1 0.4 0.1 8° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT765-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 02-06-07 MO-187 Fig 18. Package outline SOT765-1 (VSSOP8) 74LVC_LVCH2T45_3 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 03 — 19 January 2010 26 of 32 74LVC2T45; 74LVCH2T45 NXP Semiconductors Dual supply translating transceiver; 3-state XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm 1 2 SOT833-1 b 4 3 4× (2) L L1 e 8 7 6 e1 5 e1 e1 8× A (2) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max A1 max b D E e e1 L L1 mm 0.5 0.04 0.25 0.17 2.0 1.9 1.05 0.95 0.6 0.5 0.35 0.27 0.40 0.32 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT833-1 --- MO-252 --- EUROPEAN PROJECTION ISSUE DATE 07-11-14 07-12-07 Fig 19. Package outline SOT833-1 (XSON8) 74LVC_LVCH2T45_3 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 03 — 19 January 2010 27 of 32 74LVC2T45; 74LVCH2T45 NXP Semiconductors Dual supply translating transceiver; 3-state XSON8U: plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 3 x 2 x 0.5 mm B D SOT996-2 A A E A1 detail X terminal 1 index area e1 v w b e L1 1 4 8 5 C C A B C M M y y1 C L2 L X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 b D E e e1 L L1 L2 v w y y1 mm 0.5 0.05 0.00 0.35 0.15 2.1 1.9 3.1 2.9 0.5 1.5 0.5 0.3 0.15 0.05 0.6 0.4 0.1 0.05 0.05 0.1 REFERENCES OUTLINE VERSION IEC SOT996-2 --- JEDEC JEITA --- EUROPEAN PROJECTION ISSUE DATE 07-12-18 07-12-21 Fig 20. Package outline SOT996-2 (XSON8U) 74LVC_LVCH2T45_3 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 03 — 19 January 2010 28 of 32 74LVC2T45; 74LVCH2T45 NXP Semiconductors Dual supply translating transceiver; 3-state XQFN8U: plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm B D SOT902-1 A terminal 1 index area A E A1 detail X L1 e e C ∅v M C A B ∅w M C L 4 y1 C y 5 3 metal area not for soldering e1 b 2 6 e1 7 1 terminal 1 index area 8 X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 b D E e e1 L L1 v w y y1 mm 0.5 0.05 0.00 0.25 0.15 1.65 1.55 1.65 1.55 0.55 0.5 0.35 0.25 0.15 0.05 0.1 0.05 0.05 0.05 REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT902-1 --- MO-255 --- EUROPEAN PROJECTION ISSUE DATE 05-11-25 07-11-14 Fig 21. Package outline SOT902-1 (XQFN8U) 74LVC_LVCH2T45_3 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 03 — 19 January 2010 29 of 32 74LVC2T45; 74LVCH2T45 NXP Semiconductors Dual supply translating transceiver; 3-state 16. Abbreviations Table 19. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 17. Revision history Table 20. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC_LVCH2T45_3 20100119 Product data sheet - 74LVC_LVCH2T45_2 Modifications: • Table 6: input transition rise and fall rate conditions and limits changed. 74LVC_LVCH2T45_2 20090205 Product data sheet - 74LVC_LVCH2T45_1 74LVC_LVCH2T45_1 20081118 Product data sheet - - 74LVC_LVCH2T45_3 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 03 — 19 January 2010 30 of 32 74LVC2T45; 74LVCH2T45 NXP Semiconductors Dual supply translating transceiver; 3-state 18. Legal information 18.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 18.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74LVC_LVCH2T45_3 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 03 — 19 January 2010 31 of 32 NXP Semiconductors 74LVC2T45; 74LVCH2T45 Dual supply translating transceiver; 3-state 20. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 14.1 14.2 14.3 14.4 15 16 17 18 18.1 18.2 18.3 18.4 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Typical propagation delay characteristics . . 17 Application information. . . . . . . . . . . . . . . . . . 23 Unidirectional logic level-shifting application . 23 Bidirectional logic level-shifting application. . . 23 Power-up considerations . . . . . . . . . . . . . . . . 24 Enable times . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 26 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 30 Legal information. . . . . . . . . . . . . . . . . . . . . . . 31 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 31 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Contact information. . . . . . . . . . . . . . . . . . . . . 31 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 19 January 2010 Document identifier: 74LVC_LVCH2T45_3