PHILIPS 74AVC4T245

74AVC4T245
4-bit dual supply translating transceiver with configurable
voltage translation; 3-state
Rev. 01 — 20 July 2009
Product data sheet
1. General description
The 74AVC4T245 is an 4-bit, dual supply transceiver that enables bidirectional level
translation. The device can be used as two 2-bit transceivers or as a 4-bit transceiver. It
features two data input-output ports (nAn and nBn), a direction control input (nDIR), a
output enable input (nOE) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and
VCC(B) can be supplied at any voltage between 0.8 V and 3.6 V making the device suitable
for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and
3.3 V). Pins nAn, nOE and nDIR are referenced to VCC(A) and pins nBn are referenced to
VCC(B). A HIGH on nDIR allows transmission from nAn to nBn and a LOW on nDIR allows
transmission from nBn to nAn. The output enable input (nOE) can be used to disable the
outputs so the buses are effectively isolated.
The device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing any damaging backflow current through the
device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at
GND level, both nAn and nBn are in the high-impedance OFF-state.
2. Features
n Wide supply voltage range:
u VCC(A): 0.8 V to 3.6 V
u VCC(B): 0.8 V to 3.6 V
n Complies with JEDEC standards:
u JESD8-12 (0.8 V to 1.3 V)
u JESD8-11 (0.9 V to 1.65 V)
u JESD8-7 (1.2 V to 1.95 V)
u JESD8-5 (1.8 V to 2.7 V)
u JESD8-B (2.7 V to 3.6 V)
n ESD protection:
u HBM JESD22-A114E Class 3B exceeds 8000 V
u MM JESD22-A115-A exceeds 200 V
u CDM JESD22-C101C exceeds 1000 V
n Maximum data rates:
u 380 Mbit/s (≥ 1.8 V to 3.3 V translation)
u 200 Mbit/s (≥ 1.1 V to 3.3 V translation)
u 200 Mbit/s (≥ 1.1 V to 2.5 V translation)
u 200 Mbit/s (≥ 1.1 V to 1.8 V translation)
u 150 Mbit/s (≥ 1.1 V to 1.5 V translation)
74AVC4T245
NXP Semiconductors
4-bit dual supply translating transceiver; 3-state
n
n
n
n
n
n
u 100 Mbit/s (≥ 1.1 V to 1.2 V translation)
Suspend mode
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
IOFF circuitry provides partial Power-down mode operation
Multiple package options
Specified from −40 °C to +85 °C and −40 °C to +125 °C
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
−40 °C to +125 °C
SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
74AVC4T245PW −40 °C to +125 °C
TSSOP16
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
74AVC4T245BQ −40 °C to +125 °C
DHVQFN16 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 16 terminals;
body 2.5 × 3.5 × 0.85 mm
74AVC4T245D
SOT763-1
4. Functional diagram
13
12
1B1
VCC(A)
15
2
11
1B2
10
2B1
2B2
VCC(B)
1OE
2OE
1DIR
2DIR
1A1
1A2
2A1
14
3
2A2
001aak280
4
Fig 1.
5
6
7
Logic symbol
74AVC4T245_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 20 July 2009
2 of 25
74AVC4T245
NXP Semiconductors
4-bit dual supply translating transceiver; 3-state
DIR
OE
A1
B1
A2
B2
VCC(A)
VCC(B)
001aak281
Fig 2.
Logic diagram (one 2-bit transceiver)
5. Pinning information
5.1 Pinning
74AVC4T245
VCC(A)
1
16 VCC(B)
1DIR
2
15 1OE
2DIR
3
14 2OE
1A1
4
13 1B1
1A2
5
12 1B2
2A1
6
11 2B1
2A2
7
10 2B2
GND
8
9
GND
001aak283
Fig 3. Pin configuration SOT109-1 (SO16)
74AVC4T245_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 20 July 2009
3 of 25
74AVC4T245
NXP Semiconductors
4-bit dual supply translating transceiver; 3-state
1
terminal 1
index area
74AVC4T245
16 VCC(B)
VCC(A)
74AVC4T245
1DIR
2
15 1OE
2DIR
3
14 2OE
VCC(A)
1
16 VCC(B)
1DIR
2
15 1OE
1A1
4
13 1B1
2DIR
3
14 2OE
1A2
5
12 1B2
1A1
4
13 1B1
2A1
6
1A2
5
12 1B2
2A2
7
2A1
6
11 2B1
2A2
7
10 2B2
GND
8
8
9
GND
GND
11 2B1
10 2B2
GND
9
GND(1)
001aak284
Transparent top view
001aak282
(1) The die substrate is attached to this pad using
conductive die attach material. It cannot be used as
a supply pin or input.
Fig 4. Pin configuration SOT403-1 (TSSOP16)
Fig 5. Pin configuration SOT763-1 (DHVQFN16)
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
VCC(A)
1
supply voltage A (nAn, nOE and nDIR inputs are referenced to VCC(A))
1DIR, 2DIR
2, 3
direction control
1A1, 1A2
4, 5
data input or output
2A1, 2A2
6, 7
data input or output
GND[1]
8, 9
ground (0 V)
2B2, 2B1
10, 11
data input or output
1B2, 1B1
12, 13
data input or output
2OE, 1OE
14, 15
output enable input (active LOW)
VCC(B)
16
supply voltage B (nBn inputs are referenced to VCC(B))
[1]
All GND pins must be connected to ground (0 V).
74AVC4T245_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 20 July 2009
4 of 25
74AVC4T245
NXP Semiconductors
4-bit dual supply translating transceiver; 3-state
6. Functional description
Table 3.
Function table[1]
Input/output[3]
Supply voltage
Input
VCC(A), VCC(B)
nOE[2]
nDIR[2]
nAn[2]
nBn[2]
0.8 V to 3.6 V
L
L
nAn = nBn
input
0.8 V to 3.6 V
L
H
input
nBn = nAn
0.8 V to 3.6 V
H
X
Z
Z
GND[3]
X
X
Z
Z
[1]
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
[2]
The nAn, nDIR and nOE input circuit is referenced to VCC(A); The nBn input circuit is referenced to VCC(B).
[3]
If at least one of VCC(A) or VCC(B) is at GND level, the device goes into suspend mode.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC(A)
VCC(B)
IIK
input clamping current
Conditions
Min
Max
Unit
supply voltage A
−0.5
+4.6
V
supply voltage B
−0.5
+4.6
V
−50
-
mA
−0.5
+4.6
V
VI < 0 V
[1]
VI
input voltage
IOK
output clamping current
VO < 0 V
VO
output voltage
Active mode
−50
-
mA
[1][2][3]
−0.5
VCCO + 0.5
V
Suspend or 3-state mode
[1]
−0.5
+4.6
V
[2]
-
±50
mA
IO
output current
VO = 0 V to VCCO
ICC
supply current
ICC(A) or ICC(B)
IGND
ground current
Tstg
storage temperature
total power dissipation
Ptot
Tamb = −40 °C to +125 °C
[4]
-
100
mA
−100
-
mA
−65
+150
°C
-
500
mW
[1]
The minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
VCCO is the supply voltage associated with the output port.
[3]
VCCO + 0.5 V should not exceed 4.6 V.
[4]
For SO16 package: above 70 °C derates linearly with 8 mW/K.
For TSSOP16 package: above 60 °C the value of Ptot derates linearly at 5.5 mW/K.
For DHVQFN16 package: above 60 °C the value of Ptot derates linearly at 4.5 mW/K.
74AVC4T245_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 20 July 2009
5 of 25
74AVC4T245
NXP Semiconductors
4-bit dual supply translating transceiver; 3-state
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol
Parameter
VCC(A)
Conditions
Min
Max
Unit
supply voltage A
0.8
3.6
V
VCC(B)
supply voltage B
0.8
3.6
V
VI
input voltage
VO
output voltage
Active mode
[1]
Suspend or 3-state mode
Tamb
∆t/∆V
ambient temperature
input transition rise and fall rate
VCCI =0.8 V to 3.6 V
[1]
VCCO is the supply voltage associated with the output port.
[2]
VCCI is the supply voltage associated with the input port.
[2]
0
3.6
V
0
VCCO
V
0
3.6
V
−40
+125
°C
-
5
ns/V
9. Static characteristics
Table 6.
Typical static characteristics at Tamb = 25 °C[1][2]
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
VOH
HIGH-level output voltage
Conditions
LOW-level output voltage
Typ
Max
Unit
-
0.69
-
V
-
0.07
-
V
-
±0.025 ±0.25 µA
VI = VIH or VIL
IO = −1.5 mA; VCC(A) = VCC(B) = 0.8 V
VOL
Min
VI = VIH or VIL
IO = 1.5 mA; VCC(A) = VCC(B) = 0.8 V
II
input leakage current
nDIR, nOE input; VI = 0 V or 3.6 V;
VCC(A) = VCC(B) = 0.8 V to 3.6 V
IOZ
OFF-state output current
A or B port; VO = 0 V or VCCO;
VCC(A) = VCC(B) = 3.6 V
[3]
-
±0.5
±2.5
µA
suspend mode A port; VO = 0 V or VCCO;
VCC(A) = 3.6 V; VCC(B) = 0 V
[3]
-
±0.5
±2.5
µA
suspend mode B port; VO = 0 V or VCCO;
VCC(A) = 0 V; VCC(B) = 3.6 V
[3]
-
±0.5
±2.5
µA
A port; VI or VO = 0 V to 3.6 V;
VCC(A) = 0 V; VCC(B) = 0.8 V to 3.6 V
-
±0.1
±1
µA
B port; VI or VO = 0 V to 3.6 V;
VCC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V
-
±0.1
±1
µA
power-off leakage current
IOFF
CI
input capacitance
nDIR, nOE input; VI = 0 V or 3.3 V;
VCC(A) = VCC(B) = 3.3 V
-
1.0
-
pF
CI/O
input/output capacitance
A and B port; VO = 3.3 V or 0 V;
VCC(A) = VCC(B) = 3.3 V
-
4.0
-
pF
[1]
VCCO is the supply voltage associated with the output port.
[2]
VCCI is the supply voltage associated with the data input port.
[3]
For I/O ports, the parameter IOZ includes the input leakage current.
74AVC4T245_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 20 July 2009
6 of 25
74AVC4T245
NXP Semiconductors
4-bit dual supply translating transceiver; 3-state
Table 7.
Static characteristics [1][2]
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
VIH
HIGH-level
input voltage
−40 °C to +85 °C
Conditions
−40 °C to +125 °C
Unit
Min
Max
Min
Max
VCCI = 0.8 V
0.70VCCI
-
0.70VCCI
-
V
VCCI = 1.1 V to 1.95 V
0.65VCCI
-
0.65VCCI
-
V
VCCI = 2.3 V to 2.7 V
1.6
-
1.6
-
V
VCCI = 3.0 V to 3.6 V
2
-
2
-
V
VCC(A) = 0.8 V
0.70VCC(A)
-
0.70VCC(A)
-
V
VCC(A) = 1.1 V to 1.95 V
0.65VCC(A)
-
0.65VCC(A)
-
V
VCC(A) = 2.3 V to 2.7 V
1.6
-
1.6
-
V
VCC(A) = 3.0 V to 3.6 V
2
-
2
-
V
VCCI = 0.8 V
-
0.30VCCI
-
0.30VCCI
V
VCCI = 1.1 V to 1.95 V
-
0.35VCCI
-
0.35VCCI
V
VCCI = 2.3 V to 2.7 V
-
0.7
-
0.7
V
VCCI = 3.0 V to 3.6 V
-
0.8
-
0.8
V
VCC(A) = 0.8 V
-
0.30VCC(A)
-
0.30VCC(A) V
VCC(A) = 1.1 V to 1.95 V
-
0.35VCC(A)
-
0.35VCC(A) V
VCC(A) = 2.3 V to 2.7 V
-
0.7
-
0.7
V
VCC(A) = 3.0 V to 3.6 V
-
0.8
-
0.8
V
VCCO − 0.1
-
VCCO − 0.1
-
V
IO = −3 mA;
VCC(A) = VCC(B) = 1.1 V
0.85
-
0.85
-
V
IO = −6 mA;
VCC(A) = VCC(B) = 1.4 V
1.05
-
1.05
-
V
IO = −8 mA;
VCC(A) = VCC(B) = 1.65 V
1.2
-
1.2
-
V
IO = −9 mA;
VCC(A) = VCC(B) = 2.3 V
1.75
-
1.75
-
V
IO = −12 mA;
VCC(A) = VCC(B) = 3.0 V
2.3
-
2.3
-
V
data input
nDIR, nOE input
VIL
LOW-level
input voltage
data input
nDIR, nOE input
VOH
HIGH-level
VI = VIH or VIL
output voltage
IO = −100 µA;
VCC(A) = VCC(B) = 0.8 V to 3.6 V
74AVC4T245_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 20 July 2009
7 of 25
74AVC4T245
NXP Semiconductors
4-bit dual supply translating transceiver; 3-state
Table 7.
Static characteristics …continued[1][2]
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
VOL
−40 °C to +85 °C
Conditions
−40 °C to +125 °C
Unit
Min
Max
Min
Max
-
0.1
-
0.1
V
IO = 3 mA;
VCC(A) = VCC(B) = 1.1 V
-
0.25
-
0.25
V
IO = 6 mA;
VCC(A) = VCC(B) = 1.4 V
-
0.35
-
0.35
V
IO = 8 mA;
VCC(A) = VCC(B) = 1.65 V
-
0.45
-
0.45
V
IO = 9 mA;
VCC(A) = VCC(B) = 2.3 V
-
0.55
-
0.55
V
IO = 12 mA;
VCC(A) = VCC(B) = 3.0 V
-
0.7
-
0.7
V
-
±1
-
±5
µA
LOW-level
VI = VIH or VIL
output voltage
IO = 100 µA;
VCC(A) = VCC(B) = 0.8 V to 3.6 V
II
input leakage
current
nDIR, nOE input; VI = 0 V or 3.6
V; VCC(A) = VCC(B) = 0.8 V to 3.6 V
IOZ
OFF-state
output current
A or B port; VO = 0 V or VCCO;
VCC(A) = VCC(B) = 3.6 V
[3]
-
±5
-
±30
µA
suspend mode A port;
VO = 0 V or VCCO; VCC(A) = 3.6 V;
VCC(B) = 0 V
[3]
-
±5
-
±30
µA
suspend mode B port;
VO = 0 V or VCCO; VCC(A) = 0 V;
VCC(B) = 3.6 V
[3]
-
±5
-
±30
µA
A port; VI or VO = 0 V to 3.6 V;
VCC(A) = 0 V;
VCC(B) = 0.8 V to 3.6 V
-
±5
-
±30
µA
B port; VI or VO = 0 V to 3.6 V;
VCC(B) = 0 V;
VCC(A) = 0.8 V to 3.6 V
-
±5
-
±30
µA
IOFF
power-off
leakage
current
74AVC4T245_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 20 July 2009
8 of 25
74AVC4T245
NXP Semiconductors
4-bit dual supply translating transceiver; 3-state
Table 7.
Static characteristics …continued[1][2]
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
ICC
−40 °C to +85 °C
Conditions
−40 °C to +125 °C
Unit
Min
Max
Min
Max
VCC(A) = 0.8 V to 3.6 V;
VCC(B) = 0.8 V to 3.6 V
-
10
-
55
µA
VCC(A) = 1.1 V to 3.6 V;
VCC(B) = 1.1 V to 3.6 V
-
8
-
50
µA
VCC(A) = 3.6 V; VCC(B) = 0 V
-
8
-
50
µA
VCC(A) = 0 V; VCC(B) = 3.6 V
−2
-
−12
-
µA
VCC(A) = 0.8 V to 3.6 V;
VCC(B) = 0.8 V to 3.6 V
-
10
-
55
µA
VCC(A) = 1.1 V to 3.6 V;
VCC(B) = 1.1 V to 3.6 V
-
8
-
50
µA
VCC(A) = 3.6 V; VCC(B) = 0 V
−2
-
−12
-
µA
supply current A port; VI = 0 V or VCCI; IO = 0 A
B port; VI = 0 V or VCCI; IO = 0 A
VCC(A) = 0 V; VCC(B) = 3.6 V
-
8
-
50
µA
A plus B port (ICC(A) + ICC(B));
IO = 0 A; VI = 0 V or VCCI;
VCC(A) = 0.8 V to 3.6 V;
VCC(B) = 0.8 V to 3.6 V
-
20
-
70
µA
A plus B port (ICC(A) + ICC(B));
IO = 0 A; VI = 0 V or VCCI;
VCC(A) = 1.1 V to 3.6 V;
VCC(B) = 1.1 V to 3.6 V
-
16
-
65
µA
[1]
VCCO is the supply voltage associated with the output port.
[2]
VCCI is the supply voltage associated with the data input port.
[3]
For I/O ports, the parameter IOZ includes the input leakage current.
Table 8.
VCC(A)
Typical total supply current (ICC(A) + ICC(B))
VCC(B)
Unit
0V
0.8 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0V
0
0.1
0.1
0.1
0.1
0.1
0.1
µA
0.8 V
0.1
0.1
0.1
0.1
0.1
0.3
1.6
µA
1.2 V
0.1
0.1
0.1
0.1
0.1
0.1
0.8
µA
1.5 V
0.1
0.1
0.1
0.1
0.1
0.1
0.4
µA
1.8 V
0.1
0.1
0.1
0.1
0.1
0.1
0.2
µA
2.5 V
0.1
0.3
0.1
0.1
0.1
0.1
0.1
µA
3.3 V
0.1
1.6
0.8
0.4
0.2
0.1
0.1
µA
74AVC4T245_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 20 July 2009
9 of 25
74AVC4T245
NXP Semiconductors
4-bit dual supply translating transceiver; 3-state
10. Dynamic characteristics
Table 9.
Typical power dissipation capacitance at VCC(A) = VCC(B) and Tamb = 25 °C [1][2]
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
power dissipation
capacitance
CPD
Conditions
VCC(A) = VCC(B)
0.8 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
A port: (direction nAn to
nBn); output enabled
0.2
0.2
0.2
0.2
0.3
0.4
pF
A port: (direction nAn to
nBn); output disabled
0.2
0.2
0.2
0.2
0.3
0.4
pF
A port: (direction nBn to
nAn); output enabled
9.5
9.7
9.8
9.9
10.7
11.9
pF
A port: (direction nBn to
nAn); output disabled
0.6
0.6
0.6
0.6
0.7
0.7
pF
B port: (direction nAn to
nBn); output enabled
9.5
9.7
9.8
9.9
10.7
11.9
pF
B port: (direction nAn to
nBn); output disabled
0.6
0.6
0.6
0.6
0.7
0.7
pF
B port: (direction nBn to
nAn); output enabled
0.2
0.2
0.2
0.2
0.3
0.4
pF
B port: (direction nBn to
nAn); output disabled
0.2
0.2
0.2
0.2
0.3
0.4
pF
[1]
CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
[2]
fi = 10 MHz; VI = GND to VCC; tr = tf = 1 ns; CL = 0 pF; RL = ∞ Ω.
74AVC4T245_1
Product data sheet
Unit
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 20 July 2009
10 of 25
74AVC4T245
NXP Semiconductors
4-bit dual supply translating transceiver; 3-state
Table 10. Typical dynamic characteristics at VCC(A) = 0.8 V and Tamb = 25 °C [1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7
Symbol Parameter
tpd
VCC(B)
Unit
0.8 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
propagation delay nAn to nBn
14.5
7.3
6.5
6.2
5.9
6.0
ns
nBn to nAn
14.5
12.7
12.4
12.3
12.1
12.0
ns
nOE to nAn
14.3
14.3
14.3
14.3
14.3
14.3
ns
nOE to nBn
17.0
9.9
9.0
9.4
9.0
9.7
ns
nOE to nAn
18.2
18.2
18.2
18.2
18.2
18.2
ns
nOE to nBn
19.2
10.7
9.8
9.6
9.7
10.2
ns
tdis
disable time
ten
enable time
[1]
Conditions
tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH.
Table 11. Typical dynamic characteristics at VCC(B) = 0.8 V and Tamb = 25 °C [1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7
Symbol Parameter
tpd
VCC(A)
Unit
0.8 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
propagation delay nAn to nBn
14.5
12.7
12.4
12.3
12.1
12.0
ns
nBn to nAn
14.5
7.3
6.5
6.2
5.9
6.0
ns
nOE to nAn
14.3
5.5
4.1
4.0
3.0
3.5
ns
nOE to nBn
17.0
13.8
13.4
13.1
12.9
12.7
ns
nOE to nAn
18.2
5.6
4.0
3.2
2.4
2.2
ns
nOE to nBn
19.2
14.6
14.1
13.9
13.7
13.6
ns
tdis
disable time
ten
enable time
[1]
Conditions
tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH.
74AVC4T245_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 20 July 2009
11 of 25
74AVC4T245
NXP Semiconductors
4-bit dual supply translating transceiver; 3-state
Table 12. Dynamic characteristics for temperature range −40 °C to +85 °C [1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7.
Symbol Parameter
Conditions
VCC(B)
Unit
1.2 V ± 0.1 V
1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V
3.3 V ± 0.3 V
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
0.5
9.4
0.5
7.1
0.5
6.2
0.5
5.2
0.5
5.1
ns
VCC(A) = 1.1 V to 1.3 V
tpd
propagation
delay
nAn to nBn
nBn to nAn
0.5
9.4
0.5
8.9
0.5
8.7
0.5
8.4
0.5
8.2
ns
tdis
disable time
nOE to nAn
1.8
10.9
1.8
10.9
1.8
10.9
1.8
10.9
1.8
10.9
ns
nOE to nBn
1.9
12.4
1.9
9.6
1.9
9.5
1.4
8.1
1.2
9.1
ns
nOE to nAn
1.4
12.8
1.4
12.8
1.4
12.8
1.4
12.8
1.4
12.8
ns
nOE to nBn
1.1
13.3
1.1
10.0
1.1
8.9
1.0
7.9
1.0
7.7
ns
nAn to nBn
0.3
8.9
0.3
6.3
0.3
5.2
0.3
4.2
0.3
4.2
ns
nBn to nAn
0.7
7.1
0.7
6.3
0.5
6.0
0.4
5.7
0.3
5.6
ns
enable time
ten
VCC(A) = 1.4 V to 1.6 V
propagation
delay
tpd
disable time
tdis
enable time
ten
nOE to nAn
1.8
10.2
1.8
10.2
1.5
10.2
1.3
10.2
1.6
10.2
ns
nOE to nBn
1.9
11.3
1.9
10.3
1.9
9.1
1.4
7.4
1.2
7.6
ns
nOE to nAn
1.1
9.4
1.4
9.4
1.1
9.4
0.7
9.4
0.4
9.4
ns
nOE to nBn
1.4
12.1
1.4
9.6
1.1
7.7
0.9
5.8
0.9
5.6
ns
VCC(A) = 1.65 V to 1.95 V
propagation
delay
nAn to nBn
0.1
8.7
0.1
6.0
0.1
4.9
0.1
3.9
0.3
3.9
ns
nBn to nAn
0.6
6.2
0.6
5.3
0.5
4.9
0.3
4.6
0.3
4.5
ns
tdis
disable time
nOE to nAn
1.8
8.6
1.6
8.6
1.8
8.6
1.3
8.6
1.6
8.6
ns
nOE to nBn
1.7
10.9
1.7
9.9
1.6
8.7
1.2
6.9
1.0
6.9
ns
ten
enable time
nOE to nAn
1.0
7.2
1.0
7.2
1.0
7.2
0.6
7.2
0.4
7.2
ns
nOE to nBn
1.2
11.7
1.2
9.2
1.0
7.4
0.8
5.3
0.8
4.6
ns
propagation
delay
nAn to nBn
0.1
8.4
0.1
5.7
0.1
4.6
0.2
3.5
0.1
3.6
ns
nBn to nAn
0.6
5.2
0.6
4.2
0.4
3.9
0.2
3.4
0.2
3.3
ns
disable time
nOE to nAn
1.0
6.2
1.0
6.2
1.0
6.2
1.0
6.2
1.0
6.2
ns
nOE to nBn
1.5
10.4
1.5
8.8
1.3
8.2
1.1
6.2
0.9
5.2
ns
tpd
VCC(A) = 2.3 V to 2.7 V
tpd
tdis
enable time
ten
nOE to nAn
0.7
4.8
0.7
4.8
0.7
4.8
0.6
4.8
0.4
4.8
ns
nOE to nBn
0.9
11.3
0.9
8.8
0.8
7.0
0.6
4.8
0.6
4.0
ns
0.1
8.2
0.1
5.6
0.1
4.5
0.1
3.3
0.1
2.9
ns
VCC(A) = 3.0 V to 3.6 V
tpd
propagation
delay
nAn to nBn
nBn to nAn
0.6
5.1
0.6
4.2
0.4
3.4
0.2
3.0
0.1
2.8
ns
tdis
disable time
nOE to nAn
0.7
5.6
0.7
5.6
0.7
5.6
0.7
5.6
0.7
5.6
ns
nOE to nBn
1.4
10.2
1.4
9.3
1.2
8.1
1.0
6.4
0.8
6.2
ns
nOE to nAn
0.6
3.8
0.6
3.8
0.6
3.8
0.6
3.8
0.4
3.8
ns
nOE to nBn
0.8
11.3
0.8
8.7
0.6
6.8
0.5
4.7
0.5
3.8
ns
enable time
ten
[1]
tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH.
74AVC4T245_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 20 July 2009
12 of 25
74AVC4T245
NXP Semiconductors
4-bit dual supply translating transceiver; 3-state
Table 13. Dynamic characteristics for temperature range −40 °C to +125 °C [1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7
Symbol Parameter
Conditions
VCC(B)
Unit
1.2 V ± 0.1 V
1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V
3.3 V ± 0.3 V
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
0.5
10.4
0.5
7.9
0.5
6.9
0.5
5.8
0.5
5.7
ns
VCC(A) = 1.1 V to 1.3 V
tpd
propagation
delay
nAn to nBn
nBn to nAn
0.5
10.4
0.5
9.8
0.5
9.6
0.5
9.3
0.5
9.1
ns
tdis
disable time
nOE to nAn
1.8
12.0
1.8
12.0
1.8
12.0
1.8
12.0
1.8
12.0
ns
nOE to nBn
1.9
13.7
1.9
10.6
1.9
10.5
1.4
9.0
1.2
10.1
ns
nOE to nAn
1.4
14.1
1.4
14.1
1.4
14.1
1.4
14.1
1.4
14.1
ns
nOE to nBn
1.1
14.7
1.1
11.0
1.1
9.8
1.0
8.7
1.0
8.5
ns
propagation
delay
nAn to nBn
0.3
9.8
0.3
7.0
0.3
5.8
0.3
4.7
0.3
4.7
ns
nBn to nAn
0.7
7.9
0.7
7.0
0.5
6.6
0.4
6.3
0.3
6.2
ns
disable time
nOE to nAn
1.8
11.3
1.8
11.3
1.5
11.3
1.3
11.3
1.6
11.3
ns
nOE to nBn
1.9
12.5
1.9
11.4
1.9
10.1
1.4
8.2
1.2
8.4
ns
nOE to nAn
1.1
10.4
1.4
10.4
1.1
10.4
0.7
10.4
0.4
10.4
ns
nOE to nBn
1.4
13.3
1.4
10.6
1.1
8.5
0.9
6.4
0.9
6.2
ns
enable time
ten
VCC(A) = 1.4 V to 1.6 V
tpd
tdis
enable time
ten
VCC(A) = 1.65 V to 1.95 V
propagation
delay
nAn to nBn
0.1
9.6
0.1
6.6
0.1
5.4
0.1
4.3
0.3
4.3
ns
nBn to nAn
0.6
6.9
0.6
5.9
0.5
5.4
0.3
5.1
0.3
5.0
ns
tdis
disable time
nOE to nAn
1.8
9.5
1.6
9.5
1.8
9.5
1.3
9.5
1.6
9.5
ns
nOE to nBn
1.7
12.0
1.7
10.9
1.6
9.6
1.2
7.6
1.0
7.6
ns
ten
enable time
nOE to nAn
1.0
8.0
1.0
8.0
1.0
8.0
0.6
8.0
0.4
8.0
ns
nOE to nBn
1.2
12.9
1.2
10.2
1.0
8.2
0.8
5.9
0.8
5.1
ns
propagation
delay
nAn to nBn
0.1
9.3
0.1
6.3
0.1
5.1
0.2
4.0
0.1
4.0
ns
nBn to nAn
0.6
5.8
0.6
4.7
0.4
4.3
0.2
3.9
0.2
3.8
ns
disable time
nOE to nAn
1.0
6.9
1.0
6.9
1.0
6.9
1.0
6.9
1.0
6.9
ns
nOE to nBn
1.5
11.5
1.5
10.4
1.3
9.1
1.1
6.9
0.9
5.8
ns
tpd
VCC(A) = 2.3 V to 2.7 V
tpd
tdis
enable time
ten
nOE to nAn
0.7
5.3
0.7
5.3
0.7
5.3
0.6
5.3
0.4
5.3
ns
nOE to nBn
0.9
12.4
0.9
9.7
0.8
7.7
0.6
5.3
0.6
4.4
ns
0.1
9.1
0.1
6.2
0.1
5.0
0.1
3.8
0.1
3.3
ns
VCC(A) = 3.0 V to 3.6 V
tpd
propagation
delay
nAn to nBn
nBn to nAn
0.6
5.7
0.6
4.7
0.4
3.9
0.2
3.4
0.1
3.3
ns
tdis
disable time
nOE to nAn
0.7
6.2
0.7
6.2
0.7
6.2
0.7
6.2
0.7
6.2
ns
nOE to nBn
1.4
11.3
1.4
10.3
1.2
9.0
1.0
7.1
0.8
6.9
ns
nOE to nAn
0.6
4.2
0.6
4.2
0.6
4.2
0.6
4.2
0.4
4.2
ns
nOE to nBn
0.8
12.4
0.8
9.6
0.6
7.5
0.5
5.2
0.5
4.2
ns
enable time
ten
[1]
tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH.
74AVC4T245_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 20 July 2009
13 of 25
74AVC4T245
NXP Semiconductors
4-bit dual supply translating transceiver; 3-state
11. Waveforms
VI
nAn, nBn input
VM
GND
tPHL
tPLH
VOH
VM
nBn, nAn output
VOL
001aak285
Measurement points are given in Table 14.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 6.
The data input (nAn, nBn) to output (nBn, nAn) propagation delay times
VI
VM
nOE input
GND
tPLZ
tPZL
VCCO
output
LOW-to-OFF
OFF-to-LOW
VM
VX
VOL
tPHZ
VOH
tPZH
VY
output
HIGH-to-OFF
OFF-to-HIGH
VM
GND
outputs
enabled
outputs
disabled
outputs
enabled
001aak286
Measurement points are given in Table 14.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 7.
Table 14.
Enable and disable times
Measurement points
Supply voltage
Input[1]
Output[2]
VCC(A), VCC(B)
VM
VM
VX
VY
0.8 V to 1.6 V
0.5VCCI
0.5VCCO
VOL + 0.1 V
VOH − 0.1 V
1.65 V to 2.7 V
0.5VCCI
0.5VCCO
VOL + 0.15 V
VOH − 0.15 V
3.0 V to 3.6 V
0.5VCCI
0.5VCCO
VOL + 0.3 V
VOH − 0.3 V
[1]
VCCI is the supply voltage associated with the data input port.
[2]
VCCO is the supply voltage associated with the output port.
74AVC4T245_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 20 July 2009
14 of 25
74AVC4T245
NXP Semiconductors
4-bit dual supply translating transceiver; 3-state
tW
VI
90 %
negative
pulse
VM
VM
10 %
0V
tf
tr
tr
tf
VI
90 %
positive
pulse
VM
VM
10 %
0V
tW
VEXT
VCC
VI
RL
VO
G
DUT
RT
CL
RL
001aae331
Test data is given in Table 15.
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance.
VEXT = External voltage for measuring switching times.
Fig 8.
Table 15.
Load circuit for switching times
Test data
Supply voltage
Input
VCC(A), VCC(B)
VI[1]
∆t/∆V[2]
Load
CL
RL
tPLH, tPHL
tPZH, tPHZ
tPZL, tPLZ[3]
0.8 V to 1.6 V
VCCI
≤ 1.0 ns/V
15 pF
2 kΩ
open
GND
2VCCO
1.65 V to 2.7 V
VCCI
≤ 1.0 ns/V
15 pF
2 kΩ
open
GND
2VCCO
3.0 V to 3.6 V
VCCI
≤ 1.0 ns/V
15 pF
2 kΩ
open
GND
2VCCO
[1]
VCCI is the supply voltage associated with the data input port.
[2]
dV/dt ≥ 1.0 V/ns
[3]
VCCO is the supply voltage associated with the output port.
VEXT
74AVC4T245_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 20 July 2009
15 of 25
74AVC4T245
NXP Semiconductors
4-bit dual supply translating transceiver; 3-state
12. Typical propagation delay characteristics
001aai476
24
tpd
(ns)
(1)
(2)
(3)
(4)
(5)
(6)
tpd
(ns)
(1)
20
001aai477
21
17
16
12
13
(2)
(3)
(4)
(5)
(6)
8
4
9
0
20
40
60
0
CL (pF)
40
60
CL (pF)
a. Propagation delay (A to B); VCC(A) = 0.8 V
b. Propagation delay (A to B); VCC(B) = 0.8 V
(1) VCC(B) = 0.8 V.
(1) VCC(A) = 0.8 V.
(2) VCC(B) = 1.2 V.
(2) VCC(A) = 1.2 V.
(3) VCC(B) = 1.5 V.
(3) VCC(A) = 1.5 V.
(4) VCC(B) = 1.8 V.
(4) VCC(A) = 1.8 V.
(5) VCC(B) = 2.5 V.
(5) VCC(A) = 2.5 V.
(6) VCC(B) = 3.3 V.
(6) VCC(A) = 3.3 V.
Fig 9.
20
Typical propagation delay versus load capacitance; Tamb = 25 °C
74AVC4T245_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 20 July 2009
16 of 25
74AVC4T245
NXP Semiconductors
4-bit dual supply translating transceiver; 3-state
001aai478
7
001aai491
7
(1)
tPLH
(ns)
tPHL
(ns)
(1)
(2)
5
5
(3)
(2)
(3)
(4)
(4)
(5)
(5)
3
3
1
1
0
20
40
60
0
20
40
CL (pF)
a. LOW to HIGH propagation delay (A to B);
VCC(A) = 1.2 V
b. HIGH to LOW propagation delay (A to B);
VCC(A) = 1.2 V
001aai479
7
60
CL (pF)
001aai480
7
(1)
tPLH
(ns)
tPHL
(ns)
(1)
5
5
(2)
(3)
(2)
(3)
(4)
(5)
3
(4)
(5)
3
1
1
0
20
40
60
0
CL (pF)
20
40
60
CL (pF)
c. LOW to HIGH propagation delay (A to B);
VCC(A) = 1.5 V
d. HIGH to LOW propagation delay (A to B);
VCC(A) = 1.5 V
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4) VCC(B) = 2.5 V.
(5) VCC(B) = 3.3 V.
Fig 10. Typical propagation delay versus load capacitance; Tamb = 25 °C
74AVC4T245_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 20 July 2009
17 of 25
74AVC4T245
NXP Semiconductors
4-bit dual supply translating transceiver; 3-state
001aai481
7
(1)
tPLH
(ns)
001aai482
7
tPHL
(ns)
5
(1)
5
(2)
(3)
(2)
(3)
(4)
3
(4)
(5)
3
(5)
1
1
0
20
40
60
0
20
40
CL (pF)
a. LOW to HIGH propagation delay (A to B);
VCC(A) = 1.8 V
b. HIGH to LOW propagation delay (A to B);
VCC(A) = 1.8 V
001aai483
7
tPLH
(ns)
60
CL (pF)
001aai486
7
tPHL
(ns)
(1)
5
(1)
5
(2)
(2)
(3)
(3)
(4)
3
3
(4)
(5)
(5)
1
1
0
20
40
60
0
CL (pF)
20
40
60
CL (pF)
c. LOW to HIGH propagation delay (A to B);
VCC(A) = 2.5 V
d. HIGH to LOW propagation delay (A to B);
VCC(A) = 2.5 V
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4) VCC(B) = 2.5 V.
(5) VCC(B) = 3.3 V.
Fig 11. Typical propagation delay versus load capacitance; Tamb = 25 °C
74AVC4T245_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 20 July 2009
18 of 25
74AVC4T245
NXP Semiconductors
4-bit dual supply translating transceiver; 3-state
001aai485
7
tPLH
(ns)
001aai484
7
tPHL
(ns)
(1)
5
(1)
5
(2)
(2)
(3)
(3)
3
3
(4)
(4)
(5)
(5)
1
1
0
20
40
60
0
CL (pF)
20
40
60
CL (pF)
a. LOW to HIGH propagation delay (A to B);
VCC(A) = 3.3 V
b. HIGH to LOW propagation delay (A to B);
VCC(A) = 3.3 V
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4) VCC(B) = 2.5 V.
(5) VCC(B) = 3.3 V.
Fig 12. Typical propagation delay versus load capacitance; Tamb = 25 °C
74AVC4T245_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 20 July 2009
19 of 25
74AVC4T245
NXP Semiconductors
4-bit dual supply translating transceiver; 3-state
13. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
HE
v M A
Z
16
9
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
8
e
0
detail X
w M
bp
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.01
0.019 0.0100 0.39
0.014 0.0075 0.38
0.039
0.016
0.028
0.020
inches
0.010 0.057
0.069
0.004 0.049
0.16
0.15
0.05
0.244
0.041
0.228
0.01
0.01
0.028
0.004
0.012
θ
o
8
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT109-1
076E07
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 13. Package outline SOT109-1 (SO16)
74AVC4T245_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 20 July 2009
20 of 25
74AVC4T245
NXP Semiconductors
4-bit dual supply translating transceiver; 3-state
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
E
D
A
X
c
y
HE
v M A
Z
9
16
Q
(A 3)
A2
A
A1
pin 1 index
θ
Lp
L
1
8
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.40
0.06
8
o
0
o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT403-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
MO-153
Fig 14. Package outline SOT403-1 (TSSOP16)
74AVC4T245_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 20 July 2009
21 of 25
74AVC4T245
NXP Semiconductors
4-bit dual supply translating transceiver; 3-state
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
SOT763-1
16 terminals; body 2.5 x 3.5 x 0.85 mm
A
B
D
A
A1
E
c
detail X
terminal 1
index area
terminal 1
index area
C
e1
e
2
7
y
y1 C
v M C A B
w M C
b
L
1
8
Eh
e
16
9
15
10
Dh
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
mm
A(1)
max.
A1
b
1
0.05
0.00
0.30
0.18
c
D (1)
Dh
E (1)
Eh
0.2
3.6
3.4
2.15
1.85
2.6
2.4
1.15
0.85
e
0.5
e1
L
v
w
y
y1
2.5
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT763-1
---
MO-241
---
EUROPEAN
PROJECTION
ISSUE DATE
02-10-17
03-01-27
Fig 15. Package outline SOT763-1 (DHVQFN16)
74AVC4T245_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 20 July 2009
22 of 25
74AVC4T245
NXP Semiconductors
4-bit dual supply translating transceiver; 3-state
14. Abbreviations
Table 16.
Abbreviations
Acronym
Description
CDM
Charged Device Model
CMOS
Complementary Metal Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
15. Revision history
Table 17.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74AVC4T245_1
20090720
Product data sheet
-
-
74AVC4T245_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 20 July 2009
23 of 25
74AVC4T245
NXP Semiconductors
4-bit dual supply translating transceiver; 3-state
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
74AVC4T245_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 20 July 2009
24 of 25
74AVC4T245
NXP Semiconductors
4-bit dual supply translating transceiver; 3-state
18. Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
10
11
12
13
14
15
16
16.1
16.2
16.3
16.4
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . 10
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Typical propagation delay characteristics. . . 16
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 20
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 23
Legal information. . . . . . . . . . . . . . . . . . . . . . . 24
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 24
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Contact information. . . . . . . . . . . . . . . . . . . . . 24
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 20 July 2009
Document identifier: 74AVC4T245_1