ATMEL TH7834CCC-RB

Features
•
•
•
•
•
•
•
6.5 µm x 6.5 µm Photodiode Pixel, at 6.5 µm Pitch
2 x 2 Outputs
High Output Data Rate: 4 x 5 MHz
High Dynamic Range: 10000: 1
Antiblooming and Exposure Time Control
Very Low Lag
56 lead 0.6" DIL Package
Description
Atmel’s TH7834C is a linear sensor based on charge-coupled device (CCD) technology. It can be used in a wide range of applications thanks to operating mode flexibility,
very high definition and high dynamic range (document scanning, digital photography,
Art, Industrial and Scientific Applications).
Pixel 1
mark
VOS1
VDR1
VS1
ΦR1-2
VSS
VST
ΦA1-2
VGS1-2
VS
Φ3A
Φ1A
Φ4A
Φ2A
VSS
VSS
Φ2C
Φ4C
Φ1C
Φ3C
VSS
ΦP3-4
VA3-4
ΦLS3-4
VSS
VDD3-4
VS3
VDR3
VOS3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
TOP VIEW
VOS2
VDR2
VS2
VDD1-2
VSS
ΦLS1-2
VA1-2
ΦP1-2
VSS
Φ3D
Φ1D
Φ4D
Φ2D
VSS
VSS
Φ2B
Φ4B
Φ1B
Φ3B
VSS
VGS3-4
ΦA3-4
VST
VSS
ΦR3-4
VS4
VDR4
VOS4
Very Highresolution
Linear CCD
Image Sensor
(12000 Pixels)
TH7834C
Rev. 1997A–IMAGE–05/02
1
Pin Description
Pin Number
Symbol
Designation
1
VOS1
Output 1 (Odd Pixels)
2
VDR1
Reset DC Bias (Output 1)
3
VS1
Amplifier Source Bias (Output 1)
4
ΦR1-2
Reset Clock (Outputs 1 and 2)
5, 9, 14, 15, 20, 24, 33,
37, 42, 43, 48, 52
VSS
Substrate Bias (Ground)
6, 34
VST
Pixel Storage Gate DC Bias
7
ΦA1-2
Antiblooming and/or Exposure Time Control
8
VGS1-2
Output Gate DC Bias
10
Φ3A
Register Main Transport Clock
11
Φ1A
Register Main Transport Clock
12
Φ4A
Register Main Transport Clock
13
Φ2A
Register Main Transport Clock
16
Φ2C
Register Main Transport Clock
17
Φ4C
Register Main Transport Clock
18
Φ1C
Register Main Transport Clock
19
Φ3C
Register Main Transport Clock
21
ΦP3-4
Transfer Clock
22
VA3-4
Antiblooming Diode Bias
23
ΦLS3-4
Register End Transport Clock
25
VDD3-4
Amplifier Drain Supplies (Outputs 3, 4)
26
VS3
Amplifier Source Bias (Output 3)
27
VDR3
Reset DC Bias (Output 3)
28
VOS3
Output 3 (Odd Pixels)
29
VOS4
Output 4 (Even Pixels)
30
VDR4
Reset DC Bias (Output 4)
31
VS4
Amplifier Source Bias (Output 4)
32
ΦR3-4
Reset Clock (Outputs 3 and 4)
35
ΦA3-4
Antiblooming and/or Exposure Time Control
36
VGS3-4
Output Gate DC Bias
38
Φ3D
Register Main Transport Clock
39
Φ1D
Register Main Transport Clock
40
Φ4D
Register Main Transport Clock
41
Φ2D
Register Main Transport Clock
44
Φ2B
Register Main Transport Clock
45
Φ4B
Register Main Transport Clock
2
TH7834C
1997A–IMAGE–05/02
TH7834C
Pin Description (Continued)
Pin Number
Symbol
Designation
46
Φ1B
Register Main Transport Clock
47
Φ3B
Register Main Transport Clock
49
ΦP1-2
Transfer Clock
50
VA1-2
Antiblooming Diode Bias
51
ΦLS1-2
Register End Transport Clock
53
VDD1-2
Amplifier Drain Supplies (Outputs 1, 2)
54
VS2
Amplifier Source Bias (Output 2)
55
VDR2
Reset DC Bias (Output 2)
56
Notes:
VOS2
Output 2 (Even Pixels)
1. Pins ΦA1-2, VGS1-2, ΦP1-2, VA1-2, ΦLS1-2, VDD1-2, ΦR1-2 and respectively, ΦA3-4, VGS3-4, ΦP3-4, VA3-4, ΦLS3-4, VDD3-4, ΦR3-4 are not
connected together inside the package.
2. Two Pins VST connected together inside the package.
Figure 1. TH7834 Block Diagram
Φ3B
VS2
VDR2
VOS2
ΦLS1-2
CCD
Φ4B
Φ2D
Φ2B
Φ1B
Φ1D
Φ4D
Φ3D
B
VGS3-4
CCD
VDR4
VS4
D
VOS4
ΦP1-2
VST
VDD1-2
ΦR3-4
ΦR1-2
12000
1
VDD3-4
VST
ΦP3-4
VOS1
CCD
VS1
VDR1
A
CCD
Φ3A
Description
Φ2A
Φ1A
VGS1-2
Φ4A
Φ4C
Φ2C
Φ3C
C
ΦLS3-4
VOS3
VDR3
VS3
Φ1C
TH7834C high resolution linear array consists of 12000 useful pixel photosensitive line,
associated with four CCD shift registers and four output amplifiers. Transfer gates on
both sides of the photosensitive line enable delivery of charges, respectively:
•
on one side, charge accumulated by odd pixels (1, 3, 5… 11999), to CCD shift
registers A and C,
•
on the other side, charge accumulated by even pixels (2, 4, 6… 12000), to CCD
shift registers B and D.
Shift registers 1 and 2 collect charges generated by one half of the photosensitive line
(pixel 1 to 6000), whereas shift registers 3 and 4 collect charges generated by the second half of the photosensitive line (pixels 12000 to 6001).
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1997A–IMAGE–05/02
The four CCD shift registers have separated clocks. The output signal can be, then,
delivered simultaneously or sequentially on the four outputs.
The four CCD shift registers are designed with 4 separated gates. According to the gate
connection, the signal can be read through 2 or 4 output amplifiers.
According to gate connection, 2 or 4 output operating mode can be chosen. In the 4 output operating mode, signals associated to the end pixels of the array (either pixels
number 1, 2 or pixels number 11999, 12000) are delivered first in time and signals corresponding to the center of the line (pixels number 5999, 6000 and 6001, 6002) are
delivered last in time. Thus, external circuitry and processing are needed to combine the
four video outputs and to restore the normal order of the pixels in accordance with their
spatial distribution on the photosensitive line.
Terminal stages for every CCD shift register have separate clock control inputs in order
to speed up the final charge to voltage conversion and reduce the video output settling
time.
Antiblooming and exposure time control functions are provided.
Symmetrical TH7834 package PIN OUT allow to inverted pin 1 and 56 positions without
damage.
To obtain optimal operating mode, separated driving circuits are recommended for each
readout shift register (at least ΦLS and ΦR).
Figure 2. Driving Schematic
Logical signal : ΦL1
ΦL2
Logical signal : ΦL1
Pins Φ(1,2,3,4)B
VOS2
2
CCD B
ΦL2
Pins Φ(1,2,3,4)D
6000 6002
CCD D
12000
VOS4
5999 6001
CCD C
11999
VOS3
Photosensitive line
VOS1
1
CCD A
Pins F(1,2,3,4)A
Logical signal : ΦL1
4
ΦL2
Pins F(1,2,3,4)C
Logical signal : ΦL1
PHI3C
ΦL2
TH7834C
1997A–IMAGE–05/02
TH7834C
Readout Shift Register
Clocking
All gates of the 4 CCD shift registers are separated, enabling two or four output readout
modes.
To select 2 or 4 outputs operating mode, register main transport gates must be connected as described here after:
•
4 outputs mode:
VOS1: ΦL1 = Φ2A + Φ3A; ΦL2 = Φ1A + Φ4A
VOS2: ΦL1 = Φ2B + Φ3B; ΦL2 = Φ1B + Φ4B
VOS3: ΦL1 = Φ2C + Φ3C; ΦL2 = Φ1C + Φ4C
VOS4: ΦL1 = Φ2D + Φ3D; ΦL2 = Φ1D + Φ4D
•
2 output mode: VOS1 and VOS2:
VOS1: ΦL1 = Φ2A + Φ3A + Φ1C + Φ2C
ΦL2 = Φ1A + Φ4A + Φ3C + Φ4C
VOS2: ΦL1 = Φ2B + Φ3B + Φ1D + Φ2D
ΦL2 = Φ1B + Φ4B + Φ3D + Φ4D
•
2 output mode: VOS3 and VOS4:
VOS3: ΦL1 = Φ1A + Φ2A + Φ2C + Φ3C
ΦL2 = Φ3A + Φ4A + Φ1C + Φ4C
VOS4: ΦL1 = Φ1B + Φ2B + Φ2D + Φ3D
ΦL2 = Φ3B + Φ4B + Φ1D + Φ4D
Note:
In 2 output mode, the unused outputs can be connected as following:
• ΦLS = ΦR = VGS = 0V
• 10V < VDR < 15V
• VDD = 15V
• VS not connected in order to cancel unused output amplifiers power consumption.
Absolute Maximum Ratings*
Storage Temperature ................................... -55°C to + 150°C
Operating Temperature .................................
0°C to + 70°C
Thermal Cycling.........................................................15°C/mm
*NOTICE:
Stresses above those listed under absolute maximum ratings may cause permanent device failure. Functionality at or above these limits is not
implied. Exposure to absolute maximum ratings
for extended periods may affect reliability.
Maximum Voltage:
• Pins: 4, 6, 7, 8, 10, 11, 12, 13, 16, 17, 18,
19, 21, 23, 32, 34, 35, 36, 38, 39, 40, 41, 44,
45, 46, 47, 49, 51...............................................-0.3V to + 15V
• Pins: 2, 3, 22, 25, 26, 27, 30,
31, 50, 53, 54, 55............................................-0.3V to + 15.5V
• Pins: 5, 9, 14, 15, 20, 24, 33, 37, 42, 43, 48, 52 .. Ground 0V
Operating Range
Operating range defines the temperature limits between which the functionality is guaranteed: 0°C to 70°C.
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1997A–IMAGE–05/02
Operating
Precautions
Shorting the video outputs to VSS or VDD, even temporarily, can permanently damage
the output amplifiers.
Operating Conditions (T = 25°C)
Table 1. DC Characteristics
Value
Parameter
Symbol
Min.
Typ.
Max.
Unit
VDD1-2, VDD3-4
14.5
15
15.5
V
VSS
0
0
V
VDR1, VDR2, VDR3, VDR4
VDD - 0.5
V
VS1, VS2, VS3, VS4
0
V
Output Amplifier Drain Supply
Substrate Voltage
Reset DC Bias
Output Amplifier Source Bias
Output Gate DC Bias
VGS1-2, VGS3-4
2.2
2.4
2.6
V
VST
3.5
4
4.5
V
VA1-2, VA3-4
14
14.5
15
V
Photosensitive Zone DC Bias
Antiblooming Diode Bias
Note:
If no exposure time control is required, ΦA1-2 and ΦA3-4 must be connected to an adjustable DC bias (see Figure 7).
Typical current in VDR, VA < 10 µA; in VGS, VST < 1 µA.
Timing Diagram
Figure 3. Line Timing Diagram
ΦP1-2
ΦP3-4
Φ L1, Φ L2
Φ LS1-2, Φ LS3-4
Φ R1-2, Φ R3-4
ΦEc1
(clamp)
External
ΦEch
(Sampling)
Detailed timing diagram
for transfert from
photosite to register
(see fig. 4)
Detailed pixel
timing diagram
(see fig. 5)
Pixel N
Cleaning
Readout time for line M
Integration time Ti for line M+1
•
Minimum exposure time: Ti min = readout time.
3043
For data rate of 5 MHz: Ti min = ----------------- = 608.6 µs.
5 MHz
Note:
6
It is better to clean the shift registers (with running clocks) and not to stop clocking them
after readout time.
TH7834C
1997A–IMAGE–05/02
TH7834C
•
Each video line in four output operating mode consists in:
–
30 inactive pre-scan, (not connected to pixels),
–
6 dark references,
–
4 isolation elements, (inactive, not connected to pixels),
–
3 non-useful pixels,
–
3 000 useful pixels of the line.
N = number of pixel periods (Tp) during readout period (see Figure 5).
Four output operating mode: N ≥ 3043.
Two output operating mode: N ≥ 6086.
(ΦLS can be clocked during the line blancking).
Figure 4. Detailed Timing Diagram For Transfer From Photosite To Register
ΦP1-2, ΦP3-4
≥ 20 ns
≥ 2 µs
ΦL1, ΦL2
≥ 100 ns
ΦLS
N
1
ΦR
Figure 5. Detailed Pixel Timing Diagram
Tp (200 ns Typ.)
ΦP1-2, ΦP3-4
ΦL1, ΦL2
Tp/2 Typ.
ΦLS1-2, ΦLS3-4
ΦR1-2, ΦR3-4
≥ 20 ns
≥ 30 ns
VOS (1-2-3-4)
(CCD output signal)
Reset
Signal
Floating
diode
(Reference level for
correlated double Sampling)
TP = Pixel period
Rise and fall time:
ΦR1-2, ΦR3-4: 5% of TP (min. 5 ns),
ΦLS1-2, ΦLS3-4: 5% of TP (min. 5 ns),
ΦL1, ΦL2: 25% of TP (min. 30 ns),
ΦP1-2, ΦP3-4: 100 ns (min 20 ns).
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1997A–IMAGE–05/02
Cross over of complementary clocks (ΦL1 and ΦL2) preferably at 50% of their amplitude.
Note:
Generally, the difference between the floating diode level and signal level is the sum of
several signals:
• Register clock feedthrough
• Average CCD register dark signal proportional to CCD clock period, mode, temperature
• Pixel dark signal (depending upon temperature and exposure time)
• Pixel signal under illumination
Table 2.
Elements
Inactive
Prescan
Dark
References
Isolation
Elements
Non Useful
Pixels
Useful Pixels
Register Clock Feedthrough
X
X
X
X
X
Average CCD Register Dark Signal
X
X
X
X
X
X
X
X
X
Signals
Pixel Dark Signal
X
Pixel Signal Under Illumination
Table 3. Drive Clock Voltage Swings
Value
Parameter
Symbol
Register Main Transport Clock(1)
ΦL1, ΦL2
Register End Transport Clock(1)
ΦLS1-2,
ΦLS3-4
Antiblooming (Low Level) And
Exposure Time Control (High Level)(1)
ΦA1-2, ΦA3-4
Reset Clock(1)
ΦR1-2, ΦR3-4
Transfer Clock(1)
Note:
8
ΦP1-2, ΦP3-4
Logic
Min.
Typ.
Max.
Unit
High
8.5
9
11
V
Low
0
0.4
0.6
V
High
8.5
9
11
V
Low
0
0.2
0.4
V
High
9.5
10
10.5
V
Low
0
To be
adjusted
High
10.5
11
12.5
V
Low
0
1.5
2
V
High
10.5
11
11.5
V
Low
0
0.4
0.6
V
V
1. Transients under 0.0V in the clock pulses will lead to charge injection, causing a localized increase of the dark signal. If such
spurious negative transients are present, they can be removed by inserting a serial resistor of appropriate value (typically
20 Ω to 100 Ω) at the relevant driver output.
TH7834C
1997A–IMAGE–05/02
TH7834C
Table 4. Drive Clock Capacitances Operating Frequencies(1)
Symbol
Function/Clock
Capacitive Network
ΦL1
ΦL1, ΦL2
Register Main Transport Clock
ΦLS1-2, ΦLS3-4
Register End Transfer Clock
ΦP1-2, ΦP3-4
160pF
ΦL2
250pF
320pF
Total
Max. Frequency
ΦL1: 570 pF
ΦL2: 640 pF
for one CCD(1)
10 MHz
≤ 50 pF per phase
10 MHz
80 pF per phase
Pulse duration ≥ 2 µs
Period: ≥ 608.6 µs
(4 outputs mode)
ΦP
15pF
15pF
VST
Transfer Clock
ΦL2
50pF
VSS
15pF
ΦA1-2, ΦA3-4
Antiblooming And Exposure
Time Control
VST
ΦA
60pF
VSS
Reset Clock
ΦR1-2, ΦR3-4
Note:
1. For ¼ of total CCD register.
100 pF per phase
≤ 50 pF per phase
10 MHz
Table 5. Static and Dynamic Electrical Characteristics
Value
Parameter
Symbol
Min.
Typ.
Max.
Unit
Remarks
DC Output Level (Pins: 1, 28, 29, 56)
Vref
10
Output Impedance (Pins: 1, 28, 29,
56)
ZS
400
600
Ω
Maximum Data Output Frequency
Per Channel
FS max
5
10
MHz
Ie
<< 1
2
µA
Vin = 15V
with all other
pins = 0V
IDD1-2, IDD3-4
10
16
mA
VDD = 15V
Input Current On Active Pins 4, 6, 7,
8, 10, 11, 12, 13, 16, 17, 18, 19, 21,
23, 32, 34, 35, 36, 38, 39, 40, 41, 44,
45, 46, 47, 49, 51
Amplifier Drain Supply Current (Per
VDD)
V
(Note:)
Static Power Dissipation (Per VDD)
PD1-2, PD3-4
165
240
mW
Note:
The maximum clock frequency is limited by the dark signal increase. Full performance for 5 MHz.
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1997A–IMAGE–05/02
Electro-optical
Performance
•
General measurement conditions: Tc = 25°C; Ti = 1 ms; FΦLA, FΦLB, FΦLC, FΦLD =
5 MHz, readout through 4 outputs.
•
Light source: tungsten filament lamp (2,854 K) + BG 38 filter (2 mm thick) + F/3.5
aperture. The BG 38 filter limits the spectrum to 700 nm. In these conditions,
1 µJ/cm2 corresponds to 3.5 lux.s.
•
Typical operating conditions (see Table 1, 2, 3 and 4). First and last pixels of the
photosensitive line, as well as reference elements, are excluded from the
specification.
•
Test without antiblooming, except for AE max.
Table 6. Electro-optical Performance
Value
Parameter
Symbol
Min.
Typ.
Saturation Output Voltage With
Antiblooming OFF
VSAT
2
3
V
Saturation Exposure
ESAT
0.6
µJ/cm2
5
V/µJ/cm2
Responsitivity
Photo Response Non-uniformity
Excluding Single Defects
Contrast Transfer Function At Nyquist
Frequency (77 Ip/mm)
at 500 nm
at 600 nm
at 700 nm
R
3.5
Unit
Remarks
(1)(2)(3)
% VOS
VOS = 1.0V(4)
75
62
47
%
%
%
VOS = 1.5V
For white level
300
µV
(5)
PRNU
±6
CTF
Temporal Noise In Darkness (rms)
Max.
± 10
Dynamic Range (Relative to rms
Noise)
DR
10000
Pixel Average Dark Signal
VDS
110
250
µV/ms
(6)
Dark Signal Non-uniformity
DSNU
90
400
µV/ms
Peak to peak(6)
Register Single Stage Transfer
Efficiency
1-ε
Lag (Vertical Charge Transfer
Efficiency)
VCTE
0.99998
VOS = 1V
0.999998
0.1
0.5
%
(7)
(8)
Antiblooming Efficiency
AE max
<1
15
mV
Notes: 1. Value measured with respect to zero reference level.
2. Conversion factor is typically: 6 µV/e-.
3. Without antiblooming: ΦA1-2 = ΦA3-4 = 0V.
4. VOS = average output voltage; PRNU for each output, in 4 output operating mode.
5. Measured in Correlated Double Sampling (C.D.S.) mode.
6. VDS and DSNU vary with temperature.
7. Residual signal after line readout, at VOS= 1V.
8. Line acquisition with Phi-A at high level. AE max = maximum signal along the line (to test all the antiblooming sites).
10
TH7834C
1997A–IMAGE–05/02
TH7834C
Figure 6. Typical Spectral Responsitivity
8.0
η=0.8
η=0.7
7.2
η=0.6
6.4
(V/µJ/cm 2)
5.6
4.8
4.0
3.2
2.4
1.6
0.8
0
400
500
600
700
800
900
1000
1100
Lambda (nm)
Figure 7. VSAT versus ΦA Low Level Typical Curve
Vsat. (mV)
Antiblooming
OFF
Antiblooming
ON
3600
3400
3200
3000
2800
2600
2400
2200
2000
1800
1600
1400
1200
1000
800
600
400
200
0
VST = 4 V
Φ R Low level = 1.5V
VA = 13V
0
1
2
3
4
5
6
7
8 8.5
ΦA bias (V)
Exposure Time
Reduction (See
Figure 8)
TH7834 allows a reduction in the exposure time without changing the readout time. It
thus provides a function which is equivalent to an optical iris.
The exposure time reduction consists in increasing the ΦA gate bias in order to remove
continuously, during period 2, the photoelectrons from the pixel and to inject them into
the antiblooming diode VA. When ΦA returns to the normal bias, electrons are integrated
in the pixel.
Only excess electrons are evacuated into VA (blooming control). Thus, the actual integration time is ti instead of Ti, without any change in the readout sequence. Register
transfer and reset clocks (ΦL, ΦLS and ΦR) must be pulsed during the Ti integration time.
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1997A–IMAGE–05/02
Table 7. Exposure Time Reduction Conditions
Value
Parameter
Symbol
Min.
Typ.
Max.
Unit
Antiblooming Diode Bias
VA1-2. VA3-4
14
15.5
15
V
Antiblooming And Expose Time
Control
Period 1
ΦA1-2, ΦA3-4
Period 2
to be adjusted
9.5
V
10
10.5
V
Figure 8. Timing Diagram For Exposure Time Control
ΦP(1-2, 3,4)
ΦA(1-2, 3,4)
0V
Clear period
Period 2
Antiblooming
level
≥TR
∆t ≥ 20ns
Period 1
integration time ti
TR = Readout period
It is better to have ΦA falling/rising edge outside the useful readout period.
Note:
3.2
4.2
9.71 ± 0.6
68.58 ± 0.25
(2.54 × 27)
4.35 ± 0.45
1.27 ± 0.25
1
2.12 ± 0.27
PIXEL 1 MARK
1.10 ± 0.10
3.15 ± 0.32
2.54 ± 0.25
Outline Drawing
3
2
15.24 ±0.25
Z=1.80±0.30
88.0 ±0.88.
7.50 ± 0.10
Y
Note:
X
5.00 ± 0.10
pixel 12000
|Y12000-Y1| ≤ 150 µm
Window
2
Photosensitive area
3
Optical distance between
external face of window
and photosensitive area
Antireflective window: reflection.
Less than 1% per side over 400 - 700 nm wavelength range.
All dimensions are in mm (except otherwise specified).
Ordering Code
12
1st pixel
1
The ordering code is TH7834CCC-RB
TH7834C
1997A–IMAGE–05/02
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Atmel Operations
Corporate Headquarters
Memory
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TEL 1(408) 441-0311
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Microcontrollers
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44306 Nantes Cedex 3, France
TEL (33) 2-40-18-18-18
FAX (33) 2-40-18-19-60
Asia
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimhatsui
East Kowloon
Hong Kong
TEL (852) 2721-9778
FAX (852) 2722-1369
RF/Automotive
ASIC/ASSP/Smart Cards
Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
TEL (81) 3-3523-3551
FAX (81) 3-3523-7581
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TEL 1(719) 576-3300
FAX 1(719) 540-1759
Biometrics/Imaging/Hi-Rel MPU/
High Speed Converters/RF Datacom
Avenue de Rochepleine
BP 123
38521 Saint-Egreve Cedex, France
TEL (33) 4-76-58-30-00
FAX (33) 4-76-58-34-80
Zone Industrielle
13106 Rousset Cedex, France
TEL (33) 4-42-53-60-00
FAX (33) 4-42-53-60-01
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TEL 1(719) 576-3300
FAX 1(719) 540-1759
Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
TEL (44) 1355-803-000
FAX (44) 1355-242-743
e-mail
[email protected]
Web Site
http://www.atmel.com
© Atmel Corporation 2002.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical
components in life support devices or systems.
ATMEL ® is the registered trademarks of Atmel.
Other terms and product names may be the trademarks of others.
Printed on recycled paper.
1997A–IMAGE–05/02
0M