PHILIPS SSTUM32865ET

SSTUM32865
1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-800
RDIMM applications
Rev. 01 — 19 September 2007
Product data sheet
1. General description
The SSTUM32865 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank
by four (2R × 4) and similar high-density Double Data Rate 2 (DDR2) memory modules. It
is similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the
functionality of the normally required two registers in a single package, thereby freeing up
board real-estate and facilitating routing to accommodate high-density Dual In-line
Memory Module (DIMM) designs.
The SSTUM32865 also integrates a parity function, which accepts a parity bit from the
memory controller, compares it with the data received on the D-inputs and indicates
whether a parity error has occurred on its open-drain PTYERR pin (active LOW).
It further offers added features over the JEDEC standard register in that it is permanently
configured for high output drive strength. This allows use in high density designs with
heavier than normal net loading conditions. Furthermore, the SSTUM32865 features two
additional chip select inputs, which allow more versatile enabling and disabling in densely
populated memory modules. Both added features (drive strength and chip selects) are
fully backward compatible to the JEDEC standard register.
The SSTUM32865 is packaged in a 160-ball, 12 × 18 grid, 0.65 mm ball pitch, thin profile
fine-pitch ball grid array (TFBGA) package, which, while requiring a minimum
9 mm × 13 mm of board space, allows for adequate signal routing and escape using
conventional card technology.
2. Features
n 28-bit data register supporting DDR2
n Fully compliant to JEDEC standard for SSTUB32865
n Supports 2 rank by 4 DIMM density by integrating equivalent functionality of two
JEDEC-standard DDR2 registers (that is, 2 × SSTUB32864 or 2 × SSTUB32866)
n Parity checking function across 22 input data bits
n Parity out signal
n Controlled multi-impedance output impedance drivers enable optimal signal integrity
and speed
n Meets or exceeds SSTUB32865 JEDEC standard speed performance
n Supports up to 450 MHz clock frequency of operation
n Permanently configured for high output drive
n Optimized pinout for high-density DDR2 module design
n Chip-selects minimize power consumption by gating data outputs from changing state
n Two additional chip select inputs allow optional flexible enabling and disabling
SSTUM32865
NXP Semiconductors
1.8 V DDR2-800 registered buffer with parity
n
n
n
n
n
Supports Stub Series Terminated Logic SSTL_18 data inputs
Differential clock (CK and CK) inputs
Supports LVCMOS switching levels on the control and RESET inputs
Single 1.8 V supply operation (1.7 V to 2.0 V)
Available in 160-ball 9 mm × 13 mm, 0.65 mm ball pitch TFBGA package
3. Applications
n 400 MT/s to 800 MT/s high-density (for example, 2 rank by 4) DDR2 registered DIMMs
n DDR2 Registered DIMMs (RDIMM) desiring parity checking functionality
4. Ordering information
Table 1.
Ordering information
Type number
Solder process
Package
Name
Description
Version
SSTUM32865ET/G
Pb-free (SnAgCu solder ball TFBGA160 plastic thin fine-pitch ball grid array package; SOT802-2
compound)
160 balls; body 9 × 13 × 0.7 mm
SSTUM32865ET/S
Pb-free (SnAgCu solder ball TFBGA160 plastic thin fine-pitch ball grid array package; SOT802-2
compound)
160 balls; body 9 × 13 × 0.7 mm
4.1 Ordering options
Table 2.
Ordering options
Type number
Topside mark
Temperature range
SSTUM32865ET/G
SSTUM32865ET
Tamb = 0 °C to +70 °C
SSTUM32865ET/S
SSTUM32865ETS
Tamb = 0 °C to +85 °C
SSTUM32865_1
Product data sheet
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Rev. 01 — 19 September 2007
2 of 28
SSTUM32865
NXP Semiconductors
1.8 V DDR2-800 registered buffer with parity
5. Functional diagram
(CS ACTIVE)
VREF
PARITY
GENERATOR
AND
CHECKER
D Q
PARIN
22
R
SSTUM32865
PTYERR
Q0A
D Q
D0
Q0B
R
Q21A
D Q
D21
Q21B
R
QCS0A
DCS0
D Q
QCS0B
R
CSGATEEN
QCS1A
DCS1
D Q
QCS1B
R
DCS2
DCS3
DCKE0,
DCKE1
2
D Q
2
QCKE0B,
QCKE1B
R
DODT0,
DODT1
2
D Q
QCKE0A,
QCKE1A
2
R
QODT0A,
QODT1A
QODT0B,
QODT1B
RESET
CK
CK
002aac647
Fig 1. Functional diagram of SSTUM32865
SSTUM32865_1
Product data sheet
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Rev. 01 — 19 September 2007
3 of 28
SSTUM32865
NXP Semiconductors
1.8 V DDR2-800 registered buffer with parity
6. Pinning information
6.1 Pinning
SSTUM32865ET/G
SSTUM32865ET/S
ball A1
index area
2
1
4
3
6
5
8
7
9
10 12
11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
002aac648
Transparent top view
Fig 2. Pin configuration for TFBGA160
SSTUM32865_1
Product data sheet
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Rev. 01 — 19 September 2007
4 of 28
SSTUM32865
NXP Semiconductors
1.8 V DDR2-800 registered buffer with parity
1
2
3
4
5
6
7
8
9
10
11
12
A
VREF
n.c.
PARIN
n.c.
n.c.
QCKE1A
QCKE0A
Q21A
Q19A
Q18A
Q17B
Q17A
B
D1
D2
n.c.
n.c.
n.c.
QCKE1B
QCKE0B
Q21B
Q19B
Q18B
QODT0B
QODT0A
C
D3
D4
QODT1B
QODT1A
D
D6
D5
VDDL
GND
n.c.
n.c.
GND
GND
Q20B
Q20A
E
D7
D8
VDDL
GND
VDDL
VDDR
GND
GND
Q16B
Q16A
F
D11
D9
VDDL
GND
VDDR
VDDR
Q1B
Q1A
G
D18
D12
VDDL
GND
VDDR
VDDR
Q2B
Q2A
H
CSGATEEN
D15
DCS2
GND
GND
GND
Q5B
Q5A
J
CK
DCS0
GND
GND
VDDR
VDDR
QCS0B
QCS0A
K
CK
DCS1
DCS3
VDDL
GND
GND
QCS1B
QCS1A
L
RESET
D14
GND
GND
VDDR
VDDR
Q6B
Q6A
M
D0
D10
GND
GND
GND
GND
Q10B
Q10A
N
D17
D16
VDDL
VDDL
VDDR
VDDR
Q9B
Q9A
P
D19
D21
GND
VDDL
VDDL
VDDR
VDDR
GND
Q11B
Q11A
R
D13
D20
GND
VDDL
VDDL
GND
GND
GND
Q15B
Q15A
T
DODT1
DODT0
Q14B
Q14A
U
DCKE0
DCKE1
MCL
PTYERR
MCH
Q3B
Q12B
Q7B
Q4B
Q13B
Q0B
Q8B
V
VREF
MCL
MCL
n.c.
MCH
Q3A
Q12A
Q7A
Q4A
Q13A
Q0A
Q8A
002aac650
160-ball, 12 × 18 grid; top view.
An empty cell indicates no ball is populated at that grid point.
n.c. denotes a no-connect (ball present but not connected to the die).
MCL denotes a pin that must be connected LOW.
MCH denotes a pin that must be connected HIGH.
Fig 3. Ball mapping
SSTUM32865_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 19 September 2007
5 of 28
SSTUM32865
NXP Semiconductors
1.8 V DDR2-800 registered buffer with parity
6.2 Pin description
Table 3.
Pin description
Symbol
Pin
Type
Description
DCKE0, DCKE1
U1, U2
SSTL_18
DRAM function pins not associated with Chip Select.
DODT0, DODT1
T2, T1
Ungated inputs
Chip Select gated inputs
D0 to D21
M1, B1, B2, C1, C2, D2, D1, SSTL_18
E1, E2, F2, M2, F1, G2, R1,
L2, H2, N2, N1, G1, P1, R2,
P2
DRAM inputs, re-driven only when Chip Select is LOW.
J2, K2, H4, K4
DRAM Chip Select signals. These pins initiate DRAM
address/command decodes, and as such at least one will
be LOW when a valid address/command is present. The
register can be programmed to re-drive all D-inputs only
(CSGATEEN = HIGH) when at least one Chip Select
input is LOW. DCS2 and DCS3 are not re-driven and can
be left open-circuit to default HIGH by means of its
internal pull-up resistors.
Chip Select inputs
DCS0, DCS1,
DCS2, DCS3[1]
SSTL_18
Re-driven outputs
Q0A to Q21A
V11, F12, G12, V6, V9, H12, SSTL_18
L12, V8, V12, N12, M12,
P12, V7, V10, T12, R12,
E12, A12, A10, A9, D12, A8
Q0B to Q21B
U11, F11, G11, U6, U9,
H11, L11, U8, U12, N11,
M11, P11, U7, U10, T11,
R11, E11, A11, B10, B9,
D11, B8
QCS0A, QDS1A,
QCS0B, QCS1B
J12, K12, J11, K11
QCKE0A, QCKE1A,
QCKE0B, QCKE1B
A7, A6, B7, B6
Outputs of the register, valid after the specified clock
count and immediately following a rising edge of the
clock.
QODT0A, QODT1A, B12, C12, B11, C11
QODT0B, QODT1B
Parity input
PARIN
A3
SSTL_18
Parity input for the D0 to D21 inputs. Arrives one clock
cycle after the corresponding data input.
U4
open-drain
When LOW, this output indicates that a parity error was
identified associated with the address and/or command
inputs. PTYERR will be active for two clock cycles, and
delayed by an additional clock cycle for compatibility with
final parity out timing on the industry-standard DDR2
register with parity (in JEDEC definition).
Parity error
PTYERR
SSTUM32865_1
Product data sheet
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Rev. 01 — 19 September 2007
6 of 28
SSTUM32865
NXP Semiconductors
1.8 V DDR2-800 registered buffer with parity
Table 3.
Pin description …continued
Symbol
Pin
Type
Description
H1
1.8 V
LVCMOS
with weak
pull-up
Chip Select Gate Enable. When HIGH, the D0 to D21
inputs will be latched only when at least one Chip Select
input is LOW during the rising edge of the clock. When
LOW, the D0 to D21 inputs will be latched and redriven
on every rising edge of the clock.
J1, K1
SSTL_18
Differential master clock input pair to the register. The
register operation is triggered by a rising edge on the
positive clock input (CK).
Program inputs
CSGATEEN
Clock inputs
CK, CK
Miscellaneous inputs
MCL
U3, V2, V3
Must be connected to a logic LOW.
MCH
U5, V5
Must be connected to a logic HIGH.
RESET
L1
1.8 V
LVCMOS
with weak
pull-up
Asynchronous reset input. When LOW, it causes a reset
of the internal latches, thereby forcing the outputs LOW.
RESET also resets the PTYERR signal.
VREF
A1, V1
0.9 V
nominal
Input reference voltage for the SSTL_18 inputs. Two pins
(internally tied together) are used for increased reliability.
VDDL
D4, E4, E6, F4, G4, K5, N4,
N5, P5, P6, R5, R6
Power supply voltage.
VDDR
E7, F8, F9, G8, G9, J8, J9,
L8, L9, N8, N9, P7, P8
Power supply voltage.
GND
D5, D8, D9, E5, E8, E9, F5,
G5, H5, H8, H9, J4, J5, K8,
K9, L4, L5, M4, M5, M8, M9,
P4, P9, R4, R7, R8, R9
Ground.
n.c.
A2, A4, A5, B3, B4, B5, D6,
D7, V4
Ball present but not connected to die.
[1]
If application does not require DCS2 and DCS3, it is allowed to connect H4 and K4 to VDD.
SSTUM32865_1
Product data sheet
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Rev. 01 — 19 September 2007
7 of 28
SSTUM32865
NXP Semiconductors
1.8 V DDR2-800 registered buffer with parity
7. Functional description
7.1 Function table
Table 4.
Function table (each flip-flop)
Outputs[1]
Inputs
RESET
DCS0[2] DCS1[2]
CSGATEEN
CK
CK
Dn, DODTn, DCKEn
Qn
QCS0
QCS1
QODTn,
QCKEn
H
L
L
X
↑
↓
L
L
L
L
L
H
L
L
X
↑
↓
H
H
L
L
H
H
L
L
X
L or H
L or H
X
Q0
Q0
Q0
Q0
H
L
H
X
↑
↓
L
L
L
H
L
H
L
H
X
↑
↓
H
H
L
H
H
H
L
H
X
L or H
L or H
X
Q0
Q0
Q0
Q0
H
H
L
X
↑
↓
L
L
H
L
L
H
H
L
X
↑
↓
H
H
H
L
H
H
H
L
X
L or H
L or H
X
Q0
Q0
Q0
Q0
H
H
H
L
↑
↓
L
L
H
H
L
H
H
H
L
↑
↓
H
H
H
H
H
H
H
H
L
L or H
L or H
X
Q0
Q0
Q0
Q0
H
H
H
H
↑
↓
L
Q0
H
H
L
H
H
H
H
↑
↓
H
Q0
H
H
H
H
H
H
H
L or H
L or H
X
Q0
Q0
Q0
Q0
L
X or
floating
X or
floating
X or floating
X or
floating
X or
floating
X or floating
L
L
L
L
[1]
Q0 is the previous state of the associated output.
[2]
DCS2 and DCS3 operate identically to DCS0 and DCS1, except they do not have corresponding re-driven (QCS) outputs.
Table 5.
Parity and standby function table
Inputs
Output
∑ of inputs = H
(D0 to D21)
PARIN[2]
PTYERR[3][4]
↓
even
L
H
↑
↓
odd
L
L
H
↑
↓
even
H
L
H
↑
↓
odd
H
H
H
L
↑
↓
even
L
H
H
H
L
↑
↓
odd
L
L
H
H
L
↑
↓
even
H
L
H
H
L
↑
↓
odd
H
H
H
H
H
↑
↓
X
X
PTYERR0
H
X
X
L or H
L or H
X
X
PTYERR0
L
X or floating
X or floating
X or floating
X or floating
X or floating
X or floating
H
RESET
DCS0[1]
DCS1[1]
CK
CK
H
L
H
↑
H
L
H
H
L
H
L
H
SSTUM32865_1
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Rev. 01 — 19 September 2007
8 of 28
SSTUM32865
NXP Semiconductors
1.8 V DDR2-800 registered buffer with parity
[1]
DCS2 and DCS3 operate identically to DCS0 and DCS1 with regard to the parity function.
[2]
PARIN arrives one clock cycle after the data to which it applies. All Dn inputs must be driven to a known state for parity to be calculated
correctly.
[3]
This condition assumes PTYERR is HIGH at the crossing of CK going HIGH and CK going LOW. If PTYERR is LOW, it stays latched
LOW for two clock cycles or until RESET is driven LOW. CSGATEEN is ‘don’t care’ for PTYERR.
[4]
PTYERR0 is the previous state of output PTYERR.
7.2 Functional information
This 28-bit 1 : 2 registered buffer with parity is designed for 1.7 V to 2.0 V VDD operation.
All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The
control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized
to drive the DDR2 DIMM load.
The SSTUM32865 operates from a differential clock (CK and CK). Data are registered at
the crossing of CK going HIGH, and CK going LOW.
The device supports low-power standby operation. When the reset input (RESET) is LOW,
the differential input receivers are disabled, and undriven (floating) data, clock and
reference voltage (VREF) inputs are allowed. In addition, when RESET is LOW all
registers are reset, and all outputs except PTYERR are forced LOW. The LVCMOS
RESET input must always be held at a valid logic HIGH or LOW level.
To ensure defined outputs from the register before a stable clock has been supplied,
RESET must be held in the LOW state during power-up.
In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with
respect to CK and CK. Therefore, no timing relationship can be guaranteed between the
two. When entering reset, the register will be cleared and the data outputs will be driven
LOW quickly, relative to the time to disable the differential input receivers. However, when
coming out of reset, the register will become active quickly, relative to the time to enable
the differential input receivers. As long as the data inputs are LOW, and the clock is stable
during the time from the LOW-to-HIGH transition of RESET until the input receivers are
fully enabled, the design of the SSTUM32865 ensures that the outputs remain LOW, thus
ensuring no glitches on the output.
The device monitors DCS0, DCS1, DCS2 and DCS3 inputs and will gate the Qn outputs
from changing states when all DCSn inputs are HIGH. If DCSn input is LOW, the Qn
outputs will function normally. The RESET input has priority over the DCSn control and
will force the Qn outputs LOW and the PTYERR output HIGH. If the DCSn-control
functionality is not desired, then the CSGATEEN input can be hardwired to ground, in
which case, the set-up time requirement for DCSn would be the same as for the other Dn
data inputs.
The SSTUM32865 includes a parity checking function. The SSTUM32865 accepts a
parity bit from the memory controller at its input pin PARIN, compares it with the data
received on the Dn inputs (with either DCSn inputs active) and indicates whether a parity
error has occurred on its open-drain PTYERR pin (active LOW).
SSTUM32865_1
Product data sheet
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Rev. 01 — 19 September 2007
9 of 28
SSTUM32865
NXP Semiconductors
1.8 V DDR2-800 registered buffer with parity
7.3 Functional differences to SSTU32864
The SSTUM32865 for its basic register functionality, signal definition and performance is
based upon the industry-standard SSTU32864, but provides key operational features
which differ (at least in part) from the industry-standard register in the following aspects:
7.3.1 Chip Select (CS) gating of key inputs (DCS0, DCS1, DCS2, DCS3,
CSGATEEN)
As a means to reduce device power, the internal latches will only be updated when one or
more of the CS inputs are active (LOW) and CSGATEEN HIGH at the rising edge of the
clock. The 22 ‘Chip-Select-gated’ input signals associated with this function include
addresses (ADDR0 to ADDR15, BA0 to BA2), and RAS, CAS, WE, with the remaining
signals (CS, CKE, ODT) continuously re-driven at the rising edge of every clock as they
are independent of CS. The CS gating function can be disabled by tying CSGATEEN
LOW, enabling all internal latches to be updated on every rising edge of the clock.
Table 6.
Chip Select gating mode
Mode
Signal name
Description
Gating
CSGATEEN
Registers only re-drive signals to the DRAMs when
Chip Select inputs are LOW.
HIGH
Non-gating
CSGATEEN
LOW
Registers always re-drive signals on every clock cycle,
independent of the state of the Chip Select inputs.
7.3.2 Parity error checking and reporting
The SSTUM32865 incorporates a parity function, whereby the signal received on input pin
PARIN is received as parity to the register, one clock cycle later than the CS-gated inputs.
The received parity bit is then compared to the parity calculated across these same inputs
by the register parity logic to verify that the information has not been corrupted. The 22
CS-gated input signals will be latched and re-driven on the first clock, and any error will be
reported one clock cycle later via the PTYERR output pin (driven LOW for two consecutive
clock cycles). PTYERR is an open-drain output, allowing multiple modules to share a
common signal pin for reporting the occurrence of a parity error during a valid command
cycle (coincident with the re-driven signals). This output is driven LOW for two consecutive
clock cycles to allow the memory controller sufficient time to sense and capture the error
even. A LOW state on PTYERR indicates that a parity error has occurred.
7.3.3 Reset (RESET)
Similar to the RESET pin on the industry-standard SSTU32864, this pin is used to clear all
internal latches and all outputs will be driven LOW quickly except the PTYERR output,
which will be floated (and will normally default HIGH by their external pull-up).
7.3.4 Power-up sequence
The reset function for the SSTUM32865 is similar to that of the SSTU32864 except that
the PTYERR signal is also cleared and will be held clear (HIGH) for three consecutive
clock cycles.
SSTUM32865_1
Product data sheet
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Rev. 01 — 19 September 2007
10 of 28
SSTUM32865
NXP Semiconductors
1.8 V DDR2-800 registered buffer with parity
RESET
DCSn
m
m+1
m+2
m+3
m+4
CK
CK
tACT
tsu
th
Dn (1)
tPDM, tPDMSS
CK to Q
Qn
tsu
th
PARIN
tPHL
tPHL, tPLH
CK to PTYERR
CK to PTYERR
PTYERR
002aaa983
HIGH, LOW, or Don't care
HIGH or LOW
(1) After RESET is switched from LOW to HIGH, all data and PARIN input signals must be set and held LOW for a minimum
time of tACT(max) to avoid false error.
Fig 4. RESET switches from LOW to HIGH
SSTUM32865_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 19 September 2007
11 of 28
SSTUM32865
NXP Semiconductors
1.8 V DDR2-800 registered buffer with parity
RESET
DCSn
m+1
m
m+2
m+3
m+4
CK
CK
tsu
th
Dn (1)
tPDM, tPDMSS
CK to Q
Qn
tsu
th
PARIN
tPHL, tPLH
CK to PTYERR
PTYERR
Unknown input event
Output signal is dependent
on the prior unknown event
002aaa984
HIGH or LOW
Fig 5. RESET being held HIGH
SSTUM32865_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 19 September 2007
12 of 28
SSTUM32865
NXP Semiconductors
1.8 V DDR2-800 registered buffer with parity
RESET
tINACT
DCSn
CK (1)
CK (1)
Dn (1)
tPHL
RESET to Q
Qn
PARIN (1)
tPLH
RESET to PTYERR
PTYERR
002aac649
HIGH, LOW, or Don't care
HIGH or LOW
(1) After RESET is switched from HIGH to LOW, all data and clock input signals must be set and held at valid logic levels (not
floating) for a minimum time of tINACT(max).
Fig 6. RESET switches from HIGH to LOW
SSTUM32865_1
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Rev. 01 — 19 September 2007
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SSTUM32865
NXP Semiconductors
1.8 V DDR2-800 registered buffer with parity
22
Dn
D Q
22
QnA
QnB
D
PARIN
D
PTYERR
LATCHING AND
RESET FUNCTION(1)
D
CLOCK
002aaa417
(1) This function holds the error for two cycles. For details, see Section 7 “Functional description” and Figure 4 “RESET
switches from LOW to HIGH”.
Fig 7. Parity logic diagram
SSTUM32865_1
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1.8 V DDR2-800 registered buffer with parity
8. Limiting values
Table 7.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDD
supply voltage
Conditions
Min
Max
Unit
V
−0.5
+2.5
−0.5
+2.5
V
−0.5
VDD + 0.5
V
VI
input voltage
receiver
[1]
VO
output voltage
driver
[1]
IIK
input clamping current
VI < 0 V or VI > VDD
-
−50
mA
IOK
output clamping current
VO < 0 V or VO > VDD
-
±50
mA
IO
output current
continuous; 0 V < VO < VDD
-
±50
mA
IDDC
continuous current through
each VDD[2] or GND pin
-
±100
mA
Tstg
storage temperature
−65
+150
°C
Vesd
electrostatic discharge
voltage
Human Body Model (HBM); 1.5 kΩ; 100 pF
2
-
kV
Machine Model (MM); 0 Ω; 200 pF
150
-
V
[1]
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
Pins VDDL or VDDR.
9. Recommended operating conditions
Table 8.
Recommended operating conditions
Symbol
Parameter
VDD
supply voltage
1.7
-
2.0
V
Vref
reference voltage
0.49 × VDD
0.50 × VDD
0.51 × VDD
V
VT
termination voltage
Vref − 0.040
Vref
Vref + 0.040
V
VI
input voltage
V
Conditions
Min
Typ
Max
0
-
VDD
Unit
VIH(AC)
AC HIGH-level input voltage
data inputs (Dn)
[1]
Vref + 0.250
-
-
V
VIL(AC)
AC LOW-level input voltage
data inputs (Dn)
[1]
-
-
Vref − 0.250
V
VIH(DC)
DC HIGH-level input voltage
data inputs (Dn)
[1]
Vref + 0.125
-
-
V
data inputs (Dn)
[1]
-
-
Vref − 0.125
V
0.65 × VDD
-
-
V
-
-
0.35 × VDD
V
1.125
V
VIL(DC)
DC LOW-level input voltage
VIH
HIGH-level input voltage
RESET
[2]
VIL
LOW-level input voltage
RESET
[2]
VICR
common mode input voltage
range
CK, CK
0.675
-
VID
differential input voltage
CK, CK
600
-
-
mV
IOH
HIGH-level output current
-
-
−8
mA
IOL
LOW-level output current
-
-
8
mA
Tamb
ambient temperature
operating in free air
SSTUM32865ET/G
0
-
+70
°C
SSTUM32865ET/S
0
-
+85
°C
[1]
The differential inputs must not be floating, unless RESET is LOW.
[2]
The RESET input of the device must be held at valid logic levels (not floating) to ensure proper device operation.
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1.8 V DDR2-800 registered buffer with parity
10. Characteristics
Table 9.
Characteristics
Over recommended operating conditions, unless otherwise noted.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VOH
HIGH-level output voltage
IOH = −6 mA; VDD = 1.7 V
1.2
-
-
V
VOL
LOW-level output voltage
IOL = 6 mA; VDD = 1.7 V
-
-
0.5
V
II
input current
all inputs; VI = VDD or GND;
VDD = 2.0 V
-
-
±5
µA
IDD
supply current
static standby current;
RESET = GND; VDD = 2.0 V
-
-
2
mA
static operating current;
RESET = VDD; VDD = 2.0 V;
VI = VIH(AC) or VIL(AC)
-
-
40
mA
clock only; RESET = VDD;
VI = VIH(AC) or VIL(AC); CK and CK
switching at 50 % duty cycle.
IO = 0 mA; VDD = 1.8 V
-
16
-
µA
per each data input;
RESET = VDD;
VI = VIH(AC) or VIL(AC); CK and CK
switching at 50 % duty cycle. One
data input switching at half clock
frequency, 50 % duty cycle.
IO = 0 mA; VDD = 1.8 V
-
19
-
µA
data inputs; VI = Vref ± 250 mV;
VDD = 1.8 V
2.5
-
3.5
pF
CK and CK; VICR = 0.9 V;
VID = 600 mV; VDD = 1.8 V
2
-
3
pF
RESET; VI = VDD or GND;
VDD = 1.8 V
3
-
5
pF
-
7
-
Ω
-
53
-
Ω
IDDD
dynamic operating current per MHz
input capacitance
Ci
output impedance
Zo
instantaneous
steady-state
[1]
[1]
Instantaneous is defined as within < 2 ns following the output data transition edge.
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Table 10. Timing requirements
Over recommended operating conditions, unless otherwise noted.
Symbol
Parameter
fclock
clock frequency
tW
pulse width
Min
Typ
Max
Unit
-
-
450
MHz
1
-
-
ns
differential inputs active time
[1][2]
-
-
10
ns
tINACT
differential inputs inactive time
[1][3]
-
-
15
ns
tsu
set-up time
Chip Select; DCS0, DCS1
valid before clock
switching
0.6
-
-
ns
Data; Dn valid before
clock switching
0.5
-
-
ns
PARIN; PARIN before CK
and CK
0.5
-
-
ns
input to remain valid after
clock switching
0.4
-
-
ns
PARIN after CK and CK
0.4
-
-
ns
tACT
Conditions
CK, CK HIGH or LOW
hold time
th
[1]
This parameter is not necessarily production tested.
[2]
Data inputs must be active below a minimum time of tACT(max) after RESET is taken HIGH.
[3]
Data and clock inputs must be held at valid levels (not floating) a minimum time of tINACT(max) after RESET is taken LOW.
Table 11. Switching characteristics
Over recommended operating conditions, unless otherwise noted.
Symbol
Parameter
fmax
maximum input clock frequency
Conditions
[1]
Min
Typ
Max
Unit
450
-
-
MHz
tPDM
peak propagation delay
CK and CK to output
1.0
-
1.4
ns
tLH
LOW to HIGH delay time
CK and CK to PTYERR
1.2
-
3
ns
tHL
HIGH to LOW delay time
CK and CK to PTYERR
1
-
3
ns
tPLH
LOW-to-HIGH propagation delay
from RESET to PTYERR
-
-
3
ns
-
-
1.5
ns
-
-
3
ns
Min
Typ
Max
Unit
tPDMSS
simultaneous switching peak
propagation delay
CK and CK to output
tPHL
HIGH-to-LOW propagation delay
RESET to output
[1]
Includes 350 ps of test-load transmission line delay.
[2]
This parameter is not necessarily production tested.
[1][2]
Table 12. Output edge rates
Over recommended operating conditions, unless otherwise noted.
Symbol
Parameter
Conditions
dV/dt_r
rising edge slew rate
1
-
4
V/ns
dV/dt_f
falling edge slew rate
1
-
4
V/ns
dV/dt_∆
absolute difference between dV/dt_r
and dV/dt_f
-
-
1
V/ns
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1.8 V DDR2-800 registered buffer with parity
11. Test information
11.1 Test circuit
All input pulses are supplied by generators having the following characteristics:
Pulse Repetition Rate (PRR) ≤ 10 MHz; Z0 = 50 Ω; input slew rate = 1 V/ns ± 20 %,
unless otherwise specified.
The outputs are measured one at a time with one transition per measurement.
VDD
DUT
CK
CK
CK inputs
RL = 1000 Ω
delay = 350 ps
Zo = 50 Ω
50 Ω
OUT
CL = 30 pF(1)
RL = 1000 Ω
test point
RL = 100 Ω
test point
002aaa371
(1) CL includes probe and jig capacitance.
Fig 8. Load circuit
LVCMOS
VDD
0.5VDD
0.5VDD
RESET
0V
tINACT
IDD(1)
tACT
90 %
10 %
002aaa372
(1) IDD tested with clock and data inputs held at VDD or GND, and IO = 0 mA.
Fig 9. Voltage and current waveforms; inputs active and inactive times
tW
VIH
input
VICR
VICR
VID
VIL
002aaa373
VID = 600 mV.
VIH = Vref + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs.
VIL = Vref − 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
Fig 10. Voltage waveforms; pulse duration
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1.8 V DDR2-800 registered buffer with parity
CK
VICR
VID
CK
tsu
th
VIH
input
Vref
Vref
VIL
002aaa374
VID = 600 mV.
Vref = 0.5VDD.
VIH = Vref + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs.
VIL = Vref − 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
Fig 11. Voltage waveforms; set-up and hold times
CK
VICR
VICR
tPLH
tPHL
Vi(p-p)
CK
VOH
VT
output
VOL
002aaa375
tPLH and tPHL are the same as tPD.
Fig 12. Voltage waveforms; propagation delay times (clock to output)
LVCMOS
VIH
RESET
0.5VDD
VIL
tPHL
VOH
output
VT
VOL
002aaa376
tPLH and tPHL are the same as tPD.
VIH = Vref + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs.
VIL = Vref − 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
Fig 13. Voltage waveforms; propagation delay times (reset to output)
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1.8 V DDR2-800 registered buffer with parity
11.2 Output slew rate measurement
VDD = 1.8 V ± 0.1 V.
All input pulses are supplied by generators having the following characteristics:
PRR ≤ 10 MHz; Zo = 50 Ω; input slew rate = 1 V/ns ± 20 %, unless otherwise specified.
VDD
DUT
RL = 50 Ω
OUT
test point
CL = 10
pF(1)
002aaa377
(1) CL includes probe and jig capacitance.
Fig 14. Load circuit, HIGH-to-LOW slew measurement
output
VOH
80 %
dv_f
20 %
dt_f
002aaa378
VOL
Fig 15. Voltage waveforms, HIGH-to-LOW slew rate measurement
DUT
OUT
test point
CL = 10 pF(1)
RL = 50 Ω
002aaa379
(1) CL includes probe and jig capacitance.
Fig 16. Load circuit, LOW-to-HIGH slew measurement
dt_r
VOH
80 %
dv_r
20 %
output
002aaa380
VOL
Fig 17. Voltage waveforms, LOW-to-HIGH slew rate measurement
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1.8 V DDR2-800 registered buffer with parity
11.3 Error output load circuit and voltage measurement
VDD = 1.8 V ± 0.1 V.
All input pulses are supplied by generators having the following characteristics:
PRR ≤ 10 MHz; Zo = 50 Ω; input slew rate = 1 V/ns ± 20 %, unless otherwise specified.
VDD
DUT
RL = 1 kΩ
OUT
test point
CL = 10 pF(1)
002aaa500
(1) CL includes probe and jig capacitance.
Fig 18. Load circuit, error output measurements
LVCMOS
RESET
VDD
0.5VDD
0V
tPLH
VOH
output
waveform 2
0.15 V
0V
002aaa501
Fig 19. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to
RESET input
timing
inputs
VICR
Vi(p-p)
VICR
tHL
VDD
output
waveform 1
0.5VDD
002aaa502
VOL
Fig 20. Voltage waveforms, open-drain output HIGH-to-LOW transition time with respect
to clock inputs
SSTUM32865_1
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SSTUM32865
NXP Semiconductors
1.8 V DDR2-800 registered buffer with parity
timing
inputs
VICR
Vi(p-p)
VICR
tLH
VOH
output
waveform 2
0.15 V
002aaa503
0V
Fig 21. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to
clock inputs
SSTUM32865_1
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1.8 V DDR2-800 registered buffer with parity
12. Package outline
TFBGA160: plastic thin fine-pitch ball grid array package; 160 balls; body 9 x 13 x 0.7 mm
A
B
D
SOT802-2
ball A1
index area
E
A
A2
A1
detail X
e1
C
1/2 e
∅v
∅w
b
e
M
M
y1 C
C A B
C
y
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
ball A1
index area
e
e2
1/2 e
1
2
3
4
5
6
7
8
9
10
11
12
X
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max
A1
A2
b
D
E
e
e1
e2
v
w
y
y1
mm
1.15
0.35
0.25
0.80
0.65
0.45
0.35
9.1
8.9
13.1
12.9
0.65
7.15
11.05
0.15
0.08
0.1
0.1
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT802-2
---
---
---
EUROPEAN
PROJECTION
ISSUE DATE
05-06-21
05-07-13
Fig 22. Package outline SOT802-2 (TFBGA160)
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1.8 V DDR2-800 registered buffer with parity
13. Soldering
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus PbSn soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
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1.8 V DDR2-800 registered buffer with parity
13.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 23) than a PbSn process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 13 and 14
Table 13.
SnPb eutectic process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
≥ 350
< 2.5
235
220
≥ 2.5
220
220
Table 14.
Lead-free process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 23.
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1.8 V DDR2-800 registered buffer with parity
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 23. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
14. Abbreviations
Table 15.
Abbreviations
Acronym
Description
CMOS
Complementary Metal Oxide Semiconductor
DDR2
Double Data Rate 2
DIMM
Dual In-line Memory Module
DRAM
Dynamic Random Access Memory
LVCMOS
Low Voltage Complementary Metal Oxide Semiconductor
MT/s
Mega Transfers per second
RDIMM
Registered Dual In-line Memory Module
SSTL
Stub Series Terminated Logic
SSTL_18
Stub Series Terminated Logic for 1.8 V
15. Revision history
Table 16.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
SSTUM32865_1
20070919
Product data sheet
-
-
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1.8 V DDR2-800 registered buffer with parity
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a NXP Semiconductors product can reasonably be expected to
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: [email protected]
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1.8 V DDR2-800 registered buffer with parity
18. Contents
1
2
3
4
4.1
5
6
6.1
6.2
7
7.1
7.2
7.3
7.3.1
7.3.2
7.3.3
7.3.4
8
9
10
11
11.1
11.2
11.3
12
13
13.1
13.2
13.3
13.4
14
15
16
16.1
16.2
16.3
16.4
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
Functional description . . . . . . . . . . . . . . . . . . . 8
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional information . . . . . . . . . . . . . . . . . . . 9
Functional differences to SSTU32864 . . . . . . 10
Chip Select (CS) gating of key inputs (DCS0,
DCS1, DCS2, DCS3, CSGATEEN) . . . . . . . . 10
Parity error checking and reporting. . . . . . . . . 10
Reset (RESET) . . . . . . . . . . . . . . . . . . . . . . . . 10
Power-up sequence . . . . . . . . . . . . . . . . . . . . 10
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 15
Recommended operating conditions. . . . . . . 15
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 16
Test information . . . . . . . . . . . . . . . . . . . . . . . . 18
Test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Output slew rate measurement. . . . . . . . . . . . 20
Error output load circuit and voltage
measurement . . . . . . . . . . . . . . . . . . . . . . . . . 21
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 23
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Introduction to soldering . . . . . . . . . . . . . . . . . 24
Wave and reflow soldering . . . . . . . . . . . . . . . 24
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 24
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 25
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 26
Legal information. . . . . . . . . . . . . . . . . . . . . . . 27
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 27
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Contact information. . . . . . . . . . . . . . . . . . . . . 27
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 19 September 2007
Document identifier: SSTUM32865_1