PHILIPS SSTU32864

SSTU32864
1.8 V configurable registered buffer for DDR2 RDIMM
applications
Rev. 02 — 22 October 2004
Product data sheet
1. General description
The SSTU32864 is a 25-bit 1:1 or 14-bit 1:2 configurable registered buffer designed for
1.7 V to 1.9 V VDD operation.
All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The
control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized
to drive the DDR2 DIMM load.
The SSTU32864 operates from a differential clock (CK and CK). Data are registered at
the crossing of CK going HIGH, and CK going LOW.
The C0 input controls the pinout configuration of the 1:2 pinout from A configuration (when
LOW) to B configuration (when HIGH). The C1 input controls the pinout configuration from
25-bit 1:1 (when LOW) to 14-bit 1:2 (when HIGH).
The device supports low-power standby operation. When the reset input (RESET) is LOW,
the differential input receivers are disabled, and undriven (floating) data, clock and
reference voltage (VREF) inputs are allowed. In addition, when RESET is LOW all registers
are reset, and all outputs are forced LOW. The LVCMOS RESET and Cn inputs must
always be held at a valid logic HIGH or LOW level.
To ensure defined outputs from the register before a stable clock has been supplied,
RESET must be held in the LOW state during power-up.
In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with
respect to CK and CK. Therefore, no timing relationship can be guaranteed between the
two. When entering reset, the register will be cleared and the data outputs will be driven
LOW quickly, relative to the time to disable the differential input receivers. However, when
coming out of reset, the register will become active quickly, relative to the time to enable
the differential input receivers. As long as the data inputs are LOW, and the clock is stable
during the time from the LOW-to-HIGH transition of RESET until the input receivers are
fully enabled, the design of the SSTU32864 must ensure that the outputs will remain
LOW, thus ensuring no glitches on the output.
The device monitors both DCS and CSR inputs and will gate the Qn outputs from
changing states when both DCS and CSR inputs are HIGH. If either DCS or CSR input is
LOW, the Qn outputs will function normally. The RESET input has priority over the DCS
and CSR control and will force the outputs LOW. If the DCS-control functionality is not
desired, then the CSR input can be hardwired to ground, in which case the setup time
requirement for DCS would be the same as for the other Dn data inputs.
The SSTU32864 is available in a 96-ball, low profile fine-pitch ball grid array (LFBGA96)
package.
SSTU32864
Philips Semiconductors
1.8 V configurable registered buffer for DDR2 RDIMM applications
2. Features
■
■
■
■
■
■
■
■
■
■
■
■
Configurable register supporting DDR2 Registered DIMM applications
Configurable to 25-bit 1:1 mode or 14-bit 1:2 mode
Controlled output impedance drivers enable optimal signal integrity and speed
Exceeds JESD82-7 speed performance (1.8 ns max. single-bit switching propagation
delay; 2.0 ns max. mass-switching)
Supports up to 450 MHz clock frequency of operation
Optimized pinout for high-density DDR2 module design
Chip-selects minimize power consumption by gating data outputs from changing state
Supports SSTL_18 data inputs
Differential clock (CK and CK) inputs
Supports LVCMOS switching levels on the control and RESET inputs
Single 1.8 V supply operation
Available in 96-ball, 13.5 × 5.5 mm, 0.8 mm ball pitch LFBGA package
3. Ordering information
Table 1:
Ordering information
Tamb = 0 °C to +70 °C.
Type number
Solder process
Package
Name
Description
SSTU32864EC/G Pb-free (SnAgCu
solder ball compound)
LFBGA96
plastic low profile fine-pitch ball grid array package; SOT536-1
96 balls; body 13.5 × 5.5 × 1.05 mm
SSTU32864EC
LFBGA96
plastic low profile fine-pitch ball grid array package; SOT536-1
96 balls; body 13.5 × 5.5 × 1.05 mm
SnPb solder ball
compound
9397 750 14092
Product data sheet
Version
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 02 — 22 October 2004
2 of 21
SSTU32864
Philips Semiconductors
1.8 V configurable registered buffer for DDR2 RDIMM applications
4. Functional diagram
RESET
CK
CK
SSTU32864
VREF
DCKE
DODT
DCS
1D
C1
QCKEA
R
QCKEB (1)
1D
C1
R
QODTA
1D
C1
R
QCSA
1D
C1
R
Q1A
QODTB (1)
QCSB (1)
CSR
D1
0
1
Q1B (1)
002aaa954
to other channels
(1) Disabled in 1:1 configuration.
Fig 1. Functional diagram of SSTU32864; 1:2 mode (positive logic)
9397 750 14092
Product data sheet
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 02 — 22 October 2004
3 of 21
SSTU32864
Philips Semiconductors
1.8 V configurable registered buffer for DDR2 RDIMM applications
5. Pinning information
5.1 Pinning
SSTU32864EC/G
ball A1
SSTU32864EC
index area
1 2 3 4 5 6
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
002aab107
Transparent top view
Fig 2. Pin configuration for LFBGA96
1
2
3
4
5
6
A
DCKE
n.c.
VREF
VDD
QCKE
d.n.u.
B
D2
D15
GND
GND
Q2
Q15
C
D3
D16
VDD
VDD
Q3
Q16
D
DODT
n.c.
GND
GND
QODT
d.n.u.
E
D5
D17
VDD
VDD
Q5
Q17
F
D6
D18
GND
GND
Q6
Q18
G
n.c.
RESET
VDD
VDD
C1
C0
H
CK
DCS
GND
GND
QCS
d.n.u.
J
CK
CSR
VDD
VDD
ZOH
ZOL
K
D8
D19
GND
GND
Q8
Q19
L
D9
D20
VDD
VDD
Q9
Q20
M
D10
D21
GND
GND
Q10
Q21
N
D11
D22
VDD
VDD
Q11
Q22
P
D12
D23
GND
GND
Q12
Q23
R
D13
D24
VDD
VDD
Q13
Q24
T
D14
D25
VREF
VDD
Q14
Q25
002aaa955
Fig 3. Ball mapping; 1:1 register (C0 = 0, C1 = 0); top view
9397 750 14092
Product data sheet
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 02 — 22 October 2004
4 of 21
SSTU32864
Philips Semiconductors
1.8 V configurable registered buffer for DDR2 RDIMM applications
1
2
3
4
5
6
A
DCKE
n.c.
VREF
VDD
QCKEA
QCKEB
B
D2
d.n.u.
GND
GND
Q2A
Q2B
C
D3
d.n.u.
VDD
VDD
Q3A
Q3B
D
DODT
n.c.
GND
GND
QODTA
QODTB
E
D5
d.n.u.
VDD
VDD
Q5A
Q5B
F
D6
d.n.u.
GND
GND
Q6A
Q6B
G
n.c.
RESET
VDD
VDD
C1
C0
H
CK
DCS
GND
GND
QCSA
QCSB
J
CK
CSR
VDD
VDD
ZOH
ZOL
K
D8
d.n.u.
GND
GND
Q8A
Q8B
L
D9
d.n.u.
VDD
VDD
Q9A
Q9B
M
D10
d.n.u.
GND
GND
Q10A
Q10B
N
D11
d.n.u.
VDD
VDD
Q11A
Q11B
P
D12
d.n.u.
GND
GND
Q12A
Q12B
R
D13
d.n.u.
VDD
VDD
Q13A
Q13B
T
D14
d.n.u.
VREF
VDD
Q14A
Q14B
002aaa956
Fig 4. Ball mapping; 1:2 register A (C0 = 0, C1 = 1); top view
1
2
3
4
5
6
A
D1
n.c.
VREF
VDD
Q1A
Q1B
B
D2
d.n.u.
GND
GND
Q2A
Q2B
C
D3
d.n.u.
VDD
VDD
Q3A
Q3B
D
D4
n.c.
GND
GND
Q4A
Q4B
E
D5
d.n.u.
VDD
VDD
Q5A
Q5B
F
D6
d.n.u.
GND
GND
Q6A
Q6B
G
n.c.
RESET
VDD
VDD
C1
C0
H
CK
DCS
GND
GND
QCSA
QCSB
J
CK
CSR
VDD
VDD
ZOH
ZOL
K
D8
d.n.u.
GND
GND
Q8A
Q8B
L
D9
d.n.u.
VDD
VDD
Q9A
Q9B
M
D10
d.n.u.
GND
GND
Q10A
Q10B
N
DODT
d.n.u.
VDD
VDD
QODTA
QODTB
P
D12
d.n.u.
GND
GND
Q12A
Q12B
R
D13
d.n.u.
VDD
VDD
Q13A
Q13B
T
DCKE
d.n.u.
VREF
VDD
QCKEA
QCKEB
002aaa957
Fig 5. Ball mapping; 1:2 register B (C0 = 1, C1 = 1); top view
9397 750 14092
Product data sheet
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 02 — 22 October 2004
5 of 21
SSTU32864
Philips Semiconductors
1.8 V configurable registered buffer for DDR2 RDIMM applications
5.2 Pin description
Table 2:
Pin description
Symbol
Pin
Type
Description
GND
ground input
B3, B4, D3, D4,
F3, F4, H3, H4, K3,
K4, M3, M4, P3,
P4
ground
VDD
1.8 V nominal
A4, C3, C4, E3,
E4, G3, G4, J3, J4,
L3, L4, N3, N4, R3,
R4, T4
power supply voltage
VREF
A3, T3
0.9 V nominal
input reference voltage
ZOH
J5
input
reserved for future use
ZOL
J6
input
reserved for future use
CK
H1
differential input
positive master clock input
CK
J1
differential input
negative master clock input
C0, C1
G6, G5
LVCMOS inputs
configuration control inputs
RESET
G2
LVCMOS input
Asynchronous reset input. Resets registers and disables VREF
data and clock differential-input receivers.
CSR, DCS
J2, H2
SSTL_18 input
Chip select inputs. Disables data outputs switching when both
inputs are HIGH. [2]
D1 to D25
[1]
SSTL_18 input
Data inputs. Clocked in on the crossing of the rising edge of
CK and the falling edge of CK.
DODT
[1]
SSTL_18 input
The outputs of this register will not be suspended by DCS and
CSR control.
DCKE
[1]
SSTL_18 input
The outputs of this register will not be suspended by DCS and
CSR control.
Q1 to Q25,
Q1A to Q14A,
Q1B to Q14B
[1]
1.8 V CMOS
The outputs that are suspended by DCS and CSR control. [3]
QCS, QCSA,
QCSB
[1]
1.8 V CMOS
Data outputs that will not be suspended by DCS and CSR
control.
QODT, QODTA,
QODTB
[1]
1.8 V CMOS
Data outputs that will not be suspended by DCS and CSR
control.
QCKE, QCKEA,
QCKEB
[1]
1.8 V CMOS
Data outputs that will not be suspended by DCS and CSR
control.
n.c.
A2, D2, G1
-
Not connected. Ball present but no internal connection to the
die.
d.n.u.
[1]
-
Do-not-use. Ball internally connected to the die which should
be left open-circuit.
[1]
Depends on configuration. Refer to Figure 3, Figure 4, and Figure 5 for ball number.
[2]
Configurations:
Data inputs = D2, D3, D5, D6, D8 to D25 when C0 = 0 and C1 = 0.
Data inputs = D2, D3, D5, D6, D8 to D14 when C0 = 0 and C1 = 1.
Data inputs = D1 to D6, D8 to D10, D12, D13 when C0 = 1 and C1 = 1.
[3]
Configurations:
Data outputs = Q2, Q3, Q5, Q6, Q8 to Q25 when C0 = 0 and C1 = 0.
Data outputs = Q2, Q3, Q5, Q6, Q8 to Q14 when C0 = 0 and C1 = 1.
9397 750 14092
Product data sheet
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 02 — 22 October 2004
6 of 21
SSTU32864
Philips Semiconductors
1.8 V configurable registered buffer for DDR2 RDIMM applications
Data outputs = Q1 to Q6, Q8 to Q10, Q12, Q13 when C0 = 1 and C1 = 1.
6. Functional description
6.1 Function table
Table 3:
Function table (each flip-flop)
Outputs [1]
Inputs
RESET
DCS
CSR
CK
CK
Dn,
DODT,
DCKE
Qn
QCS
QODT,
QCKE
H
L
L
↑
↓
L
L
L
L
H
L
L
↑
↓
H
H
L
H
H
L
L
L or H
L or H
X
Q0
Q0
Q0
[1]
H
L
H
↑
↓
L
L
L
L
H
L
H
↑
↓
H
H
L
H
H
L
H
L or H
L or H
X
Q0
Q0
Q0
H
H
L
↑
↓
L
L
H
L
H
H
L
↑
↓
H
H
H
H
H
H
L
L or H
L or H
X
Q0
Q0
Q0
H
H
H
↑
↓
L
Q0
H
L
H
H
H
↑
↓
H
Q0
H
H
H
H
H
L or H
L or H
X
Q0
Q0
Q0
L
X or
floating
X or
floating
X or
floating
X or
floating
X or
floating
L
L
L
Q0 is the previous state of the associated output.
H — HIGH voltage level
L — LOW voltage level
↓ — HIGH-to-LOW transition
↑ — LOW-to-HIGH transition
X — Don’t care
9397 750 14092
Product data sheet
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 02 — 22 October 2004
7 of 21
SSTU32864
Philips Semiconductors
1.8 V configurable registered buffer for DDR2 RDIMM applications
7. Limiting values
Table 4:
Limiting values [1]
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDD
Conditions
Min
Max
Unit
supply voltage
−0.5
+2.5
V
+2.5 [3]
V
VI
receiver input voltage
−0.5 [2]
VO
driver output voltage
−0.5 [2]
VDD + 0.5 [3]
V
IIK
input clamp current
VI < 0 V or VI > VDD
-
±50
mA
IOK
output clamp current
VO < 0 V or VO > VDD
-
±50
mA
IO
continuous output current
0 V < VO < VDD
-
±50
mA
ICCC
continuous current through each
VDD or GND pin
-
±100
mA
Tstg
storage temperature
−65
+150
°C
[1]
Stresses beyond those listed under ‘absolute maximum ratings’ may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under ‘recommended operating
conditions’ is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
[2]
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
[3]
This value is limited to 2.5 V maximum.
9397 750 14092
Product data sheet
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 02 — 22 October 2004
8 of 21
SSTU32864
Philips Semiconductors
1.8 V configurable registered buffer for DDR2 RDIMM applications
8. Recommended operating conditions
Table 5:
Operating conditions
Symbol
Parameter
VDD
Min
Typ
Max
Unit
supply voltage
1.7
-
1.9
V
VREF
reference voltage
0.49 × VDD
0.50 × VDD
0.51 × VDD
V
VTT
termination voltage
VREF − 40 mV
VREF
VREF + 40 mV
V
VI
input voltage
0
-
VDD
V
VIH(AC)
AC HIGH-level input voltage
data inputs (Dn),
CSR
VREF + 250 mV
-
-
V
VIL(AC)
AC LOW-level input voltage
data inputs (Dn),
CSR
-
-
VREF − 250 mV V
VIH(DC)
DC HIGH-level input voltage data inputs (Dn),
CSR
VREF + 125 mV
-
-
VIL(DC)
DC LOW-level input voltage
data inputs (Dn),
CSR
-
-
VREF − 125 mV V
VIH
HIGH-level input voltage
RESET, Cn
[1]
0.65 × VDD
-
VDD
V
RESET, Cn
[1]
-
-
0.35 × VDD
V
0.675
-
1.125
V
600
-
-
mV
LOW-level input voltage
VIL
Conditions
V
VICR
common mode input voltage CK, CK
range
[2]
VID
differential input voltage
[2]
IOH
HIGH-level output current
-
-
−8
mA
IOL
LOW-level output current
-
-
8
mA
Tamb
operating ambient
temperature in free air
0
-
+70
°C
CK, CK
[1]
The RESET and Cn inputs of the device must be held at valid logic levels (not floating) to ensure proper device operation.
[2]
The differential inputs must not be floating, unless RESET is LOW.
9397 750 14092
Product data sheet
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 02 — 22 October 2004
9 of 21
SSTU32864
Philips Semiconductors
1.8 V configurable registered buffer for DDR2 RDIMM applications
9. Characteristics
Table 6:
Characteristics
Recommended operating conditions, unless otherwise specified. Voltages are referenced to GND (ground = 0 V).
Tamb = 0 °C to +70 °C.
Symbol
Parameter
VOH
HIGH-level output voltage
IOH = −6 mA; VDD = 1.7 V
1.2
-
-
V
VOL
LOW-level output voltage
IOL = 6 mA; VDD = 1.7 V
-
-
0.5
V
II
input current
all inputs; VI = VDD or GND;
VDD = 1.9 V
−5
-
+5
µA
IDD
static standby current
RESET = GND; IO = 0 mA;
VDD = 1.9 V
-
-
100
µA
static operating current
RESET = VDD; IO = 0 mA;
VDD = 1.9 V;
VI = VIH(AC) or VIL(AC)
-
-
40
mA
dynamic operating current per
MHz, clock only
RESET = VDD;
VI = VIH(AC) or VIL(AC); CK and
CK switching at 50 % duty cycle.
IO = 0 mA; VDD = 1.9 V
-
16
-
µA
dynamic operating current per
MHz, per each data input,
1:1 mode
RESET = VDD;
VI = VIH(AC) or VIL(AC); CK and
CK switching at 50 % duty cycle.
One data input switching at half
clock frequency, 50 % duty
cycle. IO = 0 mA; VDD = 1.9 V
-
11
-
µA
dynamic operating current per
MHz, per each data input,
1:2 mode
RESET = VDD;
VI = VIH(AC) or VIL(AC); CK and
CK switching at 50 % duty cycle.
One data input switching at half
clock frequency, 50 % duty
cycle. IO = 0 mA; VDD = 1.9 V
-
19
-
µA
input capacitance, data inputs,
CSR
VI = VREF ± 250 mV;
VDD = 1.8 V
2.5
-
3.5
pF
input capacitance, CK and CK
VICR = 0.9 V; VID = 600 mV;
VDD = 1.8 V
2
-
3
pF
input capacitance, RESET
VI = VDD or GND; VDD = 1.8 V
2
-
4
pF
IDDD
Ci
Conditions
9397 750 14092
Product data sheet
Min
Typ
Max
Unit
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 02 — 22 October 2004
10 of 21
SSTU32864
Philips Semiconductors
1.8 V configurable registered buffer for DDR2 RDIMM applications
Table 7:
Timing requirements
Recommended operating conditions; VDD = 1.8 V ± 0.1 V; Tamb = 0 °C to +70 °C; unless otherwise specified.
See Figure 6 through Figure 11.
Symbol
Parameter
Min
Typ
Max
Unit
fclock
clock frequency
Conditions
-
-
450
MHz
tW
pulse duration, CK, CK HIGH or
LOW
1
-
-
ns
tACT
differential inputs active time
[1] [2]
-
-
10
ns
tINACT
differential inputs inactive time
[1] [3]
-
-
15
ns
tsu
set-up time
DCS before CK ↑, CK ↓,
CSR HIGH
0.7
-
-
ns
DCS before CK ↑, CK ↓,
CSR LOW
0.5
-
-
ns
CSR, ODT, CKE, and data
before CK ↑, CK ↓
0.5
-
-
ns
DCS, CSR, ODT, CKE,
and data after CK ↑, CK ↓
0.5
-
-
ns
hold time
th
[1]
This parameter is not necessarily production tested.
[2]
Data inputs must be active below a minimum time of tACT(max) after RESET is taken HIGH.
[3]
Data and clock inputs must be held at valid levels (not floating) a minimum time of tINACT(max) after RESET is taken LOW.
Table 8:
Switching characteristics
Recommended operating conditions; VDD = 1.8 V ± 0.1 V; Tamb = 0 °C to +70 °C;
Class I, VREF = VTT = VDD × 0.5 and CL = 10 pF; unless otherwise specified. See Figure 6 through Figure 11.
Symbol
Parameter
fMAX
maximum input clock frequency
tPDM
propagation delay
Conditions
CK and CK to output
[1]
[1] [2]
tPDMSS
propagation delay, simultaneous
switching
CK and CK to output
tPHL
propagation delay
RESET to output
[1]
Includes 350 ps of test-load transmission line delay.
[2]
This parameter is not necessarily production tested.
Min
Typ
Max
Unit
450
-
-
MHz
1.41
-
1.8
ns
-
-
2.0
ns
-
-
3
ns
Min
Typ
Max
Unit
Table 9:
Output edge rates
Recommended operating conditions, unless otherwise specified. VDD = 1.8 V ± 0.1 V
Symbol
Parameter
Conditions
dV/dt_r
rising edge slew rate
1
-
4
V/ns
dV/dt_f
falling edge slew rate
1
-
4
V/ns
dV/dt_∆
absolute difference between dV/dt_r
and dV/dt_f
-
-
1
V/ns
9397 750 14092
Product data sheet
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 02 — 22 October 2004
11 of 21
SSTU32864
Philips Semiconductors
1.8 V configurable registered buffer for DDR2 RDIMM applications
10. Test information
10.1 Test circuit
All input pulses are supplied by generators having the following characteristics:
PRR ≤ 10 MHz; Z0 = 50 Ω; input slew rate = 1 V/ns ± 20 %, unless otherwise specified.
The outputs are measured one at a time with one transition per measurement.
VDD
DUT
TL = 50 Ω
RL = 1000 Ω
TL = 350 ps, 50 Ω
CK
CK
CK inputs
OUT
CL = 30 pF(1)
RL = 1000 Ω
test point
RL = 100 Ω
002aaa371
test point
(1) CL includes probe and jig capacitance.
Fig 6. Load circuit
LVCMOS
VDD
RESET
VDD/2
VDD/2
0V
tINACT
tACT
90 %
IDD(1)
10 %
002aaa372
(1) IDD tested with clock and data inputs held at VDD or GND, and IO = 0 mA.
Fig 7. Voltage and current waveforms; inputs active and inactive times
tW
VIH
input
VICR
VICR
VID
VIL
002aaa373
VID = 600 mV
VIH = VREF + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs.
VIL = VREF − 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
Fig 8. Voltage waveforms; pulse duration
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1.8 V configurable registered buffer for DDR2 RDIMM applications
CK
VICR
VID
CK
tsu
th
VIH
input
VREF
VREF
VIL
002aaa374
VID = 600 mV
VREF = VDD/2
VIH = VREF + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs.
VIL = VREF − 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
Fig 9. Voltage waveforms; set-up and hold times
CK
VICR
VICR
tPLH
tPHL
Vi(p-p)
CK
VOH
VTT
output
002aaa375
VOL
tPLH and tPHL are the same as tPD.
Fig 10. Voltage waveforms; propagation delay times (clock to output)
LVCMOS
VIH
RESET
VDD/2
VIL
tPHL
VOH
output
VTT
002aaa376
VOL
tPLH and tPHL are the same as tPD.
VIH = VREF + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs.
VIL = VREF − 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
Fig 11. Voltage waveforms; propagation delay times (reset to output)
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Philips Semiconductors
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10.2 Output slew rate measurement
VDD = 1.8 V ± 0.1 V.
All input pulses are supplied by generators having the following characteristics:
PRR ≤ 10 MHz; Z0 = 50 Ω; input slew rate = 1 V/ns ± 20 %, unless otherwise specified.
VDD
DUT
RL = 50 Ω
OUT
test point
CL = 10
pF(1)
002aaa377
(1) CL includes probe and jig capacitance.
Fig 12. Load circuit, HIGH-to-LOW slew measurement
output
VOH
80 %
dv_f
20 %
dt_f
002aaa378
VOL
Fig 13. Voltage waveforms, HIGH-to-LOW slew rate measurement
DUT
OUT
test point
CL = 10 pF(1)
RL = 50 Ω
002aaa379
(1) CL includes probe and jig capacitance.
Fig 14. Load circuit, LOW-to-HIGH slew measurement
dt_r
VOH
80 %
dv_r
20 %
output
002aaa380
VOL
Fig 15. Voltage waveforms, LOW-to-HIGH slew rate measurement
9397 750 14092
Product data sheet
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Rev. 02 — 22 October 2004
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Philips Semiconductors
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11. Package outline
LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm SOT536-1
A
B
D
ball A1
index area
A
A2
E
A1
detail X
e1
C
1/2 e
∅v M C A B
e
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
ball A1
index area
y1 C
y
∅w M C
b
e
e2
1/2 e
1 2 3 4 5 6
X
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
b
D
E
e
e1
e2
v
w
y
y1
mm
1.5
0.41
0.31
1.2
0.9
0.51
0.41
5.6
5.4
13.6
13.4
0.8
4
12
0.15
0.1
0.1
0.2
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
00-03-04
03-02-05
SOT536-1
Fig 16. Package outline SOT536-1 (LFBGA96)
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Product data sheet
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Rev. 02 — 22 October 2004
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12. Soldering
12.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account of
soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages
(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface mount IC packages. Wave
soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is recommended.
12.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and
binding agent) to be applied to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement. Driven by legislation and
environmental forces the worldwide use of lead-free solder pastes is increasing.
Several methods exist for reflowing; for example, convection or convection/infrared
heating in a conveyor type oven. Throughput times (preheating, soldering and cooling)
vary between 100 seconds and 200 seconds depending on heating method.
Typical reflow peak temperatures range from 215 °C to 270 °C depending on solder paste
material. The top-surface temperature of the packages should preferably be kept:
• below 225 °C (SnPb process) or below 245 °C (Pb-free process)
– for all BGA, HTSSON..T and SSOP..T packages
– for packages with a thickness ≥ 2.5 mm
– for packages with a thickness < 2.5 mm and a volume ≥ 350 mm3 so called
thick/large packages.
• below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with a
thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages.
Moisture sensitivity precautions, as indicated on packing, must be respected at all times.
12.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices
(SMDs) or printed-circuit boards with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering method was specifically
developed.
If wave soldering is used the following conditions must be observed for optimal results:
• Use a double-wave soldering method comprising a turbulent wave with high upward
pressure followed by a smooth laminar wave.
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be
parallel to the transport direction of the printed-circuit board;
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– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the
transport direction of the printed-circuit board.
The footprint must incorporate solder thieves at the downstream end.
• For packages with leads on four sides, the footprint must be placed at a 45° angle to
the transport direction of the printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement and before soldering, the package must be fixed with a droplet of
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the adhesive is cured.
Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C
or 265 °C, depending on solder material applied, SnPb or Pb-free respectively.
A mildly-activated flux will eliminate the need for removal of corrosive residues in most
applications.
12.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage
(24 V or less) soldering iron applied to the flat part of the lead. Contact time must be
limited to 10 seconds at up to 300 °C.
When using a dedicated tool, all other leads can be soldered in one operation within
2 seconds to 5 seconds between 270 °C and 320 °C.
12.5 Package related soldering information
Table 10:
Suitability of surface mount IC packages for wave and reflow soldering methods
Package [1]
Soldering method
Wave
Reflow [2]
BGA, HTSSON..T [3], LBGA, LFBGA, SQFP,
SSOP..T [3], TFBGA, VFBGA, XSON
not suitable
suitable
DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP,
HSQFP, HSSON, HTQFP, HTSSOP, HVQFN,
HVSON, SMS
not suitable [4]
suitable
PLCC [5], SO, SOJ
suitable
suitable
not
recommended [5] [6]
suitable
SSOP, TSSOP, VSO, VSSOP
not
recommended [7]
suitable
CWQCCN..L [8], PMFP [9], WQCCN..L [8]
not suitable
LQFP, QFP, TQFP
[1]
For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026);
order a copy from your Philips Semiconductors sales office.
[2]
All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the
maximum temperature (with respect to time) and body size of the package, there is a risk that internal or
external package cracks may occur due to vaporization of the moisture in them (the so called popcorn
effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit
Packages; Section: Packing Methods.
[3]
These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no
account be processed through more than one soldering cycle or subjected to infrared reflow soldering with
peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package
body peak temperature must be kept as low as possible.
9397 750 14092
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not suitable
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17 of 21
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1.8 V configurable registered buffer for DDR2 RDIMM applications
[4]
These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the
solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink
on the top side, the solder might be deposited on the heatsink surface.
[5]
If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave
direction. The package footprint must incorporate solder thieves downstream and at the side corners.
[6]
Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
[7]
Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger
than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
[8]
Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered
pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by
using a hot bar soldering process. The appropriate soldering profile can be provided on request.
[9]
Hot bar soldering or manual soldering is suitable for PMFP packages.
13. Abbreviations
Table 11:
Abbreviations
Acronym
Description
CMOS
Complementary Metal Oxide Silicon
DDR
Double Data Rate
DIMM
Dual In-line Memory Module
JEDEC
Joint Electron Device Engineering Council
LFBGA
Low profile Fine-pitch Ball Grid Array
LVCMOS
Low Voltage Complementary Metal Oxide Silicon
PRR
Pulse Repetition Rate
RDIMM
Registered Dual In-line Memory Module
SSTL
Stub Series Terminated Logic
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14. Revision history
Table 12:
Revision history
Document ID
Release date
Data sheet status
Change notice
Doc. number
Supersedes
SSTU32864_2
20041022
Product data sheet
-
9397 750 14092
SSTU32864-01
Modifications:
•
The format of this data sheet has been redesigned to comply with the new presentation and
information standard of Philips Semiconductors.
•
•
Data sheet status changed to ‘Product data sheet’.
Table 2 “Pin description”
– (new) Table note [1] added
– pin (ball) numbers added
– changed pin name ‘DNU’ to ‘d.n.u.’
•
Table 3 “Function table (each flip-flop)”
– moved to Section 6.1 on page 7
– added Table note 1 and its reference at ‘Outputs’
– corrected column sub-headings under ‘Outputs’
•
•
Table 4 “Limiting values [1]”: Symbol Vi changed to VI; Symbol Vo changed to VO
Table 5 “Operating conditions”:
– changed VIH (for data inputs) to VIH(AC) and VIH(DC); condition changed to ‘data inputs (Dn)’
– changed VIL (for data inputs) to VIL(AC) and VIL(DC); condition changed to ‘data inputs (Dn)’
– Table note split into 2 notes; references added.
•
Table 6 “Characteristics”
– changed IDDD Parameter from “dynamic operating current ...” to “dynamic operating current
per MHz ...”; change Unit from “µA/MHz” to “µA”.
•
Table 7 “Timing requirements”:
– changed symbol fCLOCK to fclock
– changed symbol tSU to tsu
– changed symbol tH to th
•
Table 8 “Switching characteristics”:
– changed tPDM and tPDMSS Conditions from ‘clock to output’ to ‘CK and CK to output’
– changed tPHL Condition from ‘reset to output’ to ‘RESET to output’
•
•
•
SSTU32864-01
Table 9 “Output edge rates”: deleted Table note [1]
Section 10.1 “Test circuit”: titles for Figure 10 and Figure 11 modified.
Added Section 13 “Abbreviations”
20040712
Objective data
-
9397 750 14092
Product data sheet
9397 750 13339
-
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 02 — 22 October 2004
19 of 21
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Philips Semiconductors
1.8 V configurable registered buffer for DDR2 RDIMM applications
15. Data sheet status
Level
Data sheet status [1]
Product status [2] [3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
Please consult the most recently issued data sheet before initiating or completing a design.
[2]
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
16. Definitions
17. Disclaimers
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
18. Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: [email protected]
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Product data sheet
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20 of 21
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Philips Semiconductors
1.8 V configurable registered buffer for DDR2 RDIMM applications
19. Contents
1
2
3
4
5
5.1
5.2
6
6.1
7
8
9
10
10.1
10.2
11
12
12.1
12.2
12.3
12.4
12.5
13
14
15
16
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
Functional description . . . . . . . . . . . . . . . . . . . 7
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8
Recommended operating conditions. . . . . . . . 9
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 10
Test information . . . . . . . . . . . . . . . . . . . . . . . . 12
Test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Output slew rate measurement. . . . . . . . . . . . 14
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Introduction to soldering surface mount
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 16
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 16
Manual soldering . . . . . . . . . . . . . . . . . . . . . . 17
Package related soldering information . . . . . . 17
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 19
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 20
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Contact information . . . . . . . . . . . . . . . . . . . . 20
© Koninklijke Philips Electronics N.V. 2004
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.
Date of release: 22 October 2004
Document number: 9397 750 14092
Published in The Netherlands