INTEGRATED CIRCUITS DATA SHEET PCF8533 Universal LCD driver for low multiplex rates Product specification Supersedes data of 1999 Mar 12 File under Integrated Circuits, IC12 1999 Jul 30 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates CONTENTS 1 FEATURES 2 GENERAL DESCRIPTION 3 ORDERING INFORMATION 4 BLOCK DIAGRAM 5 PINNING 6 FUNCTIONAL DESCRIPTION 6.1 6.2 6.3 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.5 6.5.1 6.5.2 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 Power-on reset LCD bias generator LCD voltage selector LCD drive mode waveforms Static drive mode 1 : 2 multiplex drive mode 1 : 3 multiplex drive mode 1 : 4 multiplex drive mode Oscillator Internal clock External clock Timing Display register Segment outputs Backplane outputs Display RAM Data pointer Subaddress counter Output bank selector Input bank selector Blinker 1999 Jul 30 2 PCF8533 7 CHARACTERISTICS OF THE I2C-BUS 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 Bit transfer START and STOP conditions System configuration Acknowledge PCF8533 I2C-bus controller Input filters I2C-bus protocol Command decoder Display controller Cascaded operation 8 LIMITING VALUES 9 HANDLING 10 DC CHARACTERISTICS 11 AC CHARACTERISTICS 12 BONDING PAD LOCATIONS 13 DEVICE PROTECTION 14 TRAY INFORMATION 15 DEFINITIONS 16 LIFE SUPPORT APPLICATIONS 17 PURCHASE OF PHILIPS I2C COMPONENTS 18 BARE DIE DISCLAIMER Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 1 PCF8533 FEATURES • Single-chip LCD controller/driver • Selectable backplane drive configuration: static or 2/3/4 backplane multiplexing • Selectable display bias configuration: static, 1⁄2 or 1⁄3 • Internal LCD bias generation with voltage-follower buffers 2 GENERAL DESCRIPTION The PCF8533 is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD) with low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to four backplanes and up to 80 segments and can easily be cascaded for larger LCD applications. The PCF8533 is compatible with most microprocessors/microcontrollers and communicates via a two-line bidirectional I2C-bus. Communication overheads are minimized by a display RAM with auto-incremented addressing, by hardware subaddressing and by display memory switching (static and duplex drive modes). • 80 segment drives: up to forty 8-segment numeric characters; up to twentyone 15-segment alphanumeric characters; or any graphics of up to 320 elements • 80 × 4-bit RAM for display data storage • Auto-incremented display data loading across device subaddress boundaries • Display memory bank switching in static and duplex drive modes • Versatile blinking modes • LCD and logic supplies may be separated • Wide power supply range: from 1.8 to 5.5 V • Wide LCD supply range: from 2.5 V for low threshold LCDs and up to 6.5 V for guest-host LCDs and high threshold (automobile) twisted nematic LCDs • Low power consumption • 400 kHz I2C-bus interface • TTL/CMOS compatible • Compatible with 4-bit, 8-bit or 16-bit microprocessors/microcontrollers • May be cascaded for large LCD applications (up to 5120 segments possible) • No external components • Compatible with Chip-On-Glass (COG) technology • Manufactured in silicon gate CMOS process. 3 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME PCF8533U 1999 Jul 30 − DESCRIPTION VERSION − chip with bumps in tray 3 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... BACKPLANE OUTPUTS LCD VOLTAGE SELECTOR VSS DISPLAY SEGMENT OUTPUTS DISPLAY REGISTER OUTPUT BANK SELECT AND BLINK CONTROL DISPLAY CONTROL LCD BIAS GENERATOR 4 PCF8533 CLK SYNC CLOCK SELECT AND TIMING BLINKER TIMEBASE OSC OSCILLATOR POWER-ON RESET SCL INPUT FILTERS SDA COMMAND DECODE DISPLAY RAM WRITE DATA CONTROL I2C-BUS CONTROLLER Universal LCD driver for low multiplex rates BLOCK DIAGRAM 80 VLCD Philips Semiconductors 4 1999 Jul 30 S0 to S79 BP0 BP1 BP2 BP3 handbook, full pagewidth DATA POINTER AND AUTO INCREMENT SUBADDRESS COUNTER MGL743 SA0 SDAACK VDD A1 A2 Product specification PCF8533 Fig.1 Block diagram. A0 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 5 PCF8533 PINNING SYMBOL PAD SDAACK DESCRIPTION I2C-bus 1 acknowledge output; note 1 SDA 2 and 3 I2C-bus serial data input; note 1 SCL 4 and 5 I2C-bus serial clock input CLK 6 external clock input/output VDD 7 supply voltage SYNC 8 cascade synchronization input/output 9 internal oscillator enable input OSC A0, A1 and A2 10, 11 and 12 subaddress inputs SA0 13 I2C-bus slave address input; bit 0 VSS 14 logic ground VLCD 15 LCD supply voltage BP0, BP1, BP2 and BP3 17, 99, 16 and 98 S0 to S79 LCD backplane outputs 18 to 97 LCD segment outputs Note 1. For most applications SDA and SDAACK will be shorted together; see Chapter 7. 6 FUNCTIONAL DESCRIPTION The PCF8533 is a versatile peripheral device designed to interface any microprocessor/microcontroller to a wide variety of LCDs. It can directly drive any static or multiplexed LCD containing up to four backplanes and up to 80 segments. The display configurations possible with the PCF8533 depend on the number of active backplane outputs required; a selection of display configurations is given in Table 1. All of the display configurations given in Table 1 can be implemented in the typical system shown in Fig.2. The host microprocessor/microcontroller maintains the 2-line I2C-bus communication channel with the PCF8533. The internal oscillator is selected by connecting pad OSC to VSS. The appropriate biasing voltages for the multiplexed LCD waveforms are generated internally. The only other connections required to complete the system are to the power supplies (VDD, VSS and VLCD) and the LCD panel selected for the application. Table 1 Selection of display configurations NUMBER OF 7-SEGMENTS NUMERIC 14-SEGMENTS ALPHANUMERIC DOT MATRIX BACKPLANES SEGMENTS DIGITS INDICATOR SYMBOLS CHARACTERS INDICATOR SYMBOLS 4 320 40 40 20 40 320 dots (4 × 80) 3 240 30 30 16 16 240 dots (3 × 80) 2 160 20 20 10 20 160 dots (2 × 80) 1 80 10 10 5 10 80 dots (1 × 80) 1999 Jul 30 5 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8533 V handbook, full pagewidth DD R tr 2CB HOST MICROPROCESSOR/ MICROCONTROLLER SDAACK VDD VLCD SDA 80 segment drives SCL PCF8533 OSC 4 backplanes A0 A1 A2 SA0 VSS VSS Fig.2 Typical system configuration. 1999 Jul 30 6 LCD PANEL (up to 320 elements) MGL744 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 6.1 PCF8533 The biasing configurations that apply to the preferred modes of operation, together with the biasing characteristics as functions of VOP and the resulting discrimination ratios (D), are given in Table 2. Power-on reset At Power-on the PCF8533 resets to a starting condition as follows: 1. All backplane outputs are set to VLCD. 4. Blinking is switched off. A practical value for VOP is determined by equating Voff(rms) with a defined LCD threshold voltage (Vth), typically when the LCD exhibits approximately 10% contrast. In the static drive mode a suitable choice is VOP > 3Vth. 5. Input and output bank selectors are reset (as defined in Table 5). Multiplex drive ratios of 1 : 3 and 1 : 4 with 1⁄2bias are possible but the discrimination and hence the contrast 6. The I2C-bus interface is initialized. ratios are smaller ( 3 = 1.732 for 1 : 3 multiplex or 2. All segment outputs are set to VLCD. 3. The drive mode ‘1 : 4 multiplex with 1⁄3bias’ is selected. 7. The data pointer and the subaddress counter are cleared. 21 ---------- = 1.528 for 1 : 4 multiplex). 3 8. Display disabled. The advantage of these modes is a reduction of the LCD full-scale voltage VOP as follows: Data transfers on the I2C-bus should be avoided for 1 ms following Power-on to allow completion of the reset action. 6.2 • 1 : 3 multiplex (1⁄2bias): LCD bias generator V OP = Fractional LCD biasing voltages are obtained from an internal voltage divider of the three series resistors connected between VLCD and VSS. The centre resistor can be switched out of the circuit to provide a 1⁄2bias voltage level for the 1 : 2 multiplex configuration. 6.3 6 × V off(rms) = 2.449V off(rms) • 1 : 4 multiplex (1⁄2bias): (4 × 3) V OP = ---------------------- = 2.309V off(rms) 3 These compare with VOP = 3Voff(rms) when 1⁄3bias is used. Note: VOP = VLCD. LCD voltage selector The LCD voltage selector co-ordinates the multiplexing of the LCD in accordance with the selected LCD drive configuration. The operation of the voltage selector is controlled by MODE SET commands from the command decoder. Table 2 Preferred LCD drive modes: summary of characteristics NUMBER OF LCD DRIVE MODE BACKPLANES LEVELS static 1:2 1:2 1 2 2 LCD BIAS CONFIGURATION V on(rms) ------------------V OP V on(rms) D = -----------------V off(rms) 2 static 0 1 ∞ 3 1⁄ 2 0.354 0.791 2.236 4 1⁄ 3 0.333 0.745 2.236 3 0.333 0.638 1.915 3 0.333 0.577 1.732 1:3 3 4 1⁄ 1:4 4 4 1⁄ 1999 Jul 30 V off(rms) ------------------V OP 7 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 6.4 PCF8533 LCD drive mode waveforms 6.4.1 STATIC DRIVE MODE The static LCD drive mode is used when a single backplane is provided in the LCD. Backplane and segment drive waveforms for this mode are shown in Fig.3. Tframe handbook, full pagewidth LCD segments VLCD BP0 VSS state 1 (on) VLCD state 2 (off) Sn VSS VLCD Sn + 1 VSS (a) Waveforms at driver. VLCD state 1 0V −VLCD VLCD state 2 0V −VLCD (b) Resultant waveforms at LCD segment. MGL745 Vstate1(t) = Vsn(t) − VBP0(t). Von(rms) = VLCD. Vstate2(t) = Vsn + 1(t) − VBP0(t). Voff(rms) = 0 V. Fig.3 Static drive mode waveforms. 1999 Jul 30 8 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 6.4.2 PCF8533 1 : 2 MULTIPLEX DRIVE MODE When two backplanes are provided in the LCD, the 1 : 2 multiplex mode applies. The PCF8533 allows the use of 1⁄2bias or 1⁄3bias in this mode as shown in Figs 4 and 5. Tframe handbook, full pagewidth VLCD BP0 LCD segments VLCD/2 VSS state 1 VLCD BP1 state 2 VLCD/2 VSS VLCD Sn VSS VLCD Sn + 1 VSS (a) Waveforms at driver. VLCD VLCD/2 state 1 0V −VLCD/2 −VLCD VLCD VLCD/2 state 2 0V −VLCD/2 −VLCD (b) Resultant waveforms at LCD segment. MGL746 Vstate1(t) = Vsn(t) − VBP0(t). Von(rms) = 0.791VLCD. Vstate2(t) = Vsn(t) − VBP1(t). Voff(rms) = 0.354VLCD. Fig.4 Waveforms for the 1 : 2 multiplex drive mode with 1⁄2bias. 1999 Jul 30 9 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8533 Tframe handbook, full pagewidth BP0 BP1 Sn Sn + 1 VLCD 2VLCD/3 LCD segments VLCD/3 VSS state 1 VLCD 2VLCD/3 state 2 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS (a) Waveforms at driver. VLCD 2VLCD/3 VLCD/3 state 1 0V −VLCD/3 −2VLCD/3 −VLCD VLCD 2VLCD/3 state 2 VLCD/3 0V −VLCD/3 −2VLCD/3 −VLCD (b) Resultant waveforms at LCD segment. MGL747 Vstate1(t) = Vsn(t) − VBP0(t). Von(rms) = 0.745VLCD. Vstate2(t) = Vsn(t) − VBP1(t). Voff(rms) = 0.333VLCD. Fig.5 Waveforms for the 1 : 2 multiplex drive mode with 1⁄3bias. 6.4.3 1 : 3 MULTIPLEX DRIVE MODE When three backplanes are provided in the LCD, the 1 : 3 multiplex drive mode applies, as shown in Fig.6. 1999 Jul 30 10 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8533 Tframe handbook, full pagewidth BP0 BP1 BP2 Sn Sn + 1 Sn + 2 VLCD 2VLCD/3 LCD segments VLCD/3 VSS state 1 VLCD 2VLCD/3 state 2 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS (a) Waveforms at driver. VLCD state 1 2VLCD/3 VLCD/3 0V −VLCD/3 −2VLCD/3 −VLCD VLCD 2VLCD/3 VLCD/3 state 2 0V −VLCD/3 −2VLCD/3 −VLCD (b) Resultant waveforms at LCD segment. MGL748 Vstate1(t) = Vsn(t) − VBP0(t). Von(rms) = 0.638VLCD. Vstate2(t) = Vsn(t) − VBP1(t). Voff(rms) = 0.333VLCD. Fig.6 Waveforms for the 1 : 3 multiplex drive mode. 6.4.4 1 : 4 MULTIPLEX DRIVE MODE When four backplanes are provided in the LCD, the 1 : 4 multiplex drive mode applies, as shown in Fig.7. 1999 Jul 30 11 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates Tframe handbook, full pagewidth BP0 BP1 PCF8533 VLCD 2VLCD/3 LCD segments VLCD/3 VSS state 1 VLCD 2VLCD/3 state 2 VLCD/3 VSS VLCD BP2 BP3 Sn Sn + 1 Sn + 2 Sn + 3 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS (a) Waveforms at driver. VLCD state 1 2VLCD/3 VLCD/3 0V −VLCD/3 −2VLCD/3 −VLCD VLCD 2VLCD/3 VLCD/3 state 2 0V −VLCD/3 −2VLCD/3 −VLCD (b) Resultant waveforms at LCD segment. Vstate1(t) = Vsn(t) − VBP0(t): Von(rms) = 0.577VLCD. Vstate2(t) = Vsn(t) − VBP1(t): Voff(rms) = 0.333VLCD. Fig.7 Waveforms for the 1 : 4 multiplex drive mode. 1999 Jul 30 12 MGL749 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 6.5 6.5.1 6.8 Oscillator 6.9 The clock frequency (fCLK) determines the LCD frame frequency. A clock signal must always be supplied to the device; removing the clock may freeze the LCD in a DC state. Timing The timing of the PCF8533 organizes the internal data flow of the device. This includes the transfer of display data from the display RAM to the display segment outputs. In cascaded applications, the synchronization signal (SYNC) maintains the correct timing relationship between the PCF8533s in the system. The timing also generates the LCD frame frequency which it derives as an integer division of the clock frequency (see Table 3). The frame frequency is a fixed division of the internal clock or of the frequency applied to pad CLK when an external clock is used. 6.7 6.10 Display RAM The display RAM is a static 80 × 4-bit RAM which stores LCD data. A logic 1 in the RAM bit map indicates the on-state of the corresponding LCD segment; similarly, a logic 0 indicates the off-state. There is a one-to-one correspondence between the RAM addresses and the segment outputs, and between the individual bits of a RAM word and the backplane outputs. The first RAM column corresponds to the 80 segments operated with respect to backplane BP0 (see Fig.8). In multiplexed LCD applications the segment data of the second, third and fourth column of the display RAM are time-multiplexed with BP1, BP2 and BP3 respectively. Display register The display latch holds the display data while the corresponding multiplex signals are generated. There is a one-to-one relationship between the data in the display latch, the LCD segment outputs and one column of the display RAM. 1999 Jul 30 Backplane outputs The LCD drive section includes four backplane outputs BP0 to BP3 which should be connected directly to the LCD. The backplane output signals are generated in accordance with the selected LCD drive mode. If less than four backplane outputs are required the unused outputs can be left open-circuit. In the 1 : 3 multiplex drive mode BP3 carries the same signal as BP1, therefore these two adjacent outputs can be tied together to give enhanced drive capabilities. In the 1 : 2 multiplex drive mode BP0 and BP2, BP1 and BP3 respectively carry the same signals and may also be paired to increase the drive capabilities. In the static drive mode the same signal is carried by all four backplane outputs and they can be connected in parallel for very high drive requirements. EXTERNAL CLOCK The condition for external clock is made by tying pad OSC to VDD; pad CLK then becomes the external clock input. 6.6 Segment outputs The LCD drive section includes 80 segment outputs (S0 to S79) which should be connected directly to the LCD. The segment output signals are generated in accordance with the multiplexed backplane signals and with data resident in the display latch. When less than 80 segment outputs are required the unused segment outputs should be left open-circuit. INTERNAL CLOCK The internal logic and the LCD drive signals of the PCF8533 are timed either by the built-in oscillator or from an external clock. When the internal oscillator is used, pad OSC should be connected to VSS. In this event, the output from pad CLK provides the clock signal for cascaded PCF8533s in the system. After power-up, SDA must be HIGH to guarantee that the clock starts. 6.5.2 PCF8533 13 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates When display data is transmitted to the PCF8533 the display bytes received are stored in the display RAM in accordance with the selected LCD drive mode. The data is stored as it arrives and does not wait for the acknowledge cycle as with the commands. Depending on the current mux mode data is stored singularly, in pairs, triplets or quadruplets. e.g. in 1 : 2 mux mode the RAM data is stored every second bit. To illustrate the filling order, an example of a 7-segment numeric display showing all drive modes is given in Fig.9; the RAM filling organization depicted applies equally to other LCD types. With reference to Fig.9, in the static drive mode the eight transmitted data bits are placed in bit 0 of eight successive display RAM addresses. In the 1 : 2 multiplex drive mode the eight transmitted data bits are placed in bits 0 and 1 of four successive display RAM addresses. PCF8533 In the 1 : 3 multiplex drive mode these bits are placed in bits 0, 1 and 2 of three successive addresses, with bit 2 of the third address left unchanged. This last bit may, if necessary, be controlled by an additional transfer to this address but care should be taken to avoid overriding adjacent data because full bytes are always transmitted. In the 1 : 4 multiplex drive mode the eight transmitted data bits are placed in bits 0, 1, 2 and 3 of two successive display RAM addresses. Table 3 LCD frame frequencies NOMINAL FRAME FREQUENCY (Hz) FRAME FREQUENCY 64 f CLK ----------24 display RAM addresses (rows) / segment outputs (S) handbook, full pagewidth 0 1 2 3 4 75 76 77 78 79 0 display RAM bits 1 (columns) / backplane outputs 2 (BP) 3 MGL750 Fig.8 Display RAM bit map showing direct relationship between display RAM addresses and segment outputs, and between bits in a RAM word and backplane outputs. 1999 Jul 30 14 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 6.11 6.13 Data pointer In 1 : 4 multiplex, all RAM addresses of bit 0 are selected, these are followed by the contents of bit 1, bit 2 and then bit 3. Similarly in 1 : 3 multiplex, bits 0, 1 and 2 are selected sequentially. In 1 : 2 multiplex, bits 0 and 1 are selected and, in the static mode, bit 0 is selected. The SYNC signal will reset these sequences to the following starting points; bit 3 for 1 : 4 multiplex, bit 2 for 1 : 3 multiplex, bit 1 for 1 : 2 multiplex and bit 0 for static mode. The PCF8533 includes a RAM bank switching feature in the static and 1 : 2 multiplex drive modes. In the static drive mode, the BANK SELECT command may request the contents of bit 2 to be selected for display instead of the contents of bit 0. In the 1 : 2 drive mode, the contents of bits 2 and 3 may be selected instead of bits 0 and 1. This gives the provision for preparing display information in an alternative bank and to be able to switch to it once it is assembled. Subaddress counter The storage of display data is conditioned by the contents of the subaddress counter. Storage is allowed to take place only when the contents of the subaddress counter agree with the hardware subaddress applied to A0, A1 and A2. The subaddress counter value is defined by the DEVICE SELECT command. If the contents of the subaddress counter and the hardware subaddress do not agree then data storage is inhibited but the data pointer is incremented as if data storage had taken place. The subaddress counter is also incremented when the data pointer overflows. 6.14 Input bank selector The input bank selector loads display data into the display RAM in accordance with the selected LCD drive configuration. Display data can be loaded in bit 2 in static drive mode or in bits 2 and 3 in 1 : 2 drive mode by using The storage arrangements described lead to extremely efficient data loading in cascaded applications. When a series of display bytes are sent to the display RAM, automatic wrap-over to the next PCF8533 occurs when the last RAM address is exceeded. Subaddressing across device boundaries is successful even if the change to the next device in the cascade occurs within a transmitted character (such as during the 27th display data byte transmitted in 1 : 3 multiplex mode). The hardware subaddress should not be changed whilst the device is being accessed on the I2C-bus interface. 1999 Jul 30 Output bank selector The output bank selector selects one of the four bits per display RAM address for transfer to the display latch. The actual bit selected depends on the particular LCD drive mode in operation and on the instant in the multiplex sequence. The addressing mechanism for the display RAM is realized using the data pointer. This allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display RAM. The sequence commences with the initialization of the data pointer by the LOAD DATA POINTER command. Following this, an arriving data byte is stored starting at the display RAM address indicated by the data pointer thereby observing the filling order shown in Fig.9. The data pointer is automatically incremented in accordance with the chosen LCD configuration. That is, after each byte is stored, the contents of the data pointer are incremented by eight (static drive mode), by four (1 : 2 multiplex drive mode), by three (1 : 3 multiplex drive mode) or by two (1 : 4 multiplex drive mode). If an I2C-bus data access is terminated early then the state of the data pointer will be unknown. The data pointer should be re-written prior to further RAM accesses. 6.12 PCF8533 15 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates the BANK SELECT command. The input bank selector functions independently to the output bank selector. 6.15 PCF8533 An additional feature is for an arbitrary selection of LCD segments to be blinked. This applies to the static and 1 : 2 LCD drive modes and can be implemented without any communication overheads. By means of the output bank selector, the displayed RAM banks are exchanged with alternate RAM banks at the blinking frequency. This mode can also be specified by the BLINK command. Blinker The display blinking capabilities of the PCF8533 are very versatile. The whole display can be blinked at frequencies selected by the BLINK command. The blinking frequencies are integer multiples of the clock frequency. The ratios between the clock and blinking frequencies depend on the mode in which the device is operating, see Table 4. In the 1 : 3 and 1 : 4 multiplex modes, where no alternate RAM bank is available, groups of LCD segments can be blinked by selectively changing the display RAM data at fixed time intervals. If the entire display is to be blinked at a frequency other than the nominal blinking frequency, this can be effectively performed by resetting and setting the display enable bit E at the required rate using the MODE SET command. Table 4 Blinking frequencies BLINKING MODE Off NORMAL OPERATING MODE RATIO − NOMINAL BLINKING FREQUENCY blinking off 2 Hz f CLK ----------768 2 Hz 1 Hz f CLK ------------1536 1 Hz 0.5 Hz f CLK ------------3072 0.5 Hz 1999 Jul 30 16 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... static a 2 Sn 3 Sn 4 Sn 5 Sn 6 b f g e 1 Sn 2 Sn 3 17 1:3 Sn 1 Sn 2 Sn 7 DP BP1 e c d DP b f BP1 c 0 1 2 3 BP2 DP a b BP0 n 5 n 6 n 7 c x x x b x x x a x x x f x x x g x x x e x x x d x x x DP x x x n n 1 n 2 n 3 a b x x f g x x e c x x d DP x x n n 1 n 2 b DP c x a d g x f e x x n n 1 a c b DP f e g d LSB c b a f g e d DP e 0 1 2 3 bit/ BP BP1 c d MSB a b f LSB g e c d DP MSB LSB b DP c a d g f e BP2 g BP3 MSB a c b DP f LSB e g d DP Product specification Fig.9 Relationships between LCD layout, drive mode, display RAM filling order and display data transmitted over the I2C-bus. MGL751 PCF8533 X = data bit unchanged. n 4 Sn bit/ BP f 1 n 3 BP0 a Sn Sn 0 1 2 3 bit/ BP d multiplex n 2 b f e 1:4 n 1 BP0 a g multiplex n MSB 0 1 2 3 bit/ BP g multiplex transmitted display byte 1 Sn c Sn Sn BP0 Sn d 1:2 display RAM filling order handbook, full pagewidth Sn LCD backplanes Philips Semiconductors LCD segments Universal LCD driver for low multiplex rates 1999 Jul 30 drive mode Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 7 7.4 CHARACTERISTICS OF THE I2C-BUS By connecting SDAACK to SDA on the PCF8533, the SDA line becomes fully I2C-bus compatible. Having the acknowledge output separated from the serial data line is advantageous in Chip-On-Glass (COG) applications. In COG applications where the track resistance from the SDAACK pad to the system SDA line can be significant, a potential divider is generated by the bus pull-up resistor and the Indium Tin Oxide (ITO) track resistance. It is possible that during the acknowledge cycle the PCF8533 will not be able to create a valid logic 0 level. By splitting the SDA input from the output the device could be used in a mode that ignores the acknowledge bit. In COG applications where the acknowledge cycle is required, it is necessary to minimize the track resistance from the SDAACK pad to the system SDA line to guarantee a valid low level. 7.5 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal. Bit transfer is illustrated in Fig.10. In single device application, the hardware subaddress inputs A0, A1 and A2 are normally tied to VSS which defines the hardware subaddress 0. In multiple device applications A0, A1 and A2 are tied to VSS or VDD in accordance with a binary coding scheme such that no two devices with a common I2C-bus slave address have the same hardware subaddress. START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P). The START and STOP conditions are illustrated in Fig.11. 7.3 7.6 Input filters To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on the SDA and SCL lines. System configuration A device generating a message is a ‘transmitter’, a device receiving a message is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’. The system configuration is illustrated in Fig.12. 1999 Jul 30 PCF8533 I2C-bus controller The PCF8533 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or transmit data to an I2C-bus master receiver. The only data output from the PCF8533 are the acknowledge signals of the selected devices. Device selection depends on the I2C-bus slave address, on the transferred command data and on the hardware subaddress. The following definition assumes SDA and SDAACK are connected and refers to the pair as SDA. 7.2 Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Acknowledgement on the I2C-bus is illustrated in Fig.13. The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a Serial Data line (SDA) and a Serial Clock Line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 7.1 PCF8533 18 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 7.7 PCF8533 In this way it is possible to configure the device then fill the display RAM with little overhead. I2C-bus protocol Two I2C-bus slave addresses (01110000 and 01110010) are reserved for the PCF8533. The least significant bit of the slave address that a PCF8533 will respond to is defined by the level tied at its input SA0. The PCF8533 is a write only device and will not respond to a read access. Therefore, two types of PCF8533 can be distinguished on the same I2C-bus which allows: The command bytes and control bytes are also acknowledged by all addressed PCF8533s connected to the bus. The display bytes are stored in the display RAM at the address specified by the data pointer and the subaddress counter. Both data pointer and subaddress counter are automatically updated and the data is directed to the intended PCF8533 device. 1. Up to 16 PCF8533s on the same I2C-bus for very large LCD applications 2. The use of two types of LCD multiplex on the same I2C-bus. The acknowledgement after each byte is made only by the (A0, A1 and A2) addressed PCF8533. After the last display byte, the I2C-bus master issues a STOP condition (P). Alternatively a START may be issued to RESTART an I2C-bus access. The I2C-bus protocol is shown in Fig.14. The sequence is initiated with a START condition (S) from the I2C-bus master which is followed by one of the two PCF8533 slave addresses available. All PCF8533s with the corresponding SA0 level acknowledge in parallel to the slave address, but all PCF8533s with the alternative SA0 level ignore the whole I2C-bus transfer. 7.8 Command decoder The command decoder identifies command bytes that arrive on the I2C-bus. The five commands available to the PCF8533 are defined in Table 5. After acknowledgement, a control byte follows which defines if the next byte is RAM or command information. The control byte also defines if the next following byte is a control byte or further RAM/command data. SDA SCL data line stable; data valid change of data allowed Fig.10 Bit transfer. 1999 Jul 30 19 MBA607 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8533 handbook, full pagewidth SDA SDA SCL SCL S P START condition STOP condition MBC622 Fig.11 Definition of START and STOP conditions. MASTER TRANSMITTER/ RECEIVER SLAVE TRANSMITTER/ RECEIVER SLAVE RECEIVER MASTER TRANSMITTER/ RECEIVER MASTER TRANSMITTER SDA SCL MGA807 Fig.12 System configuration. handbook, full pagewidth DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER 1 2 8 9 S clock pulse for acknowledgement START condition MBC602 Fig.13 Acknowledgement on the I2C-bus. 1999 Jul 30 20 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... RAM/command byte L S P B M A S B EXAMPLES a) transmit two bytes of RAM data S S 0 1 1 1 0 0 A 0 A 0 1 0 A RAM DATA A A COMMAND A 0 0 A COMMAND A P A COMMAND A 0 1 A RAM DATA A RAM DATA A P b) transmit two command bytes S S 0 1 1 1 0 0 A 0 A 1 0 0 c) transmit one command byte and two RAM bytes 21 S S 0 1 1 1 0 0 A 0 A 1 0 0 RAM DATA A P MGL752 Philips Semiconductors control byte S S 0 1 1 1 0 0 A 0 A Co RS 0 Universal LCD driver for low multiplex rates 1999 Jul 30 R/W = 0 slave address Fig.14 I2C-bus protocol. MSB Co RS UNUSED Fig.15 Format of control byte. Product specification MGL753 PCF8533 Co = 0; last control byte. Co = 1; control bytes continue. RS = 0; data is a command byte RS = 1; data is a display byte LSB Philips Semiconductors Product specification Universal LCD driver for low multiplex rates Table 5 PCF8533 Definition of PCF8533 commands COMMAND MODE SET OPCODE 1 1 0 0 E OPTIONS B M1 M0 Table 6 DESCRIPTION defines LCD drive mode Table 7 defines LCD bias configuration Table 8 defines display status; the possibility to disable the display allows implementation of blinking under external control LOAD DATA POINTER 0 P6 P5 P4 P3 P2 P1 P0 Table 9 seven bits of immediate data, bits P6 to P0, are transferred to the data pointer to define one of eighty display RAM addresses DEVICE SELECT 1 1 1 0 0 A2 A1 A0 Table 10 three bits of immediate data, bits A0 to A3, are transferred to the subaddress counter to define one of eight hardware subaddresses BANK SELECT 1 1 1 1 1 0 I O Table 11 defines input bank selection (storage of arriving display data) Table 12 defines output bank selection (retrieval of LCD display data); the BANK SELECT command has no effect in 1 : 3 and 1 : 4 multiplex drive modes BLINK 1 Table 6 1 1 1 0 A BF 1 BF Table 13 0 Table 14 defines the blinking frequency selects the blinking mode; normal operation with frequency set by BF1, BF0 or blinking by alternation of display RAM banks. Alternation blinking does not apply in 1 : 3 and 1 : 4 multiplex drive modes Mode set option 1 LCD DRIVE MODE DRIVE MODE Table 7 BITS BACKPLANE M1 Static 1 BP 0 1 1:2 MUX (2 BP) 1 0 1:3 MUX (3 BP) 1 1 1:4 MUX (4 BP) 0 0 Mode set option 2 LCD BIAS Table 8 M0 BIT B 1⁄ 3bias 0 1⁄ 2bias 1 Mode set option 3 DISPLAY STATUS BIT E Disabled (blank) 0 Enabled 1 1999 Jul 30 22 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates Table 9 Load data pointer option 1 DESCRIPTION 7.10 P6 P5 P4 P3 P2 P1 P0 Table 10 Device select option 1 DESCRIPTION 3 bit binary value of 0 to 7 BITS A2 A1 A0 Table 11 Bank select option 1 (Input) STATIC 1 : 2 MUX BIT I RAM bit 0 RAM bits 0 and 1 0 RAM bit 2 RAM bits 2 and 3 1 The SYNC line is provided to maintain the correct synchronization between all cascaded PCF8533s. This synchronization is guaranteed after the Power-on reset. The only time that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in adverse electrical environments, or by the definition of a multiplex mode when PCF8533s with different SA0 levels are cascaded). SYNC is organized as an input/output pad; the output selection being realized as an open-drain driver with an internal pull-up resistor. A PCF8533 asserts the SYNC line at the onset of its last active backplane signal and monitors the SYNC line at all other times. Should synchronization in the cascade be lost, it will be restored by the first PCF8533 to assert SYNC. The timing relationship between the backplane waveforms and the SYNC signal for the various drive modes of the PCF8533 are shown in Fig.17. Table 12 Bank select option 2 (Output) STATIC 1 : 2 MUX BIT O RAM bit 0 RAM bits 0 and 1 0 RAM bit 2 RAM bits 2 and 3 1 Table 13 Blink option 1 BITS BLINK FREQUENCY BF1 BF0 Off 0 0 2 Hz 0 1 1 Hz 1 0 0.5 Hz 1 1 The contact resistance between the SYNC pads of cascaded devices must be controlled. If the resistance is too high then the device will not be able to synchronize properly. This is particularly applicable to COG applications. Table 15 shows the limiting values for contact resistance. Table 14 Blink option 2 BLINK MODE Normal blinking(1) Alternation blinking BIT A 0 1 Table 15 SYNC contact resistance Note 1. Normal blinking is assumed when multiplex rates 1 : 3 or 1 : 4 are selected. 7.9 Display controller The display controller executes the commands identified by the command decoder. It contains the status registers of the PCF8533 and co-ordinates their effects. The controller is also responsible for loading display data into the display RAM as required by the filling order. 1999 Jul 30 Cascaded operation In large display configurations, up to 16 PCF8533s can be distinguished on the same I2C-bus by using the 3-bit hardware subaddress (A0, A1 and A2) and the programmable I2C-bus slave address (SA0). When cascaded PCF8533s are synchronized they can share the backplane signals from one of the devices in the cascade. Such an arrangement is cost-effective in large LCD applications since the backplane outputs of only one device need to be through-plated to the backplane electrodes of the display. The other PCF8533s of the cascade contribute additional segment outputs but their backplane outputs are left open-circuit (see Fig.16). BITS 7 bit binary value of 0 to 79 PCF8533 23 NUMBER OF DEVICES MAXIMUM CONTACT RESISTANCE 2 6000 Ω 3 to 5 2200 Ω 6 to 10 1200 Ω 11 to 16 700 Ω Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8533 handbook, full pagewidth SDAACK VDD VLCD SDA 80 segment drives SCL SYNC LCD PANEL PCF8533 CLK (up to 5120 elements) OSC A0 A1 A2 SA0 VSS BP0 to BP3 (open-circuit) VLCD VDD R HOST MICROPROCESSOR/ MICROCONTROLLER tr 2CB SDAACK VDD SDA VLCD 80 segment drives SCL SYNC PCF8533 CLK 4 backplanes BP0 to BP3 OSC MGL754 VSS A0 A1 A2 SA0 VSS Fig.16 Cascaded PCF8533 configuration. 1999 Jul 30 24 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8533 1 Tframe = f frame handbook, full pagewidth BP0 SYNC (a) static drive mode. BP1 (1/2 bias) BP1 (1/3 bias) SYNC (b) 1 : 2 multiplex drive mode. BP2 SYNC (c) 1 : 3 multiplex drive mode. BP3 SYNC MGL755 (d) 1 : 4 multiplex drive mode. Fig.17 Synchronization of the cascade for the various PCF8533 drive modes. 1999 Jul 30 25 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8533 8 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER MIN. MAX. UNIT VDD supply voltage −0.5 +6.5 V IDD supply current −50 +50 mA VLCD LCD supply voltage VSS − 0.5 +7.5 V ILCD LCD supply current −50 +50 mA ISS negative supply current −50 +50 mA VI(n) input voltage on pads SDA, SCL, CLK, SYNC, SA0, OSC and A0 to A2 VSS − 0.5 VDD + 0.5 V VO(n) output voltage on pads S0 to S79 and BP0 to BP3 VSS − 0.5 VLCD + 0.5 V II DC input current −10 +10 mA IO DC output current −10 +10 mA Ptot total power dissipation − 400 mW P/out power dissipation per output − 100 mW Tstg storage temperature −65 +150 °C 9 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices (see “Handling MOS Devices” ). 1999 Jul 30 26 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8533 10 DC CHARACTERISTICS VDD = 1.8 to 5.5 V; VSS = 0 V; VLCD = 2.5 to 6.5 V; Tamb = −40 to +85 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDD supply voltage 1.8 VLCD LCD supply voltage IDD supply current fCLK = 1536 Hz; note 1 − ILCD LCD supply current fCLK = 1536 Hz; note 1 − 2.5 − 5.5 V − 6.5 V 8 20 µA 24 60 µA Logic VIL LOW-level input voltage VSS − 0.3VDD V VIH HIGH-level input voltage 0.7VDD − VDD V IOL1 LOW-level output current on pads CLK and SYNC VOL = 0.4 V; VDD = 5 V 1 − − mA IOH1 HIGH-level output current pad CLK VOH = 4.6 V; VDD = 5 V − − mA IOL2 LOW-level output current pad SDA VOL = 0.4 V; VDD = 5 V 3 − − mA IL1 leakage current on pads SA0, A0 to A2, CLK, SDA and SCL VI = VDD or VSS −1 − +1 µA IL2 leakage current pad OSC VI = VDD −1 − +1 µA VPOR Power-on reset voltage level 1.0 1.3 1.6 V CI input capacitance note 2 − − 7 pF −1 LCD outputs VBP DC voltage component on pads BP0 to BP3 CBP = 35 nF −100 − +100 mV VS DC voltage component on pads S0 to S79 CS = 5 nF −100 − +100 mV RBP output resistance at pads BP0 to BP3 VLCD = 5 V; note 3 − 1.5 10 kΩ RS output resistance at pads S0 to S79 − 6.0 13.5 kΩ VLCD = 5 V; note 3 Notes 1. LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50% duty factor; I2C-bus inactive. 2. Not tested; given by design. 3. Outputs measured one at a time. 1999 Jul 30 27 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8533 11 AC CHARACTERISTICS VDD = 1.8 to 5.5 V; VSS = 0 V; VLCD = 2.5 to 6.5 V; Tamb = −40 to + 85 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS VDD = 5 V; note 1 MIN. TYP. MAX. UNIT fCLK oscillator frequency at pad CLK 797 1536 3046 Hz tCLKH input CLK HIGH time 130 − − µs tCLKL input CLK LOW time 130 − − µs td(p)SYNC SYNC propagation delay time − 30 − ns tSYNCL SYNC LOW time 1 − − µs td(PLCD) driver delays with test loads − − 30 µs VLCD = 5 V Timing characteristics: I2C-bus; note 2 fSCL SCL clock frequency − − 400 kHz tBUF bus free time between a STOP and START 1.3 − − µs tHD;STA START condition hold time 0.6 − − µs tSU;STA set-up time for a repeated START condition 0.6 − − µs tLOW SCL LOW time 1.3 − − µs tHIGH SCL HIGH time 0.6 − − µs tr SCL and SDA rise time − − 0.3 µs tf SCL and SDA fall time − − 0.3 µs Cb capacitive bus line load − − 400 pF tSU;DAT data set-up time 100 − − ns tHD;DAT data hold time 0 − − ns tSU;STO set-up time for STOP condition 0.6 − − µs tSW tolerable spike width on bus − − 50 ns Notes 1. Typical output duty cycle of 50%. 2. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. handbook, full pagewidth SYNC 6.8 Ω VDD (2%) CLK 3.3 k Ω 0.5VDD (2%) BP0 to BP3, and S0 to S79 SDA, SCL (2%) VDD 1 nF VSS MGS120 Fig.18 Test loads. 1999 Jul 30 1.5 k Ω 28 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8533 1/ fCLK handbook, full pagewidth tCLKH tCLKL CLK 0.7VDD 0.3VDD SYNC 0.7VDD 0.3VDD td(p)(SYNC) td(p)(SYNC) tSYNCL 0.5 V BP0 to BP3, and S0 to S79 (VDD = 5 V) 0.5 V tPLCD MGL761 Fig.19 Driver timing waveforms. dbook, full pagewidth SDA t BUF tf t LOW SCL t HD;STA t HD;DAT tr t HIGH t SU;DAT SDA MGA728 t SU;STA Fig.20 I2C-bus timing waveforms. 1999 Jul 30 29 t SU;STO Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8533 12 BONDING PAD LOCATIONS Bonding pad locations (dimensions in µm) All x and y coordinates are referenced to centre of chip (see Fig.22). PAD x y SYMBOL PAD x y SDAACK 1 −1079.20 −594.40 S20 38 +1717.60 +594.40 SDA 2 −839.20 −594.40 S21 39 +1637.60 +594.40 SDA 3 −759.20 −594.40 S22 40 +1557.60 +594.40 SCL 4 −599.20 −594.40 S23 41 +1477.60 +594.40 SCL 5 −519.20 −594.40 S24 42 +1317.60 +594.40 CLK 6 −414.80 −594.40 S25 43 +1237.60 +594.40 VDD 7 −284.80 −594.40 S26 44 +1157.60 +594.40 SYNC 8 +4.20 −594.40 S27 45 +1077.60 +594.40 OSC 9 +119.20 −594.40 S28 46 +997.60 +594.40 A0 10 +249.20 −594.40 S29 47 +917.60 +594.40 A1 11 +379.20 −594.40 S30 48 +837.60 +594.40 A2 12 +581.20 −594.40 S31 49 +757.60 +594.40 SA0 13 +711.20 −594.40 S32 50 +677.60 +594.40 SYMBOL VSS 14 +841.20 −594.40 S33 51 +597.60 +594.40 VLCD 15 +1099.60 −594.40 S34 52 +437.60 +594.40 BP2 16 +1277.60 −594.40 S35 53 +357.60 +594.40 BP0 17 +1357.60 −594.40 S36 54 +277.60 +594.40 S0 18 +1437.60 −594.40 S37 55 +197.60 +594.40 S1 19 +1517.60 −594.40 S38 56 +117.60 +594.40 S2 20 +1597.60 −594.40 S39 57 +37.60 +594.40 S3 21 +1677.60 −594.40 S40 58 −42.40 +594.40 S4 22 +1757.60 −594.40 S41 59 −122.40 +594.40 S5 23 +1837.60 −594.40 S42 60 −202.40 +594.40 S6 24 +1917.60 −594.40 S43 61 −282.40 +594.40 S7 25 +1997.60 −594.40 S44 62 −362.40 +594.40 S8 26 +2077.60 −594.40 S45 63 −442.40 +594.40 S9 27 +2157.60 −594.40 S46 64 −602.40 +594.40 S10 28 +2237.60 −594.40 S47 65 −682.40 +594.40 S11 29 +2317.60 −594.40 S48 66 −762.40 +594.40 S12 30 +2357.60 +594.40 S49 67 −842.40 +594.40 S13 31 +2277.60 +594.40 S50 68 −922.40 +594.40 S14 32 +2197.60 +594.40 S51 69 −1002.40 +594.40 S15 33 +2117.60 +594.40 S52 70 −1082.40 +594.40 S16 34 +2037.60 +594.40 S53 71 −1162.40 +594.40 S17 35 +1957.60 +594.40 S54 72 −1242.40 +594.40 S18 36 +1877.60 +594.40 S55 73 −1322.40 +594.40 S19 37 +1797.60 +594.40 S56 74 −1402.40 +594.40 1999 Jul 30 30 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8533 SYMBOL PAD x y SYMBOL PAD x y S57 75 −1562.40 +594.40 S79 97 −1442.40 −594.40 S58 76 −1642.40 +594.40 BP3 98 −1362.40 −594.40 S59 77 −1722.40 +594.40 BP1 99 −1282.40 −594.40 S60 78 −1802.40 +594.40 S61 79 −1882.40 +594.40 C1 +2300.5 +55.0 80 −1962.40 − S62 +594.40 C2 −2320.2 +107.0 S63 81 −2042.40 − +594.40 F −2208.3 −165.4 82 −2122.40 − S64 +594.40 S65 83 −2202.40 +594.40 S66 84 −2282.40 +594.40 S67 85 −2362.40 +594.40 S68 86 −2322.40 −594.40 S69 87 −2242.40 −594.40 S70 88 −2162.40 −594.40 S71 89 −2082.40 −594.40 S72 90 −2002.40 −594.40 S73 91 −1922.40 −594.40 S74 92 −1842.40 −594.40 S75 93 −1762.40 −594.40 Bottom left S76 94 −1682.40 −594.40 Top right S77 95 −1602.40 −594.40 Note S78 96 −1522.40 −594.40 1. The dummy pads are not tested. Alignment marks Dummy pads (connected to segments shown; note D1 (S11) +2469.70 −594.40 D2 (S11) +2549.70 −594.40 D3 (S12) +2517.60 +594.40 D4 (S12) +2437.60 +594.40 D5 (S67) −2442.30 +594.40 D6 (S67) −2522.30 +594.40 D7 (S68) −2554.40 −594.40 D8 (S68) −2474.40 −594.40 − −2695.00 −750.00 − +2695.00 +750.00 Chip corners (pre-sawing) handbook, halfpage REF REF C2 MGL756 F REF Fig.21 Alignment markers. 1999 Jul 30 31 C1 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... D6 D5 S67 S12 D4 D3 C1 F x 0, 0 S11 D1 D2 BP2 BP0 S0 S1 S2 VLCD VSS SA0 A2 A1 A0 OSC SYNC CLK VDD SCL SDA SDAACK S79 BP3 BP1 . . . MGL759 Product specification PCF8533 Fig.22 Bonding pad locations. . . . . . . . . . D7 D8 S68 32 The position of the bonding pads is not to scale. Chip dimensions: approximately 5.40 × 1.51 mm. Bump dimensions: 90 × 50 × 17.5 µm. Wafer thickness: 381 µm. Philips Semiconductors . . . . . . y Universal LCD driver for low multiplex rates ok, full pagewidth 1999 Jul 30 PC8533-2 C2 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8533 13 DEVICE PROTECTION handbook, full pagewidth VDD VDD VSS VSS SA0 VDD CLK SCL VSS VDD VSS OSC VSS VDD SDA SYNC VSS VSS VDD A0, A1 A2 SDAACK VSS VLCD VSS BP0, BP1, BP2, BP3 VSS VLCD VLCD S0 to S79 VSS VSS Fig.23 Device protection diagram. 1999 Jul 30 33 MGL760 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8533 14 TRAY INFORMATION x handbook, full pagewidth A C y D B F E MGL757 The dimensions are given in Table 16. Fig.24 Tray details. Table 16 Dimensions DIM. DESCRIPTION A pocket pitch, x direction VALUE 7.37 mm B pocket pitch, y direction 3.68 mm C pocket width, x direction 5.50 mm D pocket width, y direction 1.60 mm E tray width, x direction 50.8 mm F tray width, y direction 50.8 mm x no. pockets in x direction 6 y no. pockets in y direction 12 handbook, halfpage PC8533-2 MGL758 The orientation of the IC in a pocket is indicated by the position of the IC type name on the die surface with respect to the chamfer on the upper left corner of the tray. Refer to the bonding pad location diagram for the orientating and position of the type name on the die surface. Fig.25 Tray alignment. 1999 Jul 30 34 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8533 15 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 16 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 17 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 18 BARE DIE DISCLAIMER All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of ninety (90) days from the date of Philips' delivery. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There is no post waffle pack testing performed on individual die. Although the most modern processes are utilized for wafer sawing and die pick and place into waffle pack carriers, Philips Semiconductors has no control of third party procedures in the handling, packing or assembly of the die. Accordingly, Philips Semiconductors assumes no liability for device functionality or performance of the die or systems after handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used. 1999 Jul 30 35 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 62 5344, Fax.+381 11 63 5777 For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com © Philips Electronics N.V. 1999 SCA 67 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 465006/02/pp36 Date of release: 1999 Jul 30 Document order number: 9397 750 05045