INTEGRATED CIRCUITS DATA SHEET PCF8813 (67 + 1) × 102 pixels matrix LCD driver Product specification Supersedes data of 2002 Sep 24 2004 Mar 05 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver CONTENTS 1 FEATURES 2 APPLICATIONS 3 GENERAL DESCRIPTION 4 ORDERING INFORMATION 5 BLOCK DIAGRAM 6 PINNING 7 FUNCTIONAL DESCRIPTION 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 I/O buffer and interface Oscillator Address counter Display data RAM Timing generator Display address counter LCD row and column drivers LCD waveforms and DDRAM to data mapping DDRAM addressing Data order Mirror X Mirror Y Bottom row swap Output row order 8 PARALLEL INTERFACES 8.1 8.2 6800-type parallel interface 8080-type parallel interface 9 SERIAL INTERFACES 9.1 9.1.1 9.1.2 9.2 9.2.1 9.2.2 Serial peripheral interface Write mode Read mode Serial interface (3-line) Write mode Read mode 10 I2C-BUS INTERFACE (Hs-MODE) 10.1 10.1.1 10.1.2 10.1.3 10.1.4 10.2 10.3 Characteristics of the I2C-bus (Hs-mode) System configuration Bit transfer Start and stop conditions Acknowledge I2C-bus Hs-mode protocol Command decoder 11 INSTRUCTIONS 11.1 11.2 11.3 11.4 11.5 11.6 Initialization Reset function Power-down mode Display Control Set Y address of RAM Set X address of RAM 2004 Mar 05 2 PCF8813 11.7 11.8 11.9 11.10 11.11 11.12 Set maximum X address or Y address Set display start line, initial start row and row 0 Set normal or partial display mode Free programmable multiplex rate Set HV generator stages Bias system 12 TEMPERATURE COMPENSATION 13 LIMITING VALUES 14 HANDLING 15 DC CHARACTERISTICS 16 AC CHARACTERISTICS 17 MODULE MAKER PROGRAMMING 17.1 17.2 17.3 17.4 17.4.1 17.4.2 17.5 17.5.1 17.5.2 17.5.3 17.6 17.7 17.8 17.9 LCD voltage calibration Manufacturer identity Seal bit One time programming Architecture Operations Interface commands Disable OTP command Module maker calibration Refresh Filling the shift register Programming flow Programming specification Programming examples 18 APPLICATION INFORMATION 18.1 18.2 18.3 Protection from light Application examples Chip-on-glass applications 19 DEVICE PROTECTION DIAGRAM 20 BONDING PAD INFORMATION 21 TRAY INFORMATION 22 DATA SHEET STATUS 23 DEFINITIONS 24 DISCLAIMERS 25 PURCHASE OF PHILIPS I2C COMPONENTS Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver 1 PCF8813 FEATURES • Single-chip LCD controller or driver • 67 row + 1 icon row, 102 column outputs (the icon row is available twice to allow icons to be displayed at the top or at the bottom of the display) • Very low power consumption, optimized for battery operated systems • Start address line which allows, for instance, scrolling of the displayed image • On-chip: • Programmable display RAM pointers for various display sizes – Display data RAM 68 × 102 bits • Slim chip layout optimized for chip-on-glass applications – Configurable voltage multiplier (× 5, × 4, × 3 and × 2) generating highly accurate VLCD and includes booster capacitors (external VLCD is also possible) • Operating temperature range −40 to +85 °C • Very close tolerance on VLCD and frame frequency for excellent optical performance – Temperature compensation of VLCD with four selectable temperature coefficients • Support for LCD cell tolerance compensation of VLCD by OTP storage. – Generation of intermediate LCD bias voltages – Highly-accurate built-in oscillator requiring no external components (an external clock is also possible) 2 APPLICATIONS • Telecom equipment • High integration level resulting in minimum number of external capacitors and resistors • Portable instruments • Point of sale terminals. • Selectable 8-bit parallel interface, 3-line or 4-line Serial Peripheral Interface (SPI), 3-line serial interface and high-speed I2C-bus interface 3 • External reset input GENERAL DESCRIPTION The PCF8813 is a low power CMOS LCD controller driver designed to drive a graphic display of 67 rows and 102 columns plus an icon row of up to 102 symbols. All necessary functions for the display are provided in a single chip, including on-chip generation of the LCD supply and bias voltages, resulting in a minimum of external components and low power consumption. The PCF8813 can interface to microcontrollers via a parallel, serial or I2C-bus interface. • CMOS compatible inputs • Mux rates: 1 : 9 to 1 : 65 in steps of 8 and 1 : 68 • Logic supply voltage range 1.7 to 3.3 V • High voltage generator supply voltage range 2.4 to 4.5 V • Display supply voltage range 3.0 to 9.0 V • One Time Programmable (OTP) VLCD trimming • Horizontal and vertical mirroring • Status read which allows chip recognition and content checking of some registers 4 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME PCF8813U/2DA/2 2004 Mar 05 − DESCRIPTION chip with bumps in tray for COG 3 VERSION − Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver 5 PCF8813 BLOCK DIAGRAM VDD1 handbook, full pagewidth VDD2 VDD3 R0 to R67 C0 to C101 102 68 ROW DRIVERS COLUMN DRIVERS VLCDIN BIAS VOLTAGE GENERATOR SHIFT REGISTER DATA PROCESSING VSS1 VSS2 VOTPPROG VLCDSENSE VLCDOUT FOUR-STAGE HIGH-VOLTAGE GENERATOR RESET RES OSCILLATOR OSC DISPLAY DATA RAM 68 × 102 bits T1 TIMING GENERATOR T2 T3 ADDRESS COUNTER T4 DISPLAY ADDRESS COUNTER T5 COMMAND DECODER PCF8813 I/O BUFFER PARALLEL / SERIAL / I 2C-BUS INTERFACE 3 Fig.1 Block diagram. 2004 Mar 05 4 DB0 DB1 DB2/SA0 DB3/SA1 DB4 DB5/SDOUT DB6/SCLK DB7/SDATA SDAHOUT SDAH SCLH/SCE E/RD R/W/WR D/C PS [2:0] EXT MGU619 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver 6 PCF8813 PINNING SYMBOL PAD(1) R15 to R0 7 to 22 R16 to R31 23 to 38 C0 to C101 39 to 140 R67 141 R66 to R48 142 to 160 R32 to R47 161 to 176 DESCRIPTION LCD row driver outputs LCD column driver outputs LCD row driver output for row 67 (used only for icons) LCD row driver outputs R67 177 duplicated LCD row driver output for row 67 (used only for icons) SDAHOUT 183 data output for I2C-bus interface; notes 2 and 3 SDAH 184 to 185 data output for I2C-bus interface; note 2 VDD1 186 to 191 supply voltage 1; note 4 VDD3 192 to 196 supply voltage 3; note 4 VDD2 197 to 206 supply voltage 2; note 4 VDD1 207 supply voltage 1; notes 4 and 5 R/W/WR 208 READ/WRITE (6800) or WRITE (8080 interface) input; note 6 E/RD 209 clock enable (6800 interface) or READ (8080 interface) input; note 7 DB0 210 parallel data input/output; note 8 DB1 211 parallel data input/output; note 8 DB2/SA0 212 parallel data input/output or I2C-bus slave address input (bit 0) DB3/SA1 213 parallel data input/output or I2C-bus slave address input (bit 1) DB4 214 parallel data input/output; note 8 DB5/SDOUT 215 parallel data input/output or serial output (SDOUT) DB6/SCLK 216 parallel data input/output or output or serial clock input (SCLK) DB7/SDATA 217 parallel data input/output or serial data input (SDATA) VSS1 218 ground voltage 1; notes 5 and 9 D/C 219 data/command; note 10 SCE/SCLH 220 to 221 chip enable or clock input for I2C-bus interface VOTPPROG 222 to 224 voltage inputs for OTP programming; see note 11 VDD1 225 supply voltage 1; notes 4 and 5 OSC 226 oscillator input; note 12 VSS2 227 to 236 ground voltage 2; note 9 VSS1 237 to 246 ground voltage 1; note 9 T5 247 test input 5; note 13 T1 248 test input 1; note 13 T2 249 test input 2; note 13 PS0 250 parallel/serial/I2C-bus data input selection pad 0 PS1 251 parallel/serial/I2C-bus data input selection pad 1 PS2 252 parallel/serial/I2C-bus data input selection pad 2 VDD1 253 supply voltage 1; notes 4 and 5 T4 254 test output 4; note 13 T3 255 test output 3; note 13 2004 Mar 05 5 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver SYMBOL PAD(1) PCF8813 DESCRIPTION VLCDIN 256 to 262 LCD supply voltage input; note 14 VLCDOUT 263 to 271 generated LCD supply voltage; note 14 VLCDSENSE 272 voltage multiplier (VLCD) regulation input; note 14 RES 273 external reset input Notes 1. Dummy pads are located at positions 1, 2, 3, 5, 6, 179, 180, 181, 182 and 274; dummy and alignment pads are located at positions 4 and 178. 2. When not in use, this pad must be connected to VDD1 or VSS1. 3. Output SDAHOUT is used as the data acknowledge output when the I2C-bus is selected. By connecting SDAHOUT to SDAH externally, the SDAH line becomes fully I2C-bus compatible. Having the acknowledge output separated from the serial data line is advantageous in COG applications because where the track resistance from the SDAHOUT pad to the SDAH line can be significant, a potential divider is generated by the bus pull-up resistor and the ITO track resistance. Therefore it is possible during the acknowledge cycle that the PCF8813 will not create a logic LOW level. By splitting the SDAH input from the SDAHOUT output, the device could be used in a mode that ignores the acknowledge bit. In COG applications where the acknowledge cycle is required, it is necessary to minimize the track resistance from the SDAHOUT pad to the system SDAH line to guarantee a valid LOW level. 4. VDD2 and VDD3 supply the internal voltage generator, both have the same voltage and may be connected together outside of the chip; VDD1 supplies the remainder of the chip. VDD1, VDD2 and VDD3 can be connected together but then care must be taken with respect to the supply voltage range. If the internal voltage generator is not used, pads VDD2 and VDD3 must be connected to pads VDD1. 5. This pad can be used to tie-off unused input pads to the power supply voltage or to ground. 6. This input is not used in serial and I2C-bus mode and must therefore be connected to either VDD1 or VSS1. 7. This input is not used when the serial or I2C-bus interface is selected and must therefore be connected to VDD1 or VSS1. 8. When serial or I2C-bus mode is selected, the unused parallel pads must be connected to VDD1 or VSS1. 9. Supply rails VSS1 and VSS2 must be connected together. 10. This input is not used with the 3-line serial interface and must therefore be connected to VDD1 or VSS1. 11. This pad can be connected externally to the SCE/SCLH pad to reduce the number of pads routed in COG applications. When not connected in this configuration, VOTPPROG must be connected to either VDD1 or VSS1 after completion of OTP programming and after the seal bit has been set. 12. When the on-chip oscillator is used, the OSC input must be connected to VDD1. If an external clock signal is used, then this is connected to the OSC input. If both the oscillator and external clock are inhibited by connecting pad OSC to VSS1, the display is not clocked and may be in a DC state. To avoid this, the chip should always be put into Power-down mode before stopping the clock. 13. Test pads T1 to T5 are not accessible to users: T1, T2 and T5 must be connected to VSS; T3 and T4 must be open-circuit. 14. Positive power supply for the liquid crystal display (see also Figs 51, 52 and 53): a) If the internal voltage generator is used, pads VLCDIN, VLCDSENSE and VLCDOUT must be connected together. b) An external LCD supply voltage can be supplied using the VLCDIN pad, this requires that pad VLCDOUT is open-circuit, pad VLCDSENSE is connected to the VLCDIN input, and the internal voltage generator is switched off. In Power-down mode, the external LCD supply voltage must be switched off. 2004 Mar 05 6 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver 7 7.5 FUNCTIONAL DESCRIPTION 7.1 One of five industrial standard interfaces can be selected using the interface configuration inputs PS2, PS1 and PS0. PS1 PS0 0 0 0 3-line SPI 0 0 1 4-line SPI 0 1 0 8080 parallel interface 0 1 1 6800 parallel interface 1 0 0 1 1 0 1 0 1 1 1 1 7.2 7.6 INTERFACE high-speed I2C-bus 7.7 interface 3-line serial interface Oscillator Address counter The Address Counter (AC) assigns addresses to the display data RAM for writing. The X address X[6:0] and the Y address Y[3:0] are set separately. 7.4 Display data RAM The PCF8813 contains a 68 × 102 bit static RAM which stores the display data. The Display Data RAM (DDRAM) is divided into eight banks of 102 bytes (8 × 8 × 102 bits), one bank of 1 × 3 × 102 bits and a separate bank of 1 × 1 × 102 for icons. During RAM access, data is transferred to the RAM via any of the four interfaces. There is a direct correspondence between the X address and the column output number. 2004 Mar 05 LCD row and column drivers The PCF8813 contains 68 row and 102 column drivers, which connect the appropriate LCD bias voltages in a sequence to the display in accordance with the data that is to be displayed. Figure 2 shows typical waveforms. Unused outputs should be left unconnected. The on-chip oscillator provides the clock signal for the display system. No external components are required. An external clock signal, if used, is connected to this input. 7.3 Display address counter The display is generated by continuously shifting rows of RAM data to the dot matrix LCD via the column outputs. The display status (all dots on/off and normal/inverse video) is set by bits D and E in the display control command. Parallel/serial/I2C-bus interface selection PS2 Timing generator The timing generator produces the various signals required to drive the internal circuitry. Internal chip operation is not affected by operations on the data buses. I/O buffer and interface Table 1 PCF8813 7 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver 7.8 PCF8813 LCD waveforms and DDRAM to data mapping frame n + 1 frame n ROW 0 R0 (t) ROW 1 R1 (t) COL 0 C0 (t) COL 1 C1 (t) Vstate0(t) VLCD V2 V3 Vstate1 (t) V4 V5 VSS VLCD V2 V3 V4 V5 VSS VLCD V2 V3 V4 V5 VSS VLCD V2 V3 V4 V5 VSS VLCD − VSS V3 − VSS Vstate1(t) VLCD − V2 0V V3 − V2 V4 − V5 0V VSS − V5 V4 − VLCD VSS − VLCD VLCD − VSS V3 − VSS Vstate2 (t) VLCD − V2 0V V3 − V2 V4 − V5 0V VSS − V5 V4 − VLCD VSS − VLCD 0 1 2 3 4 5 6 7 8... ... 67 0 1 2 3 4 5 6 7 8... Vstate0(t) = C1(t) − R0(t). Vstate1(t) = C1(t) − R1(t). Fig.2 Typical LCD driver waveforms. 2004 Mar 05 8 ... 67 MGU620 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver PCF8813 DPRAM bank 0 top of LCD R0 bank 1 R8 bank 2 R16 LCD bank 3 R24 bank 8 R64 bank 10 R67 MGU621 Fig.3 Display data RAM. 2004 Mar 05 9 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver 7.9 PCF8813 DDRAM addressing handbook, MSB full pagewidth 0 LSB MSB MSB 8 10 icon data LSB 0 LSB X address 101 Y address MGU622 Fig.4 Sequence of writing data bytes into the RAM. Data is downloaded in bytes into the RAM matrix of the PCF8813 as indicated in Fig.4. The display data RAM has a matrix of 68 by 102 bits. The columns are addressed by the X address pointer whilst the rows are addressed in groups of 8 by the Y address pointer. However, there are only three rows in bank 8 and one row in bank 10. There is no bank 9. Thus the address ranges are: X = 0 to 101 (1100101) and Y = 0 to 8 and then 10 (1010). The PCF8813 is limited to 102 columns by 68 rows, addressing the RAM outside this area is not allowed. Addressing in bank 10 is a special case as these RAM locations are not automatically accessed. Bank 10 is reserved for icons. Icon locations must be addressed explicitly by setting the Y address pointer to 10. The Y address pointer does not auto-increment when the X address overflows or underflows (it stays in set to bank 9). Writing icon data is independent of the horizontal or vertical addressing (V-bit) but is affected by the Mirror X (MX) and Mirror Y (MY) bits. MX and MY are described in Sections 7.11 and 7.12. Two different addressing modes are possible; horizontal addressing and vertical addressing. In the horizontal addressing mode (V = 0) the X address increments after each byte. After the last X address (X = 101), x wraps-around to 0 and Y increments to address the next row (see Fig.5) until bank 8 is filled. In the vertical addressing mode (V = 1) the Y address increments after each byte. After the Y address (Y = 8), there is Y wraparound to 0 and X increments to address the next column (see Fig.6). After the very last address (X = 101 and Y = 8) the address pointers wraparound to address X = 0 and Y = 0 in both addressing modes. 2004 Mar 05 10 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver PCF8813 handbook, full pagewidth 0 1 2 102 103 104 204 205 206 306 307 308 408 409 410 510 511 512 612 613 614 714 715 716 816 817 818 918 919 0 Y address icons 0 X address 917 8 1019 10 101 MGU623 Fig.5 Sequence of writing data bytes into RAM with horizontal addressing (V = 0). handbook, full pagewidth 0 9 1 10 0 2 3 4 Y address 5 6 7 8 918 0 icons X address 917 8 1019 10 101 MGU624 Fig.6 Sequence of writing data bytes into the RAM with vertical addressing (V = 1). 2004 Mar 05 11 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver 7.10 PCF8813 Data order The Data Order bit (DO) defines the bit order (MSB on top or LSB on top) for writing in the RAM; see Figs 7 and 8. MSB handbook, full pagewidth LSB MSB MGW739 LSB Fig.7 Display data RAM byte organisation; DO = 1. LSB handbook, full pagewidth MSB LSB MGW738 MSB Fig.8 Display data RAM byte organisation; DO = 0. 2004 Mar 05 12 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver 7.11 PCF8813 Mirror X The MX bit allows horizontal mirroring. When MX = 1, the X address space is mirrored (see Fig.9). The address X = 0 is then located at the right side (column 101) of the display. When MX = 0, mirroring is disabled and the address X = 0 is located at the left side (column 0) of the display (see Fig.10). handbook, full pagewidth 0 8 10 101 X address 0 Y address MGU626 Fig.9 Display data RAM format addressing; MX = 1. handbook, full pagewidth 0 8 10 0 X address 101 Y address MGU625 Fig.10 Display data RAM format addressing; MX = 0. 2004 Mar 05 13 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver 7.12 PCF8813 Mirror Y The MY bit allows vertical mirroring. When MY = 1, the Y address space is mirrored resulting in an upside-down display. The address Y = 0 is then located at the bottom of the display (see Fig.11). When MY = 0, the mirroring is disabled and the address Y = 0 is located at top of the display (see Fig.12). A change in the state of MY has an immediate effect on the display and the effect of MY is visible immediately the bit is modified. This feature makes it possible to mount the device at the top or bottom of the display. handbook, full pagewidth 8 0 10 0 X address 101 Y address MGU628 Fig.11 Display data RAM format addressing; MY = 1. handbook, full pagewidth 0 8 10 0 X address 101 Y address MGU627 Fig.12 Display data RAM format addressing; MY = 0. 2004 Mar 05 14 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver 7.13 Bottom row swap the end for the icon data. When MY is set to 1, the RAM is still accessed in a linear manner but starting from the last row, counting down to zero and then jumping to the icon data. This mode swaps the order of the order of the rows; see Figs 13 and 14. The mode is useful to aide routing to displays when it is not possible to pass tracks under the device, as in the case of Tape Carrier Packages (TCP). 7.14 When N/P is set to 1, the Free Programmable Mux Rate (FPMR) mode is disabled and row addressing is in normal mode (see Section 11.9), therefore counting is the same as for MY = 0 and BRS = 0. When N/P is 0, FPMR mode is enabled. Only 65 rows are addressed/read in FPMR mode. Output row order The order in which the rows are activated is a function of bits Bottom Row Swap (BRS), Mirror Y (MY) and Normal Partial mode (N/P). This has important implications when the device is used either in COG or TCP applications. Figures 13 and 14 show the possibility of connecting the icon row (row R67) at the top or bottom of the display. When MY is set to 0, the RAM is accessed in a linear manner, starting at R0, counting to R66, then jumping to handbook, full pagewidth PCF8813 INTERFACE COLUMNS R67 R47 R32 R48 R63 R67 R31 R16 R0 R15 R67 R0 R15 R16 R31 R32 RAM R47 R48 R63 R66 R67 MGW793 Fig.13 Row order and interconnection with BRS = 0, MY = 0 and N/P = 1. 2004 Mar 05 15 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver handbook, full pagewidth PCF8813 INTERFACE R0 R1 R2 COLUMNS R67 R34 R19 R18 R3 R67 R35 R50 R51 R66 R67 R0 R34 R35 RAM R66 R67 MGW794 Fig.14 Row order and interconnection with BRS = 1, MY = 0 and N/P = 1. 2004 Mar 05 16 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver 8 9 PARALLEL INTERFACES 6800-type parallel interface The interface functions of the 6800-type parallel interface are shown in Table 2. Table 2 9.1 R/WR 0 0 command data write 0 1 read status register 1 0 display data write 1 1 none OPERATION 9.1.1 The 6800-type parallel interface can be configured to have the clock connected to the Enable input (E) with timing as shown in Fig.38, or with the clock connected to the chip select input (SCE) and the Enable (E) is tied HIGH with timing as shown in Fig.39. The PCF8813 is capable of detecting these different modes automatically. 8.2 Table 3 shows the interface functions of the 8080-type parallel interface. If SCE is pulled HIGH during a serial display data stream, the interrupted byte is invalid data but all previously transmitted data is valid. The next byte received will be handled as an instruction command (see Fig.18). 6800-type parallel interface function D/C RD WR 0 1 0 command data write 0 0 1 read status register 1 1 0 display data write 1 1 1 none 2004 Mar 05 WRITE MODE The display data/command indication may be controlled via software or by the D/C select input. When the D/C input is used, display data is transmitted when D/C is HIGH, and command data is transmitted when D/C is LOW (see Figs 15 and 16). When D/C is not used, the display data length instruction is used to indicate that a specific number of display data bytes (1 to 256) are to be transmitted (see Fig.17). The byte that follows the display data string is handled as an instruction command. 8080-type parallel interface Table 3 Serial peripheral interface The Serial Peripheral Interface (SPI) is a 3-line or 4-line interface for communication between the microcontroller and the LCD driver. The 3-line interface requires a chip enable input (SCE), serial clock (SCLK) and serial data (SDATA). For the 4-line serial interface, a separate D/C line is added. The PCF8813 is connected to the serial data I/O (SDATA) of the microcontroller via the pads data input (SDATA) and data output (SDOUT) connected together. 6800-type parallel interface function D/C SERIAL INTERFACES Communication with the microcontroller can also be via a clock-synchronized serial peripheral interface. It is possible to select two different 3-line interfaces (SPI and serial interface) or a 4-line serial interface (SPI). Selection of the interface is made with the inputs PS2, PS1 and PS0 (see Section 7.1). The parallel interface is an 8-bit bidirectional interface for communication between the microcontroller and the LCD driver chip. Two different parallel interfaces can be selected by the inputs PS2, PS1 and PS0. 8.1 PCF8813 OPERATION 17 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver PCF8813 handbook, full pagewidth SCE D/C SCLK SDATA DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 MGW744 Fig.15 Serial bus protocol; transmission of one byte. handbook, full pagewidth SCE D/C SCLK SDATA DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 MGW745 Fig.16 Serial bus protocol; transmission of several bytes. handbook, full pagewidth SCE SCLK SDATA DB7 DB6 DB5 DB4 DB2 DB1 DB0 data display length instruction and length data (two bytes) data last data DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 display data string Fig.17 Transmission of several bytes. 2004 Mar 05 18 instruction MGW746 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver PCF8813 handbook, full pagewidth SCE SCLK SDATA data data data data data data DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 MGW747 display data string instruction Fig.18 Transmission interrupted by SCE. 9.1.2 READ MODE The PCF8813 samples SDATA at rising SCLK edges, but shifts SDOUT data at falling SCLK edges. Thus the microcontroller reads SDOUT data at rising SCLK edges. The interface read mode means that the microcontroller reads data from the PCF8813. To do so the microcontroller first has to send a command, the read status command, and then the PCF8813 will respond by transmitting data on the SDOUT line. After that SCE is required to go HIGH before a new command is sent (see Fig.17). After the read status command has been sent, the SDATA line must be set to 3-state not later then at the falling SCLK edge of the last bit (see Fig.19). handbook, full pagewidth SCE RES SCLK SDATA DB7 DB6 DB5 DB4 DB3 DB2 SDO DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 instruction read out data Fig.19 SPI 3-line and 4-line read mode. 2004 Mar 05 19 MGU629 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver 9.2 PCF8813 Serial interface (3-line) transmission byte (1) handbook, full pagewidth D7 D/C D6 D5 D4 D3 D2 D1 MSB D/C D0 LSB transmission byte D/C transmission byte D/C transmission byte MGW713 (1) A transmission byte may be a command byte or a data byte. Fig.20 Serial data stream, write mode. The serial interface is also a 3-line bidirectional interface for communication between the microcontroller and the LCD driver chip. The three lines are: SCE (chip enable), SCLK (serial clock) and SDATA (serial data). The PCF8813 is connected to the SDA of the microcontroller by the SDATA (data input) and SDOUT (data output) pads which are connected together. 9.2.1 Figures 21, 22 and 23 show the protocol of the write mode: • When SCE is HIGH, SCLK clocks are ignored; the serial interface is initialized during the HIGH time of SCE (see Fig.21) • At the falling SCE edge SCLK must be LOW (see Fig.41) • SDATA is sampled at the rising edge of SCLK WRITE MODE • D/C indicates whether the byte is a command (D/C = 0) or RAM data (D/C = 1); it is sampled with the first rising SCLK edge In the write mode of the interface, the microcontroller writes commands and data to the PCF8813. Each data packet contains a control bit D/C and a transmission byte. If D/C is LOW, the following byte is interpreted as a command byte. If D/C is HIGH, the following byte is stored in the display data RAM. The address counter is incremented automatically after every data byte. Figure 20 shows the general format of the write mode and the definition of the transmission byte. • If SCE stays LOW after the last bit of a command/data byte, the serial interface is ready for the D/C-bit of the next byte at the next rising edge of SCLK (see Fig.22). • A reset pulse with RES interrupts the transmission and the data being written into the RAM may be corrupted. The registers are cleared. If SCE is LOW after the rising edge of RES, the serial interface is ready to receive the D/C-bit of a command/data byte (see Fig.23). Any instruction can be sent in any order to the PCF8813. The MSB of a byte is transmitted first. The serial interface is initialized when SCE is HIGH. In this state, SCLK clock pulses have no effect and no power is consumed by the serial interface. A falling edge on SCE enables the serial interface and indicates the start of data transmission. 2004 Mar 05 20 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver PCF8813 handbook, full pagewidth SCE SCLK SDATA D/C DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 MGU630 Fig.21 Serial interface (3-line), write mode - control bit followed by a transmission byte. handbook, full pagewidth SCE SCLK SDATA D/C DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 D/C DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 D/C transmission byte transmission byte MGU631 Fig.22 Serial interface (3-line), write mode - transmission of several bytes. handbook, full pagewidth SCE RES SCLK SDATA D/C DB7 DB6 DB5 DB4 D/C DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 D/C DB7 DB6 MGU632 Fig.23 Serial interface (3-line), write mode - interrupted by reset (RES). 2004 Mar 05 21 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver 9.2.2 PCF8813 READ MODE handbook, full pagewidth SCE SCLK SDATA D/C DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 SDOUT D/C DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 MGU633 Fig.24 Serial interface (3-line), read mode. In the read mode of the interface, that the microcontroller reads data from the PCF8813. To do this the microcontroller has first to send a command, then the read status command, and then the PCF8813 will respond by transmitting data on the SDOUT line. After that, SCE is required to go HIGH before a new command is sent (see Fig.24). After the read status command has been sent, the SDATA line must be set to 3-state not later than at the falling SCLK edge of the last bit. The 8th read bit is shorter than the others because it is terminated by the rising SCLK edge (see Fig.24). The last rising SCLK edge sets SDOUT to 3-state after a delay time (see time t4 in Fig.44). The PCF8813 samples the SDATA data at rising SCLK edges, but shifts SDOUT data at falling SCLK edges. Thus the microcontroller reads SDOUT data at rising SCLK edges. 2004 Mar 05 22 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver 10.1.1 10 I2C-BUS INTERFACE (Hs-MODE) 10.1 PCF8813 SYSTEM CONFIGURATION • Transmitter: the device that sends the data to the bus Characteristics of the I2C-bus (Hs-mode) • Receiver: the device that receives the data from the bus The I2C-bus Hs-mode is for bidirectional, two-line communication between different ICs or modules with speeds up to 3.4 MHz. The only difference between Hs-mode slave devices and Fast-mode slave devices is the speed at which they operate, therefore the buffers on the SLCH and SDAH outputs(1) have an open-drain. This is the same for I2C-bus master devices which have an open-drain SDAH output and a combination of open-drain pull-down and current source pull-up circuits on the SCLH output. Only the current source of one master is enabled at any one time, and only during Hs-mode. Both lines must be connected to a positive supply via a pull-up resistor. • Master: the device which initiates a transfer, generates clock signals and terminates a transfer • Slave: the device addressed by a master • Multi-master: more than one master can attempt to control the bus at the same time without corrupting the message • Arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to do so and the message is not corrupted • Synchronisation: procedure to synchronize the clock signals of two or more devices. Data transfer may be initiated only when the bus is not busy. (1) In Hs-mode, SCL and SDA lines operating at the higher frequency are referred to as SCLH and SDAH. MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER SDA SCL MGA807 Fig.25 System configuration. 10.1.2 BIT TRANSFER during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals. One data bit is transferred during each clock pulse (see Fig.26). The data on the SDAH line must remain stable handbook, full pagewidth SDA SCL data line stable; data valid change of data allowed Fig.26 Bit transfer. 2004 Mar 05 23 MBC621 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver 10.1.3 PCF8813 line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P). START AND STOP CONDITIONS Both data and clock lines remain HIGH when the bus is not busy (see Fig.27). A HIGH-to-LOW transition of the data handbook, full pagewidth SDA SDA SCL SCL S P START condition STOP condition MBC622 Fig.27 Definition of start and stop conditions. 10.1.4 ACKNOWLEDGE slave transmitter. The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Each byte of eight bits is followed by an acknowledge bit (see Fig.28). The acknowledge bit is a HIGH signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the handbook, full pagewidth DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER 1 2 8 9 S clock pulse for acknowledgement START condition MBC602 Fig.28 Acknowledge on the I2C-bus. 2004 Mar 05 24 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver 10.2 selected slave. After each acknowledge bit (A) or not-acknowledge bit (A) the active master disables its current-source pull-up circuit. The active master re-enables its current source again when all devices have released and the SCLH signal reaches a HIGH level. The rising of the SCLH is done by a resistor pull-up and so slower, the last part of the SCLH rise time is speeded up because the current-source is enabled. Data transfer only switches back to Fast-mode after a STOP condition (P). I2C-bus Hs-mode protocol The PCF8813 is a slave receiver/transmitter. If data is to be read from the device the SDAH pad must be connected, otherwise SDAHOUT may be unused. Hs-mode can only commence after the following conditions: • START condition (S) • 8-bit master code (00001XXX) A write sequence after the Hs-mode is selected is given in Fig.29. The sequence is initiated with a START condition (S) from the I2C-bus master which is followed by the slave address. All slaves with the corresponding address acknowledge in parallel, all the others will ignore the I2C-bus transfer. • Not-acknowledge bit (A). The master code has two functions, as shown in Figs 29 and 30, it allows arbitration and synchronization between competing masters at Fast-mode speeds, resulting in one winner. Also the master code indicates the beginning of an Hs-mode transfer. After acknowledgement of a write (W) cycle, one or more command words follow which define the status of the addressed slaves. A command word consists of a control byte, which defines CO and D/C, plus a data byte (see Fig.31 and Table 4). As no device is allowed to acknowledge the master code, the master code is followed by a not-acknowledge (A). After this A-bit, and the SCLH line has been pulled up to a HIGH level, the active master switches to Hs-mode and enables at tH the current-source pull-up circuit for the SCLH signal (see Fig.30). The last control byte is tagged with a cleared most significant bit, the continuation bit Co. The control and data bytes are also acknowledged by all addressed slaves on the bus. The active master will then send a repeated START condition (Sr) followed by a 7-bit slave address with a R/W-bit, and receives an acknowledge bit (A) from the Table 4 CO and D/C definition BIT 0/1 R/W CO 0 N/A 1 D/C PCF8813 0 1 ACTION last control byte to be sent; only a stream of data bytes are allowed to follow; this stream may only be terminated by a STOP or RE-START condition another control byte will follow the data byte unless a STOP or RE-START condition is received 0 data byte will be decoded and used to set-up the device 1 data byte will return the status byte 0 data byte will be stored in the display RAM 1 RAM read back is not supported After the last control byte, depending on the D/C bit setting, a series of display data bytes or command data bytes may follow. If the D/C-bit was set to logic 1, these display bytes are stored in the display RAM at the address specified by the data pointer. The data pointer is updated automatically and the data is directed to the intended PCF8813. If the D/C-bit of the last control byte was set to logic 0, these command bytes will be decoded and the setting of the device will be changed according to the received commands. The acknowledgement after each byte is made only by the addressed PCF8813. At the end of the transmission the I2C-bus master issues a STOP 2004 Mar 05 condition (P) and switches back to Fast-mode, however, to reduce the overhead of the master code, its possible that a master links a number of Hs-mode transfers, separated by repeated START conditions (Sr). A read sequence (see Fig.32) follows after the Hs-mode is selected. The PCF8813 will immediately start to output the requested data until a NOT acknowledge is transmitted by the master. Before the read access, the user has to set the D/C-bit to the appropriate value by a preceding write access. The write access should be terminated by a RE-START condition so that the HS-mode is not disabled. 25 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver PCF8813 ,,,,, ,,,,, ,,,,,,,,,, handbook, full pagewidth Hs-mode (current-source for SCLH enabled) F/S-mode S MASTER CODE A Sr SLAVE ADD. R/W A DATA ,, ,, ,,,, ,,,, F/S-mode A/A P (n bytes + ack.) Hs-mode continues Sr SLAVE ADD. MSC616 Fig.29 Data transfer format in Hs-mode. 8-bit Master code 00001xxx S A t1 tH SDAH SCLH 1 6 2 to 5 7 8 9 Fs mode R/W 7-bit SLA Sr n × (8-bit DATA A + A/A) Sr P SDAH SCLH 1 2 to 5 6 7 8 9 1 2 to 5 6 7 8 9 If P then Fs mode Hs-mode If Sr (dotted lines) then Hs mode tH tFS = MCS current source pull-up = Rp resistor pull-up Fig.30 Complete data transfer in Hs-mode. 2004 Mar 05 26 MSC618 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver acknowledge from PCF8813 acknowledge from PCF8813 handbook, full pagewidth S S Sr 0 1 1 1 1 A A 0 A 1 D/C 1 0 slave address PCF8813 control byte A acknowledge from PCF8813 data byte 2n ≥ 0 bytes R/W CO A 0 D/C acknowledge from PCF8813 control byte 1 byte CO A acknowledge from PCF8813 A P data byte n ≥ 0 bytes MSB . . . . . . . . . . . LSB MGU634 Fig.31 Master transmits in Hs-mode to slave receiver; write mode. acknowledgement from PCF8813 handbook, full pagewidth S S Sr 0 1 1 1 1 A A 1 A 1 0 NOT acknowledgement from Master status information A P slave address R/W STOP condition MGU635 Fig.32 Master receives from slave transmitter (status register is read); read mode. 10.3 Command decoder The most significant bit of a control byte is the continuation bit CO. If this bit is logic 1, it indicates that only one data byte, either command or RAM data, will follow. If the bit is logic 0, it indicates that a series of data bytes, either command or RAM data, may follow. The DB6 bit of a control byte is the RAM data/command bit D/C. When this bit is logic 1, it indicates that a RAM data byte will be transferred next. If the bit is at logic 0, it indicates that a command byte will be transferred next. The command decoder identifies command words that arrive on the I2C-bus. • Pairs of bytes – first byte determines whether information is display or instruction data – second byte contains information. • Stream of information bytes after CO = 0; display or instruction data depending on last D/C-bit. 2004 Mar 05 27 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver 11 INSTRUCTIONS PCF8813 operating mode of the device and those that fill the display RAM is made respectively by the display data length instruction (4-line SPI) or by D/C bit in the data stream (3-line serial interface and I2C-bus interface). The PCF8813 interfaces via the 8-bit parallel interface, two different 3-line serial interfaces, 4-wire serial interface or an I2C-bus interface. Processing of the instructions does not require the display clock. There are four types of instructions: • Defining PCF8813 functions such as display configuration, etc. In the case of the parallel and 4-wire serial interface, data accesses to the PCF8813 can be divided into two areas; those that define the operating mode of the device, and those that fill the display RAM; the distinction being the D/C input. When the D/C input is set to logic 0, the chip will respond to instructions as defined in Table 5. When the D/C bit is at logic 1, the chip will send data into the RAM. • Setting internal RAM addresses • Performing data transfer with internal RAM • Other instructions. In normal use, category 3 instructions are used most frequently. To lessen the MPU program load, automatic incrementing by one of the internal RAM address pointers after each data write is implemented. When the 3-wire serial interface or the I2C-bus interface is used, the distinction between instructions that define the Table 5 Instruction set Instructions not expressly defined in this table and reserved instructions are not allowed in PCF8813 applications. COMMAND BYTE INSTRUCTION D/C R/W DB7 (MSB) DB6 DB5 DB4 DB3 DB2 DB1 DB0 (LSB) DESCRIPTION H = 0 or 1 NOP 0 0 0 0 0 0 0 0 0 0 no operation Function set 0 0 0 0 1 MX MY PD V H Power-down control; entry mode Read status byte 0 1 0 0 0 1 1 0 δ(1) δ(1) read status byte for serial and I2C-bus interfaces Read status byte 0 1 BUSY DON RES MF2 MF1 MF0 DS1 DS0 reads parallel interface status byte Write data 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Reserved 0 0 0 0 0 0 0 1 X X do not use Display control 0 0 0 0 0 0 1 D 0 E sets display configuration Set lower/higher program range 0 0 0 0 0 1 0 0 0 PRS Set power control HVgen on/off 0 0 0 0 0 1 0 0 1 PC switch HVgen on/off Display configuration 0 0 0 0 0 1 0 1 1 δ(1) 0 0 0 0 0 0 0 D0 0 BRS double command byte: set data order; top/bottom row swap mode writes data to RAM H=0 2004 Mar 05 28 VLCD programming range Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver PCF8813 COMMAND BYTE INSTRUCTION D/C R/W DB7 (MSB) DB5 DB4 DB3 DB2 DB1 DB0 (LSB) DESCRIPTION DB6 double command byte; set display data length, only used in 3-line SPI Set display data length 0 0 0 1 1 1 δ(1) δ(1) δ(1) δ(1) 0 0 0 D6 D5 D4 D3 D2 D1 D0 Set Y address of RAM 0 0 0 1 0 0 Y3 Y2 Y1 Y0 Set maximum Y address 0 0 0 1 0 1 δ(1) δ(1) δ(1) δ(1) 0 0 0 0 0 0 Set maximum X address 0 0 0 1 1 0 0 0 0 Set X address of RAM 0 0 1 X6 X5 X4 X3 X2 X1 X0 Reserved 0 0 0 0 0 0 0 0 0 1 Reserved 0 0 0 0 0 0 0 0 1 X Temperature compensation 0 0 0 0 0 0 0 1 TC1 TC0 set temperature coefficient (TCx) Set HVgen stages 0 0 0 0 0 0 1 0 S1 S0 set multiplication factor Bias system 0 0 0 0 0 1 0 BS2 BS1 BS0 set bias system (BSx) Reserved 0 0 0 1 1 0 0 δ(1) δ(1) δ(1) δ(1) δ(1) δ(1) double command byte: do not use Ymax3 Ymax2 Ymax1 δ(1) δ(1) δ(1) Xmax6 Xmax5 Xmax4 Xmax3 Xmax2 Xmax1 sets Y address of RAM: 0 ≤ Y ≤ 9 double command Ymax0 byte: set maximum Y: 0 ≤ Y ≤ 8 δ(1) Xmax0 double command byte: set maximum X: 0 ≤ Y ≤ 101 sets X address of RAM: 0 ≤ X ≤ 101 H=1 0 0 0 0 0 0 δ(1) Normal or partial display mode 0 0 0 1 0 1 0 δ(1) δ(1) δ(1) 0 0 0 0 0 0 0 0 0 N/P Free programmable MUX rate 0 0 0 1 1 0 1 δ(1) δ(1) δ(1) 0 0 M7 M6 M5 M4 M3 M2 M1 M0 Set initial row to be displayed 0 0 0 1 0 0 1 δ(1) δ(1) δ(1) 0 0 0 C6 C5 C4 C3 C2 C1 C0 Set RAM line address for initial row 0 0 0 1 0 1 1 δ(1) δ(1) δ(1) 0 0 0 L6 L5 L4 L3 L2 L1 L0 2004 Mar 05 29 double command byte: set normal or partial display mode double command byte: set mask register for FPMR mode (1 : 9, 17, and 25 to 64) double command byte: set start row 0 ≤ X ≤ 66 double command byte; sets RAM line address to be displayed 0 ≤ L ≤ 66 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver PCF8813 COMMAND BYTE INSTRUCTION D/C R/W DB7 (MSB) DB6 DB5 DB4 DB3 DB2 DB1 DB0 (LSB) DESCRIPTION Disable OTP circuitry 0 0 0 0 0 1 1 1 0 0 disable OTP circuitry Enter module maker calibration mode 0 0 0 0 0 1 1 1 1 0 module maker calibration Software reset 0 0 0 1 1 1 0 0 0 1 enable software reset Set VPR 0 0 1 VPR6 VPR5 VPR4 VPR3 VPR2 VPR1 VPR0 write VPR to register Note 1. δ = don’t care. Table 6 Explanation of mnemonics used in Table 5 BIT 0 1 RESET STATE PD chip active chip is in Power-down mode 1 H basic command set extended command set 0 V horizontal addressing vertical addressing 0 PC power control off power control on 1 MX normal X addressing X address is mirrored 0 MY display is not vertically mirrored display is vertically mirrored 0 TRS top rows are not mirrored top rows are mirrored 0 BRS bottom rows are not mirrored bottom rows are mirrored 0 DO LSB is on top MSB is on top 1 PRS VLCD programming range LOW VLCD programming range HIGH 0 N/P partial display driving mode normal display driving mode 1 C[6:0] sets the initial R0 of the display.; this command cannot access R67 (icon row) 0000000 L[6:0] sets the line address of the display RAM to be displayed on the initial R0; this command cannot access R67 0000000 Ymax[3:0] sets maximum Y address for wraparound Xmax[6:0] sets the maximum X address 1000 1100101 D, E display control; see Table 8 00 TC[1:0] set temperature coefficient; see Table 9 00 S[1:0] set voltage multiplication factor; see Table 10 00 BS[2:0] bias system VPR[6:0] VLCD programming 0000000 M[7:0] set partial display (full display = 11111111) 11111111 2004 Mar 05 000 30 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver Table 7 PCF8813 Read status byte BIT FUNCTION BUSY 0 = chip is able to accept new commands; 1 = chip is unable to accept new commands DON 0 = display OFF; 1 = display ON RES 0 = reset NOT in progress; 1 = reset in progress MF[2:0] manufacturer identification bits DS[1:0] device recognition; currently has a fixed value of 00 (recognition bits for a driver with 64 to 67 rows) Table 8 Display control; bits D and E 11.2 D E After reset the LCD driver has the following state: 0 0 display blank • Power-down mode (PD = 1) 1 0 normal mode • Horizontal addressing (V = 0) 0 1 all display segments on • Normal instruction set (H = 0) 1 1 inverse video mode • Display blank (D and E = 00) FUNCTION Reset function • Address counter X[6:0] = 0000000 and Y[3:0] = 0000 Table 9 Set temperature coefficient; bits TC[1:0] • Temperature control mode TC[1:0] = 00 • VLCD is equal to 0 and PRS = 0 TC1 TC0 FUNCTION 0 0 VLCD temperature coefficient 0 0 1 VLCD temperature coefficient 1 • Normal row driving of display (N/P = 1) 1 0 VLCD temperature coefficient 2 1 1 VLCD temperature coefficient 3 • Partial mode set for all rows available (M[7:0] = 11111111) • Power control is enabled (PC = 1) • HV generator programmed off (VPR[6:0] = 0000000) Table 10 Set voltage multiplication factor; bits S[1:0] • 2 × voltage multiplier (S[1:0] = 00) S1 S0 0 0 2 × voltage multiplier • After power-on, RAM data is undefined, the reset signal does not change the content of the RAM 0 1 3 × voltage multiplier • Data order DO = 0 1 0 4 × voltage multiplier • All LCD outputs at VSS (display off) 1 1 5 × voltage multiplier • Bias system (BS[2:0] = 000 FUNCTION • Display start line set to R0 (C[6:0] = 000000) 11.1 Initialization • RAM line address set to 0 (L[6:0] = 000000) Immediately following Power-on, all internal registers as well as the RAM content are undefined. A RES pulse must be applied to the reset input. • Maximum X address = 101 (Xmax[6:0] = 1100101) • Maximum Y address = 8 (Ymax[3:0] = 1000) • Display is not mirrored (MX = 0; MY = 0 and BRS = 0). Reset is accomplished by applying an external reset pulse (active LOW) at the pad RES. When reset occurs within the specified time all internal registers are reset, however the RAM is still undefined. The RES input must be ≤0.3VDD when VDD reaches VDD(min) (or higher) within a maximum time tVHRL after VDD going HIGH (see Fig.37). 11.3 Power-down mode Power-down mode gives the following circuit status: • VLCD discharges to VSS as Power-down mode occurs • All LCD outputs go to VSS (display off) A reset can also be made by sending a reset command. This command can be used during normal operating but not to initialize the chip after Power-on. • Bias generator and VLCD generator switch-off, VLCD can be disconnected • Oscillator switches off (external clock is possible) • RAM contents are not cleared; RAM data can be written. 2004 Mar 05 31 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver 11.4 11.7 Display Control When bit MX = 0, the display RAM is written from left to right (X = 0 is on the left side and X = 101 is on the right side of the display). When bit MX = 1, the display RAM is written from right to left (X = 0 is on the right side and X = 101 is on the left side of the display). The bit MX has an impact on the way the RAM is written. So if horizontal mirroring of the display is required, the RAM must first be rewritten. 11.8 When bit MY = 1, the display is mirrored vertically. A change of bit MY has an immediate effect on the display. Set Y address of RAM Bits Y[3:0] define the Y address vector address of the display RAM. Figure 33 shows an example of how RAM data is mapped onto the display. In this example, the L command sets the data on line 8 of the RAM to be displayed. This data is displayed on a row set by the C command (16). When L and C are set to 8 and 16 respectively, data from RAM lines 4 to 7 is displayed on display rows 12 to 15 and RAM data from lines 15 to 18 is displayed on display lines 23 to 26. Table 11 Range of Y address and allowable X range RAM CONTENT Set display start line, initial start row and row 0 Set display start line L[6:0] allows the display line address of the display RAM to be chosen. The range is from line 0 to line 66 inclusive. The RAM address line 67 is not available for this command as it is reserved for icons. This command has an effect on the mapping between the data of the RAM and the display. The L address specifies which rows of the RAM are output to which row outputs of the display. The value of the L address defines which row of the RAM will be row 0. Row 0 of the display can in turn be set by the set initial row command C[6:0]. When bit V = 0, horizontal addressing is selected and data is written into the DDRAM as shown in Fig.5. When bit V = 1, vertical addressing is selected, then data is written into the DDRAM as shown in Fig.6. Y ADDRESS Set maximum X address or Y address These two commands (Xmax[6:0] and Ymax[3:0]) set the maximum address for wraparound to occur for the columns. The range of Xmax is 0 to 101. The maximum Y address also sets the Y address for wraparound to occur. The range of Ymax is 0 to 8. By design, the maximum Y setting cannot access bank 10. Xmax and Ymax together also define when wraparound-to-zero takes place. These two commands are effective only when writing to the RAM. Bits D and E (see Table 8) select the display mode. 11.5 PCF8813 ALLOWED X RANGE 3 2 1 0 0 0 0 0 bank 0 (display RAM) 0 to 101 0 0 0 1 bank 1 (display RAM) 0 to 101 0 0 1 0 bank 2 (display RAM) 0 to 101 0 0 1 1 bank 3 (display RAM) 0 to 101 0 1 0 0 bank 4 (display RAM) 0 to 101 0 1 0 1 bank 5 (display RAM) 0 to 101 0 1 1 0 bank 6 (display RAM) 0 to 101 11.9 0 1 1 1 bank 7 (display RAM) 0 to 101 1 0 0 0 bank 8 (display RAM) 0 to 101 1 0 1 0 bank 10 (display RAM) 0 to 101 When N/P = 1, the PCF8813 can operate only as a 67 + 1 row driver operating with a 1 : 68 multiplex rate. When N/P = 0, the driver is used in free programmable multiplex rate where up to eight different multiplex rates can be selected in steps of 8, depending on the mask register value M[7:0]. When the PCF8813 is operating in FPMR mode, only the first 64 rows plus the icon row are available to the user. When MY is active (MY = 1), the data from Fig.33 is mapped from the RAM to the display as shown in Fig.34. Note the ‘new’ location of C after MY. In bank 8 only three bits are accessed, and in bank 10 only one bit is accessed. 11.6 Set normal or partial display mode Set X address of RAM Table 12 Normal or partial mode display The X address points to the columns. The range of X is 0 to 101 (65H). 2004 Mar 05 N/P 32 ACTION 0 partial mode display: 65 rows available 1 normal mode display: 68 rows available Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver 11.10 Free programmable multiplex rate PCF8813 Rows 8 to 15 and 32 to 63 have been skipped. This information is also mapped to the RAM so that only the contents of active rows are displayed. The free programmable multiplex rate concept allows the user to limit the number of rows selected to groups of eight. Any, or all of these groups of rows can be enabled or disabled. The mask register command (M[7:0]) allows the user to turn-on or turn-off blocks of eight rows. Table 13 Range of free programmable multiplex rates MASK REGISTER Each mask value controls a block of eight rows, thus in partial mode the maximum number of rows available is 64 plus the icon row. A logic 1 in the mask register enables the rows available within that block of rows, and a logic 0 disables them. The mask register causes the row counter to count eight bits and then jump to the next enabled 8-bit group. For example, if the mask register value is 00001101, then the rows available will be 0 to 7, 16 to 23, 24 to 31 and 67. ROWS AVAILABLE M0 R0 to R7 + icon row M1 R8 to R15 + icon row M2 R16 to R23 + icon row M3 R24 to R31 + icon row M4 R32 to R39 + icon row M5 R40 to R47 + icon row M6 R48 to R55 + icon row M7 R56 to R63 + icon row Table 14 Examples of display normal driving mode and partial display driving mode MASK REGISTER MASK VALUE ROW SEQUENCE NORMAL DISPLAY N/P = 1 (the mask value is don’t care when N/P = 1 because all rows are enabled) M0 1 0 to 7 battery status: XXX M1 M2 0 8 to 15 address book 0 16 to 23 connection time M3 1 24 to 31 network: YYY M4 0 32 to 39 reception strength M5 0 40 to 47 2 June; 15:25 M6 0 48 to 55 M7 1 56 to 63 not available in mask register 64 to 66 not available in mask register 67 (icon row) keyboard locked N/P = 0 M0 1 0 to 7 M1 0 8 to 15 M2 0 16 to 23 M3 1 24 to 31 M4 0 32 to 39 M5 0 40 to 47 M6 0 48 to 55 M7 1 56 to 63 not available in mask register 2004 Mar 05 67 (icon row) 33 battery status: XXX network: YYY keyboard locked Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver set initial display line and start row when MY = 0 handbook, full pagewidth RAM Y address Display 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 L-address = 8 C-address = 16 56 57 58 59 60 61 62 63 64 65 66 67 7 8 9 PCF8813 icons only ROW 0 ROW 1 ROW 2 ROW 3 ROW 4 ROW 5 ROW 6 ROW 7 ROW 8 ROW 9 ROW 10 ROW 11 ROW 12 ROW 13 ROW 14 ROW 15 ROW 16 ROW 17 ROW 18 ROW 19 ROW 20 ROW 21 ROW 22 ROW 23 ROW 24 ROW 25 ROW 26 ROW 27 ROW 28 ROW 29 ROW 30 ROW 31 ROW 32 ROW 33 ROW 34 ROW 35 ROW 36 ROW 37 ROW 38 ROW 39 ROW 64 ROW 65 ROW 66 ROW 67 icons only MGU636 Fig.33 Effect of L address when MY = 0. 2004 Mar 05 34 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver set initial display line and start row when MY = 1 handbook, full pagewidth RAM Y address Display 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 ROW 0 ROW 1 ROW 2 ROW 3 L-address = 8 effective C-address 56 57 58 59 60 61 62 63 64 65 66 67 7 8 9 PCF8813 icons only ROW 17 ROW 18 ROW 19 ROW 20 ROW 21 ROW 22 ROW 23 ROW 24 ROW 25 ROW 26 ROW 27 ROW 28 ROW 29 ROW 30 ROW 41 ROW 42 ROW 43 ROW 44 ROW 45 ROW 46 ROW 47 ROW 48 ROW 49 ROW 50 ROW 51 ROW 52 ROW 53 ROW 54 ROW 55 ROW 56 ROW 57 ROW 58 ROW 59 ROW 60 ROW 61 ROW 62 ROW 63 ROW 64 ROW 65 ROW 66 ROW 67 icons only MGU637 Fig.34 Effect of L address when MY = 1. 2004 Mar 05 35 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver PCF8813 Table 16 LCD bias voltage 11.11 Set HV generator stages The PCF8813 incorporates a software-configurable voltage multiplier. After reset (RES) the voltage multiplier is set to 2 × VDD2. Other voltage multiplier factors are set via the set HVgen stages command bits S[1:0]. SYMBOL 11.12 Bias system The bias voltage levels are set in the ratio of R - R - nR - R - R giving a 1/(n + 4) bias system. Different multiplex rates require different n factors. This is programmed by BS[2:0] (see Table 15). 68 – 3 = 5.246 = 5 resulting in 1/9 bias. V2 (n + 3) ----------------(n + 4) 8/ 9 × VLCD V3 (n + 2) ----------------(n + 4) 7/ 9 × VLCD V4(1) 2 ----------------(n + 4) 2/ 9 × VLCD V5(2) 1 ----------------(n + 4) 1/ 9 × VLCD Notes Table 15 Bias system programming 2. n VLCD VLCD Changing the bias system from the optimum value will have a consequence for the contrast and viewing angle. One reason to depart from the optimum would be to reduce the required operating voltage. A compromise between contrast and operating voltage must be found for any particular application. BS[2] BS[1] BS[0] BIAS VOLTAGES FOR 1/9 BIAS V1 For multiplex rates of 1 : 68 the optimum bias value n is given by: n = BIAS VOLTAGES V6 VSS VSS 1. Operation of bias level V4 is given for V4 > VSS + 0.9 V. For higher multiplex rates, VLCD has to be selected accordingly. RECOMMENDED MULTIPLEX RATES For multiplex rates equal to or lower than 1 : 24 (n = 2) operation of the bias level V5 is limited to voltages V5 < VDD2,3 − 1.1 V. VLCD has to be selected accordingly. 0 0 0 7 1 : 100 0 0 1 6 1 : 80 0 1 0 5 1 : 65 or 1 : 67 0 1 1 4 1 : 48 1 0 0 3 1 : 34 or 1 : 40 The operating voltage can be set by software through the interface. The binary number VOP representing the operating voltage can be set according to the following formula: 1 0 1 2 1 : 24 V OP = V CAL [ 4:0 ] + V PR∗ 1 1 0 1 1 : 18 or 1 : 16 1 1 1 0 1 : 10, 1 : 9 or 1 : 8 Where: VOP is an 8-bit unsigned number used internally for generation of the LCD supply voltage VLCD VCAL is a 5-bit twos complement number set by the module maker; see Table 17 VPR is an 8-bit unsigned number composed of PRS and VPR* set by an interface command. The corresponding voltage at the reference temperature, TCUT, can be calculated as: V LCD ( Tcut ) = ( a + V OP × b ) 2004 Mar 05 36 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver The generated voltage at VLCD is dependent on the temperature, programmed temperature coefficient (TC) and the programmed voltage at the reference temperature (TCUT): PCF8813 register and selecting the temperature compensation, under all conditions and including all tolerances the VLCD maximum limit of 9.0 V will never be exceeded. For a particular liquid crystal, the optimum VLCD can be calculated for a given multiplex rate. For 1 : 68, the optimum operating voltage of the liquid crystal can be calculated as; V LCD = [ a + V OP × b ] × [ 1 + TC × ( T – T CUT ) ] TCUT and voltages a and b for each temperature coefficient are quoted in Table 17. The maximum voltage that can be generated is dependent on the voltage of VDD2 and the display load current. 1 + 68 V LCD = --------------------------------------- × V th = 6.98 × V th 1 2 × 1 – ---------- 68 As the programming range for the internally generated VLCD allows values above the maximum allowed VLCD, the user must ensure that while setting the VPR where Vth is the threshold voltage of the liquid crystal used. Table 17 Parameters of HV generator programming (typical values) Nominal temperature = 27 °C; temperature coefficients calculated at nominal VLCD = 8.6 V. SYMBOL PARAMETER TC0 TC1 TC2 TC3 UNIT a first level VLCD voltage 4.57 4.27 4.01 3.84 V b programmed voltage step 30.5 28.5 26.7 25.6 mV TCUT reference temperature 27 27 27 27 °C TC temperature coefficient 0.00 −0.25 −0.48 −0.64 mV/K handbook, full pagewidth MGT847 V LCD b a 00 01 02 03 04 05 06 ... ... If VPR[6:0] is set to zero, the charge pump is turned off. Depending on VPR restrictions defined in Table 17 and depending on VCAL, not all VOP[7:0] values can be selected. Fig.35 VLCD as a function of VOP[7:0] programming. 2004 Mar 05 37 FD FE FF V OP Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver PCF8813 12 TEMPERATURE COMPENSATION Due to the temperature dependency of the liquid crystal viscosity, the LCD controlling voltage VLCD must be increased at lower temperatures to maintain optimum contrast. Figure 36 shows VLCD for high multiplex rates. In the PCF8813 the temperature coefficient to be applied to VLCD can be selected from four values by setting bits TC[1:0]. handbook, full pagewidth MGT848 VLCD T Fig.36 VLCD as a function of liquid crystal temperature. 13 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); see notes 1 and 2 SYMBOL PARAMETER MIN. MAX. UNIT VDD1 supply voltage −0.5 +6.5 V VDD2, VDD3 supply voltage (voltage multiplier); see note 3 −0.5 +4.5 V VLCD LCD supply voltage −0.5 +9.0 V VI input voltage (any pad) −0.5 VDD + 0.5 V ISS ground supply current −50 +50 mA II, IO DC input or output current −10 +10 mA Ptot total power dissipation − 300 mW PO power dissipation per output − 30 mW Tstg storage temperature −65 +150 °C Tj junction temperature − 150 °C Notes 1. Stresses above those listed under limiting values may cause permanent damage to the device. 2. Parameters are valid over operating temperature range unless otherwise specified; all voltages are with respect to VSS unless otherwise specified. 3. VDD2 and VDD3 are always equal. 14 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices (see “Handling MOS devices”). 2004 Mar 05 38 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver PCF8813 15 DC CHARACTERISTICS VDD1 = 1.7 to 3.3 V; VSS = 0 V; VLCD = 3.0 to 9.0 V; Tamb = −40 to +85 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT 1.7 − 3.3 V 2.4 − 4.5 V 3.0 − 9.0 V note 2 4.5 − 9.0 V note 3 −70 − +70 mV 100 300 µA VDD1 supply voltage (logic circuits) VDD2, VDD3 supply voltage (voltage multiplier) VLCDIN LCD supply voltage input VLCDOUT generated LCD supply voltage VLCD(tol) tolerance of generated LCD supply voltage IDD(tot) total supply current (IDD1 + IDD2 + IDD3) normal mode; notes 4, 5, 6 − − 0.5 10 µA IDD1 supply current external VLCD; notes 4, 6, 8 − 10 35 µA ILCD LCD supply current external VLCD; notes 4, 6, 8 − 30 − µA note 1 Power-down mode; note 7 Logic circuits VOL LOW-level output voltage IOL = 0.5 mA VSS − 0.2VDD V VOH HIGH-level output voltage IOH = −0.5 mA 0.8VDD − VDD V VIL LOW-level input voltage VSS − 0.2VDD V VIH HIGH-level input voltage 0.8VDD − VDD V IL leakage current VI = VDD or VSS −1 − +1 µA VLCD = 7.6 V; note 9 − 5 20 kΩ Column and row outputs Rcol column output resistance C0 to C101 Rrow row output resistance R0 to R67 VLCD = 7.6 V; note 9 − 5 20 kΩ Vcol(tol) bias tolerance C0 to C101 note 9 −100 0 +100 mV Vrow(tol) bias tolerance R0 to R67 note 9 −100 0 +100 mV temperature coefficient 0 − 0.00 − mV/K temperature coefficient 1 − −0.23 − mV/K temperature coefficient 2 − −0.48 − mV/K temperature coefficient 3 − −0.64 − mV/K LCD supply voltage generator TC VLCD temperature compensation VLCD(nom) = 8.6 V Notes 1. VDD2 and VDD3 are always equal. 2. The maximum possible VLCD voltage that may be generated depends on voltage, temperature and load (display). 3. Valid for the temperature, VPR and TC values used at calibration. 4. Normal mode and internal clock. 5. Conditions: VDD1 = 1.8 V; VDD2 = 2.70 V; VLCD = 7.6 V; voltage multiplier = 4 × VDD2; bias system 1/9; inputs at VDD1 or VSS; VLCD generation = internal; VLCD output loaded by 10 µA; Tamb = 25 °C. 6. fINTCLK = 0 (no data bus clock). 7. Power-down mode; during Power-down all static currents are switched off. 2004 Mar 05 39 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver PCF8813 8. VLCD external voltage applied to VLCDIN and VLCDSENSE inputs; VLCDOUT disconnected; VPR and PC set to 0 (charge pump off); display load current is not transmitted to IDD. 9. Load current = 10 µA; outputs tested one at a time. 16 AC CHARACTERISTICS VDD1 = 1.7 to 3.3 V; VSS = 0 V; VLCD = 3.0 to 9.0 V; Tamb = −40 to +85 °C; all timings specified are based on 20% to 80% of VDD with an input voltage swing of VSS to VDD; unless otherwise specified. SYMBOL PARAMETER CONDITIONS fext external clock frequency note 1 fframe frame frequency internal oscillator MIN. TYP. MAX. UNIT 20 38 65 kHz note 2 56 66 76 Hz note 3 62 69 76 Hz tVHRL VDD on to RES LOW time see Fig.37 0(4) − 1 µs tRW reset pulse width LOW time see Fig.37 500 − − ns tR(oper) end of reset pulse to interface operational see Fig.37 1000 − − ns 6800-type parallel bus; VDD1 = 1.8 to 3.3 V; see Figs 38 and 39 tDCSU data/command set-up time 0 − 25 ns tDCHD data/command hold time 0 − − ns TDS(cyc) data strobe cycle time 1000 − − ns tDSL data strobe LOW time 300 − − ns tDSH data strobe HIGH time 300 − − ns tRWSU read/write set-up time 0 − − ns tRWHD read/write hold time 0 − − ns tESU chip enable set-up time 0 − − ns tEHD chip enable hold time 0 − − ns tDATSU data set-up time 80 − − ns tDATHD data hold time 30 − − ns tDATACC output access time − − 280 ns tDATOH output disable time 10 − 200 ns − 25 ns 8080-type parallel bus; VDD1 = 1.8 to 3.3 V; see Fig.40 tDCSU data/command set-up time 0 tDCHD data/command hold time 0 − − ns TDS(cyc) data strobe cycle time 1000 − − ns tDSLR data strobe LOW time (read) 120 − − ns tDSLW data strobe LOW time (write) 240 − − ns tDSHR data strobe HIGH time (read) 120 − − ns tDSHW data strobe HIGH time (write) 120 − − ns tDATSU data set-up time 80 − − ns tDATHD data hold time 30 − − ns tDATACC output access time − − 280 ns tDATOH output disable time 10 − 200 ns 2004 Mar 05 40 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver SYMBOL PARAMETER PCF8813 CONDITIONS MIN. TYP. MAX. UNIT 3-line and 4-line SPI and serial interface; VDD1 = 1.8 to 3.3 V; Figs 41 to 44; note 5 fSCLK SCLK frequency − − 9 MHz Tcyc SCLK cycle time 111 − − ns tPWH1 SCLK pulse width HIGH 45 − − ns tPWL1 SCLK pulse width LOW 45 − − ns tPWH2 SCE minimum HIGH time 50 − − ns tS1 SDATA set-up time 50 − − ns tH1 SDATA hold time 50 − − ns tS2 SCE set-up time 60 − − ns tH2 SCE hold time 45 − − ns tS3 data/command set-up time 50 − − ns tH3 data/command hold time 50 − − ns t1 SDOUT access time − − 80 ns t2 SDOUT disable time note 6 − − 80 ns t3 SCE hold time 50 − − ns t4 SDOUT disable time note 7 − − 80 ns Cb capacitive load for SDOUT note 8 − − 30 pF Rb series resistance for SDOUT note 8 − − 500 Ω I2C-bus interface in Fast-mode; VDD1 = 1.7 to 3.3 V; Fig.45 fSCL SCL clock frequency 0 − 400 kHz tLOW SCL clock low period 1.3 − − µs tHIGH SCL clock high period 0.6 − − µs tSU;DAT data set-up time 100 − − ns tHD;DAT data hold time 0 − 0.9 µs cb capacitive load represented by each bus line − − 400 pF tSU;STA set-up time for a repeated START condition 0.6 − − µs tHD;STA START condition hold time 0.6 − − µs tSU;STO set-up time for STOP condition 0.6 − − µs tSP tolerable spike width on bus − − 50 ns I2C-bus note 9 interface in Hs-mode; VDD1 = 1.7 to 3.3 V; Fig.46 fSCLH SCLH clock frequency 0 − 3.4 MHz tSU;STA set-up time (repeated) START condition 160 - − ns tHD;STA hold time (repeated) START condition 160 − − ns tLOW LOW period of the SCLH clock 160 − − ns tHIGH HIGH period of the SCLH clock 60 − − ns tSU;DAT data set-up time 10 − − ns 2004 Mar 05 41 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver SYMBOL PARAMETER PCF8813 CONDITIONS tHD;DAT data hold time tSU;STO set-up time for STOP condition Cb capacitive load for SDAH and SCLH lines 0 total capacitance of one bus line capacitive load for SDAH + SDA line and SCLH + SCL line tSP MIN. tolerable spike width on bus note 9 TYP. − MAX. UNIT 70 ns 160 − − ns − − 100 pF − − 400 pF − − 5 ns Notes f ext 1. fframe = ------- : (n depends on the multiplex rate, see Table 18). n 2. VDD1 = 1.7 V to 3.3 V; VSS = 0 V; VLCD = 3.0 to 9.0 V; Tamb = −40 to +85 °C, all MUX settings. 3. VDD1 = 2.4 V to 3.0 V; Tamb = −20 °C to +70 °C; MUX = 68. 4. RES may be LOW before VDD on. 5. Maximum values are for fSCLK = 9 MHz. Series resistance includes ITO track + connector resistance + printed-circuit board. 6. SDOUT disable time for SPI 3-line or 4-line interface. 7. SDOUT disable time for serial 3-line interface. 8. Typical conditions: VDD1 = 2.8 V, Tamb = 20 °C, MUX = 68; fframe = 70 ± 3.4 Hz. 9. Inputs SDAH and SCLH are filtered and will reject spikes on the bus lines with a width of less than tSW(max). Table 18 Value of n as a function of multiplex rate MULTIPLEX RATE n 68 483 65 462 57 464 49 500 41 504 33 476 25 468 17 505 9 500 2004 Mar 05 42 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver handbook, full pagewidth PCF8813 VDD1 t VHRL t RW RES t R(oper) SCE MGU285 Fig.37 Reset timing. handbook, full pagewidth D/C t DCHD t DCSU T DS(cyc) t DSL t DSH E t RWHD t RWSU R/W t EHD t ESU SCE t DATSU t DATHD D0 to D7 (write) t DATACC t DATOH D0 to D7 (read) MGU638 Fig.38 Parallel interface timing (6800-type) with clocking performed by enable input (E). 2004 Mar 05 43 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver PCF8813 handbook, full pagewidth D/C t DCHD t DCSU E t RWSU t RWHD R/W TDS(cyc) t DSL t DSH SCE t DATSU t DATHD D0 to D7 (write) t DATACC t DATOH D0 to D7 (read) MGU639 Fig.39 Parallel interface timing (6800-type) with clocking performed by chip select input (SCE). 2004 Mar 05 44 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver PCF8813 handbook, full pagewidth D/C t DCHD t DCSU T DS(cyc) t DSHR, t DSHW t DSLR, t DSLW WR, RD SCE t DATSU t DATHD D0 to D7 (write) t DATACC t DATOH D0 to D7 (read) MGU640 Fig.40 Parallel interface timing (8080-type). 2004 Mar 05 45 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver handbook, full pagewidth t S2 PCF8813 t H2 t PWH2 SCE t S2 t PWL1 T cyc t PWH1 SCLK t H1 t S1 SDATA MGU642 Fig.41 3-line serial interface timing. t S2 handbook, full pagewidth t H2 t PWH2 SCE t S3 t H3 D/C t S2 t PWL1 t PWH1 T cyc SCLK SDATA MGU854 Fig.42 4-line serial interface timing. 2004 Mar 05 46 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver PCF8813 handbook, full pagewidth SCE t3 SCLK t H1 t S1 SDATA t1 t2 SDOUT MGW759 Fig.43 3-line and 4-line serial peripheral (SPI) interface timing (read mode). handbook, full pagewidth SCE t3 SCLK t H1 t S1 SDATA t1 t4 SDOUT MGW760 Fig.44 3-line serial interface timing (read mode). 2004 Mar 05 47 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver PCF8813 handbook, full pagewidth SDA tLOW tf tSU;DAT tr tf tHD;STA tSP tr tBUF SCL S tHD;STA tSU;STA tHIGH tHD;DAT tSU;STO Sr P S MSC610 Fig.45 I2C-bus timing diagram (Fast-mode). handbook, full pagewidth Sr Sr trDA tfDA P SDAH tSU;STA tHD;DAT tSU;STO tHD;STA tSU;DAT SCLH tfCL trCL1 (1) trCL1 trCL tHIGH tLOW tLOW tHIGH = MCS current source pull-up = Rp resistor pull-up (1) Rising edge of the first SCLH clock pulse after an acknowledge bit. Fig.46 I2C-bus timing diagram (Hs-mode). 2004 Mar 05 48 (1) MGK871 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver PCF8813 17 MODULE MAKER PROGRAMMING 17.1 One Time Programmable (OTP) technology has been implemented on the PCF8813. This enables the module maker to program some features of the PCF8813 after it has been assembled on an LCD module. Programming is made under the control of the interfaces and using the special pad VOTPPROG. This pad must be made available on the module glass but does not need to be accessed by the set maker. Referring to Fig.47, the VLCD calibration parameter comprises a 5-bit code (VCAL[4:0]). The code is implemented in twos complement notation giving a positive or negative offset to the VPR register. The range of the VPR[6:0] register is 0 to 127. The adder in the circuit takes this into account by having underflow and overflow protection added to it. In the event of an overflow, the output will be clamped to 255, and in the case of an underflow the output will be clamped to 0. Module maker programming is an extension of the normal functions of the PCF8813 and is effective until specifically instructed otherwise with the disable OTP command. LCD voltage calibration Given that V OP = V CAL + V PR∗ The PCF8813 features three module maker programmable parameters: and • VLCD calibration (5 bits) V LCD = a + V OP × b • Manufacturer identity (3 bits) • Seal bit (1-bit). T(norm) VLCD can be calculated using parameters a and b that are defined in Table 17. An example of the relationship between VCAL code and the VLCD calibration is shown in Table 19, where b is assumed to be 25.6 mV. Possible values for VCAL are given in Table 19. The default value for VCAL when OTP is disabled is VCAL[4:0] = 00000. handbook, full pagewidth VLCD calibration: 5-bit SIGNED value −16 to +15 VCAL[4:0] + VOP to high voltage generator MGU644 VPR register: 7-bit UNSIGNED value 0 to +127 VPR [6:0] Fig.47 VLCD calibration. 2004 Mar 05 49 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver Table 19 VCAL codes and associated nominal calibration voltage when the temperature coefficient is set to TC3 PCF8813 17.2 Manufacturer identity The second OTP feature defines the manufacturer identity. A 3-bit code MF[2:0] is used to define this parameter. The default manufacturer identity is MF[2:0] = 000. VCAL VCAL[4:0] VLCD CALIBRATION (mV) +0 00000 0 (default) +1 00001 +25.6 +2 00010 +51.2 +3 00011 +76.8 +4 00100 +102.4 +5 00101 +128.0 +6 00110 +153.6 +7 00111 +179.2 +8 01000 +204.8 +9 01001 +230.4 +10 01010 +256.0 +11 01011 +281.6 +12 01100 +307.2 SEAL BIT +13 01101 +332.8 0 possible to enter calibration mode +14 01110 +358.4 1 calibration mode disabled +15 01111 +384.0 −1 11111 −25.6 17.4 −2 11110 −51.2 17.4.1 −3 11101 −76.8 −4 11100 −102.4 −5 11011 −128.0 −6 11010 −153.6 −7 11001 −179.2 −8 11000 −204.8 −9 10111 −230.4 −10 10110 −256.0 −11 10101 −281.6 −12 10100 −307.2 −13 10011 −332.8 −14 10010 −358.4 −15 10001 −384.0 −16 10000 −409.6 2004 Mar 05 17.3 Seal bit Module maker programming is performed in a special mode; the calibration mode MM. This mode is entered via the interface command, MM. To prevent wrongful programming, a seal bit prevents the device from entering the calibration mode. This seal bit, once programmed, cannot be reversed, thus further changes in programmed values are not possible. However it is possible to disable all programmed values by applying the disable OTP command. Applying the programming voltages when not in MM mode will have no effect on the programmed values. Table 20 Seal bit definition ACTION One time programming ARCHITECTURE The OTP circuitry in the PCF8813 contains nine bits of data: five for VLCD calibration, three for the manufacturer identity and one for the seal bit. The circuitry for 1-bit is called an OTP slice. Each OTP slice consists of two main parts: the OTP cell (a non-volatile memory cell) and the shift register cell (a flip-flop). The OTP cells are accessible only through their shift register cells; both reading-from and writing-to the OTP cells are performed with the shift register cells, but only the shift register cells are visible to the rest of the circuit. The basic OTP architecture is shown in Fig.48. 50 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver PCF8813 DATA TO THE CIRCUIT FOR CONFIGURATION AND CALIBRATION handbook, full pagewidth OTP slice SHIFT REGISTER FLIP-FLOP read data from the OTP cell SHIFT REGISTER DATA INPUT SHIFT REGISTER write data to the OTP cell OTP CELLs MGU289 OTP CELL Fig.48 Basic OTP architecture. 17.4.2 OPERATIONS The shifting of data into the shift register is performed in the special mode MM. In the PCF8813, the MM mode is entered through the MM command. Once in the MM mode, the data is shifted into the shift register via any of the interfaces at the rate of 1-bit per command. After transmitting the last (9th) bit and exiting the MM mode, the interface is again in the normal mode and all other commands can be sent. Care should be taken that 9 bits of data (or a multiple of 9) are always transferred before exiting the MM mode, otherwise the bits will be in the wrong positions. The OTP architecture allows the following operations: • The OTP circuit in the PCF8813 is initialized when a reset is initiated. After the reset initiation, OTP circuits can be disabled only by sending the disable OTP command. • Reading data from the OTP cells. The content of the non-volatile OTP cells is transferred to the shift register where it may affect operation of the PCF8813. • Writing data to the OTP cells. All 9 bits of data are shifted first into the shift register via the serial interface. Then the content of the shift register is transferred to the OTP cells (there are some limitations related to storing data in these cells; see Section 17.6). The value of the seal bit in the shift register is always zero at reset (also applies to all other bits). To make sure the security feature works correctly, the MM command is disabled until a refresh has been made. Once a refresh is completed, the seal bit value in the shift register is valid and permission to enter MM mode can thus be determined. • Checking calibration without writing to the OTP cells. Shifting data into the shift register allows the effects of the VLCD voltage to be observed. The 9 bits are shifted into the shift register in a predefined order: first 5 bits of VCAL[4:0], followed by 3 bits for MF[2:0] and then the seal bit. The MSB is always first, that is the first bit shifted is VCAL[4] and the seal bit is the last bit. All OTP circuitry of the PCF8813 is enabled until the disable OTP command is given. Once enabled, the reading of data from the OTP cells is initiated by either: • Exit from Power-down mode • The Refresh command (power control). This command works only when the driver is not in Power-down. In both cases, the time required for the reading operation to complete is up to 5 ms. 2004 Mar 05 51 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver 17.5 PCF8813 Interface commands Instructions additional to those of the instruction set (Table 5) are given in Table 21. Table 21 Additional instructions COMMAND BYTE INSTRUCTION D/C R/W ACTION D7 D6 D5 D4 D3 D2 D1 D0 Reset enable OTP circuitry Function set 0 0 0 0 1 0 0 0 0 0 REF (refresh) 0 0 0 0 0 1 0 0 0 PC exit Power-down switch HVgen on/off to force refresh of shift register wait 5 ms for refresh to take effect Function set 0 0 0 0 1 0 0 1 0 1 set PD = 1 and H = 1 MM 0 0 0 0 0 1 1 1 1 0 enter MM mode 17.5.1 DISABLE OTP COMMAND 17.5.3 This is a special instruction for the PCF8813 which disables all included OTP circuitry. In this case, all OTP-related commands are inactive. VCAL and MF have no effect on VLCD and manufacture identification respectively. Once disabled, the mode can only be enabled via a reset. 17.5.2 The action of the refresh instruction (REF) is to force the OTP shift register to re-load from the non-volatile OTP cells. This instruction takes up to 5 ms to complete. During this time all other instructions may be sent. In the PCF8813, the refresh instruction is associated with the power control instruction so that the shift register is refreshed automatically every time the high voltage generator is enabled or disabled. However, if this instruction is sent while in Power-down, the PC bits are updated but the refreshing is ignored. MODULE MAKER CALIBRATION Instruction (MM) enters the device into the calibration mode. This mode enables the shift register for loading and allows programming of the non-volatile OTP cells to take place. If the seal bit is set, then this mode cannot be accessed and the instruction will be ignored. Once in calibration mode all commands are interpreted as shift register data. The mode can only be exited by sending data with bit D7 set to logic 0. Reset will also clear this mode. Each shift register data byte is preceded by D/C = 0 and has only three significant bits, thus the remaining five bits are ignored. Bit D7 is the continuation bit (D7 = 1 indicates remain in MM mode; D7 = 0 indicates exit MM mode). D6 has to be logic 0 until the last bit when the seal bit is set, in which case this is set to logic 1 (D6 is set to logic 1 only when the high voltage used for programming the cells is about to be applied). Bit D0 is the data bit and its value is shifted into the OTP shift register on the falling edge of the SCLK clock. 2004 Mar 05 REFRESH 17.6 Filling the shift register An example of the sequence of commands and data for filling the shift register is shown in Table 22. This example uses the values VCAL = −4 (11100B), MF = 4 (100B is the Philips identifying code) and the seal bit is 0. It is assumed that the PCF8813 has just been reset. After transmitting the last bit the PCF8813 can exit or remain in MM mode (see Table 22, step 1). When in MM mode, the interface does not recognize commands in the normal sense. After this sequence has been applied, it is possible to observe the impact of the data shifted in. The sequence described is not useful for OTP programming because the number of bits with value = 1 is greater than that allowed for programming (see Section 17.7). Figure 49 shows the shift register after this action. 52 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver PCF8813 Table 22 Example sequence of shift register filling STEP D/C R/W D7 D6 1 D5 D4 D3 D2 D1 D0 reset ACTION reset to enable OTP circuitry 1 0 0 0 0 1 0 0 0 0 0 3 0 0 0 0 0 1 0 0 1 PC exit Power-down (PD = 0) switch HVgen on/off to force refresh of shift register wait 5 ms for refresh to take effect 0 1 set PD to 1(2) and H to 1 1 1 0 enter MM mode X X 1 shift-in data; VCAL[4] is first bit(3) X X 1 VCAL[3] X X X 1 VCAL[2] X X X 0 VCAL[1] X X X X 0 VCAL[0] X X X X X 1 MF[2] X X X X X 0 MF[1] 0 X X X X X 0 MF[0] 0 X X X X X 0 seal bit; remain in MM mode 4 0 0 0 0 1 0 0 5 0 0 0 0 0 1 1 6 0 0 1 0 X X X 7 0 0 1 0 X X X 8 0 0 1 0 X X 9 0 0 1 0 X X 10 0 0 1 0 X 11 0 0 1 0 12 0 0 1 0 13 0 0 1 14 0 0 1 1 Notes 1. X = don’t care. 2. PD does not have to be set to 1 if the effects of VCAL are intended to be observed on VLCDOUT. 3. Bit data is not in the correct shift register position until all bits have been sent. OTP SHIFT REGISTER handbook, full pagewidth shifting direction SEAL BIT = 0 LSB MMMF[2:0] MSB 0 0 1 LSB 0 MMVOPCAL [4:0] 0 1 1 MSB 1 MGU645 Fig.49 Shift register contents after example sequence of Table 22. 2004 Mar 05 53 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver 17.7 PCF8813 cell at a time is recommended. This is achieved by filling all but one shift register cells with 0. Programming flow Programming is achieved in MM mode and with application of the programming voltages. Since the data for programming the OTP cell is contained in the corresponding shift register cell, the shift register cell must be loaded with a 1 in order to program the corresponding OTP cell. If the shift register cell contains a 0, then no action will take place when the programming voltages are applied. The programming specification refers to the voltages at the chip pads, therefore contact resistance must be considered by the user. An example of the sequence of commands and data for OTP programming is given in Table 23. The order for programming cells is not significant but it is recommended that the seal bit is programmed last. Once the seal bit has been programmed it is not possible to re-enter the MM mode. Once programmed, an OTP cell cannot be de-programmed. Also, a previously programmed cell that is an OTP cell containing a 1 must not be re-programmed. It is assumed that the PCF8813 has been reset just before the programming commences. During programming a substantial current flows in the VLCDIN pad. For this reason programming only one OTP Table 23 Example sequence for OTP programming STEP D/C R/W D7 D6 D5 1 D4 D3 D2 D1 D0 reset ACTION enable OTP by applying a reset 1 0 0 0 0 1 0 0 0 0 0 3 0 0 0 0 0 1 0 0 1 PC exit Power-down (PD = 0) switch HVgen on/off to force refresh of shift register wait 5 ms for refresh to take effect 4 0 0 0 0 1 0 0 1 0 1 re-enter Power-down (PD = 1 and H = 1) 5 0 0 0 0 0 1 1 1 1 0 enter MM mode 6 0 0 1 0 X X X X X 1 VCAL[4] (the only bit with value of 1) 7 0 0 1 0 X X X X X 1 VCAL[3] 8 0 0 1 0 X X X X X 1 VCAL[2] 9 0 0 1 0 X X X X X 0 VCAL[1] 10 0 0 1 0 X X X X X 0 VCAL[0] 11 0 0 1 0 X X X X X 0 MF[2] 12 0 0 1 0 X X X X X 0 MF[1] 13 0 0 1 0 X X X X X 0 MF[0] 14 0 0 1 1 X X X X X 0 seal bit; remain in CALMM mode 15 − − − − − − − − − − apply programming voltage at pads VOTPPROG and VLCDIN − apply external reset Repeat steps 6 to 15 for each bit that should be programmed to 1 15 − − − − − − − − Note 1. X = don’t care. 2004 Mar 05 54 − Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver 17.8 PCF8813 Programming specification thd(INTCLK) tsu(INTCLK) handbook, full pagewidth INT_CLK VVOTPPROG VLCDIN tsu(gate) thd(gate) tPW MGU646 Fig.50 Programming waveforms. Table 24 Programming parameters SYMBOL VDD1 PARAMETER MIN. TYP. MAX. UNIT 2.4 − 3.3 V programming active 11.0 11.5 12.0 V programming inactive 0 − VDD1 V programming active 9.0 9.50 10.5 V programming inactive 0 − VDD2 V logic supply voltage VOTPPROG voltage applied to pad VOTPPROG VLCDIN CONDITION voltage applied to pad VLCDIN VOTPPROG relative to VSS1; note 1 VLCDIN relative to VSS1; notes 1, 2 IOTPPROG current drawn during programming − 100 200 µA ILCDIN current drawn during programming when programming one bit to logic 1 − 850 1000 µA Tprog ambient temperature during programming 0 25 40 °C tsu(INTCLK) internal data set-up time after last clock 1 − − µs thd(INTCLK) internal data hold time before next clock 1 − − µs tsu(gate) VOTPPROG set-up time prior to programming 1 − 10 ms thd(gate) VOTPPROG hold time after programming 1 − 10 ms tPW programming voltage pulse width 100 120 200 ms Notes 1. The voltage drop across the ITO track and zebra connector must be taken into account to guarantee sufficient voltage at the chip pads. 2. The high voltage generator must be disabled (VPR = 0 and PRS = 0) when pad VLCDIN is being driven. 2004 Mar 05 55 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver 17.9 PCF8813 Programming examples Table 25 Programming example for PCF8813 with serial interface (3-line serial, 3-line SPI or 4-line SPI) SERIAL BUS BYTE STEP DISPLAY D/C OPERATION DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 start 2 0 0 0 1 0 0 0 0 1 function set: PD = 0, V = 0; select extended instruction set (H = 1) 3 0 0 0 0 1 0 0 0 1 set PRS to higher programming range (PRS = 1) 4 0 1 0 0 1 0 0 0 0 set VPR: VPR* = (a + 132* × b) = 8.596 V (required voltage is dependent on liquid crystal operating environment) 5 0 0 0 1 0 0 0 0 0 function set: PD = 0, V = 0; select normal instruction set (H = 0) 6 0 0 0 0 0 1 1 0 0 display control: set normal mode (D = 1 and E = 0) 7 0 0 0 0 1 0 1 1 0 set data order: DO = 0 0 0 0 0 0 0 0 0 0 − 1 1 1 0 0 0 0 0 − 0 0 0 0 0 1 1 1 9 1 0 0 0 1 1 1 1 1 10 1 0 0 0 0 0 1 0 1 11 1 0 0 0 0 0 1 1 1 8 SCE is going low option available in 3-line SPI for setting display data length command (7 shown) data write: Y and X are initialized to 0 by default, so they are not set here MGS405 data write MGS406 data write MGS407 12 1 0 0 0 0 0 0 0 0 data write MGS407 13 1 0 0 0 1 1 1 1 1 data write MGS409 2004 Mar 05 56 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver PCF8813 SERIAL BUS BYTE STEP DISPLAY D/C 14 1 OPERATION DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 0 0 data write MGS410 15 1 0 0 0 1 1 1 1 1 data write MGS411 16 0 0 0 0 0 1 1 0 1 display control: set inverse video mode (D = 1 and E = 1) MGS412 17 0 1 0 0 0 0 0 0 0 18 1 0 0 0 0 0 0 0 0 set X address of RAM: set address to ‘0000000’ MGS412 data write MGS414 Table 26 Programming example for PCF8813 with I2C -bus SERIAL BUS BYTE STEP DISPLAY D/C 1 OPERATION DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 I2C-bus start 2 − 0 1 1 1 1 SA1 SA0 0 slave address for write 3 − 0 0 0 0 0 0 0 0 control byte with cleared CO bit and D/C set to logic 0 4 − 0 0 1 0 0 0 0 1 function set: PD = 0, V = 0; select extended instruction set (H = 1) 5 − 0 0 0 1 0 0 0 1 set PRS to higher programming range (PRS = 1) 6 − 1 0 0 1 0 0 0 0 set VPR: VPR* = (a + 132* × b) = 8.596 V (required voltage is dependent on liquid crystal operating environment) 7 − 0 0 1 0 0 0 0 0 function set: PD = 0; V = 0; select normal instruction set (H = 0) 2004 Mar 05 57 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver PCF8813 SERIAL BUS BYTE STEP DISPLAY D/C OPERATION DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 8 − 0 0 0 0 1 1 0 0 display control: set normal mode (D = 1 and E = 0) 9 − 0 0 0 1 0 1 1 0 − 0 0 0 0 0 1 0 0 display configuration (DO = 0) 10 − 11 − 0 1 1 1 1 SA1 SA0 0 slave address for write 12 − 0 1 0 0 0 0 0 0 control byte with cleared CO bit and D/C set to logic 1 13 1 0 0 0 1 1 1 1 − data write: Y and X are initialized to 0 by default, so they are not set here 14 1 0 0 0 0 0 0 1 − I2C-bus start restart: to write into the display RAM the D/C must be set to logic 1, therefore a control byte is needed MGS405 data write MGS406 15 1 0 0 0 0 0 1 1 − data write MGS407 16 1 0 0 0 0 0 0 0 − data write MGS407 17 1 0 0 0 1 1 1 1 − 18 1 0 0 0 0 0 1 0 − 19 1 0 0 0 1 1 1 1 − data write MGS409 data write MGS410 data write MGS411 I2C-bus start 20 21 − 0 22 − 1 2004 Mar 05 1 1 1 1 restart SA1 SA0 0 slave address for write control byte with set CO bit and D/C set to logic 0 58 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver PCF8813 SERIAL BUS BYTE STEP DISPLAY D/C 23 − OPERATION DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 0 1 display control: set inverse video mode (D = 1 and E = 1) MGS412 24 − 1 0 0 0 0 0 0 0 control byte with set CO bit and D/C set to logic 0 25 − 1 0 0 0 0 0 0 0 Set X address of RAM: set address to 0000000 26 − 1 1 0 0 0 0 0 0 control byte with set CO bit and D/C set to logic 1 27 − 0 0 0 0 0 0 0 0 data write 28 − 1 0 0 0 0 0 0 0 control byte with set CO bit and D/C set to logic 0 29 − 1 0 0 0 0 0 0 0 set X address of RAM: set address to 0000000 MGS412 MGS414 MGS414 I2C-bus 30 start restart 31 − 0 1 1 1 1 SA1 SA0 0 slave address for write 32 − 1 1 0 0 0 0 0 0 control byte with set CO bit and D/C set to logic 1 33 − 1 1 1 1 1 0 0 0 write data 34 − 1 0 0 0 0 0 0 0 MGS414 2004 Mar 05 59 control byte with set CO bit and D/C set to logic 0 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver PCF8813 18 APPLICATION INFORMATION 18.2 For additional application information, refer to application note “AN10170”. In the following application examples, the required minimum values of the external capacitors are: 18.1 Application examples • CVLCD = 100 nF minimum Protection from light • CVDD, CVDD1 and CVDD2 = 1 µF minimum Semiconductors are light-sensitive. Exposure to light sources can cause malfunctions, therefore the IC should be protected from light in the application. Light protection needs to be applied to all sides of the IC (front, rear and all edges). • Higher capacitor values are recommended for ripple reduction. handbook, full pagewidth DISPLAY 102 × 68 pixels 36 VSS1 VSS2 PCF8813 VLCDSENSE VLCDOUT VLCDIN 102 VDD2, 3 VDD1 32 CVLCD I/O CVDD VDD VSS MGU647 Fig.51 Application example using the internal charge pump and a single VDD source. 2004 Mar 05 60 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver PCF8813 handbook, full pagewidth DISPLAY 102 × 68 pixels 36 VLCDSENSE VLCDOUT VLCDIN 102 PCF8813 VSS1 VSS2 VDD1 VDD2, 3 32 C VDD1 VDD1 I/O CVLCD CVDD2 MGU648 VSS VDD2 Fig.52 Application example using the internal charge pump and two separate VDD sources (VDD1 and VDD2). handbook, full pagewidth DISPLAY 102 × 68 pixels I/O VLCDIN VLCDOUT VSS1 VSS2 PCF8813 36 VLCDSENSE 102 VDD2, 3 VDD1 32 CVDD VDD VSS VLCDIN MGU649 Fig.53 Application example using external high voltage generation. 2004 Mar 05 61 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver PCF8813 19 DEVICE PROTECTION DIAGRAM handbook, full pagewidth VDD1 VDD2 VDD3 VSS1 VSS1 VSS1 VSS2 VSS2 VLCDIN , VLCDSENSE VLCDOUT VSS1 VSS1 VLCDIN VDD1 VSS1 VOTPPROG VSS1 DB [7:0], SCLK, SDATA, SDO, SA1, SA0, R/W, WR LCD outputs VDD1 OSC, RES, RD, D/C, PS [2:0], T1, T2, T5, E VSS1 VSS1 VDD1 VDD1 I2C-bus pins T3, T4, VSS1*, VDD* VSS1 VSS1 VSS1 MGW770 Protection diode maximum forward current = 5 mA. Fig.54 Protection circuit diagrams. 2004 Mar 05 62 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver PCF8813 VSS1(1) DC SCE/SCLH VDD1(1) OSC VSS2 VSS1 T5 T1 PS [0] T2 T8 PS [1] VDD1 PS [2] T4 T3 (1) VLCDIN VLCDOUT RES VLCDSENSE dummy dummy handbook, full pagewidth VOTPPROG 20 BONDING PAD INFORMATION T8 alignment mark y 32 Columns x 32 Columns C0 8 Rows R31 8 Rows R0 8 Rows R16 8 Rows R15 pad 1 0, 0 T8 dummy dummy SDAHOUT SDAH VDD1 VDD3 VDD2 VDD1(1) R/W/WR E/RD DB0 DB1 DB2/SA0 DB3/SA1 DB4 DB5/SD0 DB6/SCLK DB7/SDATA dummy alignment & dummy PCF8813 alignment mark 8 Rows dummy R32 8 Rows R47 R67(2) R67 (ICON ROW) R48 8 Rows R63 R66 8 Rows C101 38 Columns alignment & dummy MGW797 (1) Can be used to tie-off unused input pads to the power supply voltage or to ground. (2) Used only for icons. Fig.55 Bonding pad locations. 2004 Mar 05 63 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver Table 27 Bonding pad locations All x and y coordinates are referenced to the centre of the chip; dummy bumps should never be connected to any electrical nodes; dimensions in µm; see Fig.55. SYMBOL dummy COORDINATES SYMBOL PAD x y R29 36 −3141 −814.5 COORDINATES R30 37 −3087 −814.5 x y R31 38 −3033 −814.5 −5328 +814.5 C0 39 −2871 −814.5 40 −2817 −814.5 PAD 1 PCF8813 dummy 2 −5328 −814.5 C1 dummy 3 −5274 −814.5 C2 41 −2763 −814.5 dummy and alignment 4 −5175 −814.5 C3 42 −2709 −814.5 C4 43 −2655 −814.5 dummy 5 −5085 −814.5 C5 44 −2601 −814.5 dummy 6 −5031 −814.5 C6 45 −2547 −814.5 R15 7 −4869 −814.5 C7 46 −2493 −814.5 R14 8 −4815 −814.5 C8 47 −2439 −814.5 R13 9 −4761 −814.5 C9 48 −2385 −814.5 R12 10 −4707 −814.5 C10 49 −2331 −814.5 R11 11 −4653 −814.5 C11 50 −2277 −814.5 R10 12 −4599 −814.5 C12 51 −2223 −814.5 R9 13 −4545 −814.5 C13 52 −2169 −814.5 R8 14 −4491 −814.5 C14 53 −2115 −814.5 R7 15 −4437 −814.5 C15 54 −2061 −814.5 R6 16 −4383 −814.5 C16 55 −2007 −814.5 R5 17 −4329 −814.5 C17 56 −1953 −814.5 R4 18 −4275 −814.5 C18 57 −1899 −814.5 R3 19 −4221 −814.5 C19 58 −1845 −814.5 R2 20 −4167 −814.5 C20 59 −1791 −814.5 R1 21 −4113 −814.5 C21 60 −1737 −814.5 R0 22 −4059 −814.5 C22 61 −1683 −814.5 R16 23 −3843 −814.5 C23 62 −1629 −814.5 R17 24 −3789 −814.5 C24 63 −1575 −814.5 R18 25 −3735 −814.5 C25 64 −1521 −814.5 R19 26 −3681 −814.5 C26 65 −1467 −814.5 R20 27 −3627 −814.5 C27 66 −1413 −814.5 R21 28 −3573 −814.5 C28 67 −1359 −814.5 R22 29 −3519 −814.5 C29 68 −1305 −814.5 R23 30 −3465 −814.5 C30 69 −1251 −814.5 R24 31 −3411 −814.5 C31 70 −1197 −814.5 R25 32 −3357 −814.5 C32 71 −1035 −814.5 R26 33 −3303 −814.5 C33 72 −981 −814.5 R27 34 −3249 −814.5 C34 73 −927 −814.5 R28 35 −3195 −814.5 C35 74 −873 −814.5 2004 Mar 05 64 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver PCF8813 COORDINATES SYMBOL COORDINATES PAD SYMBOL x y PAD x y C36 75 −819 −814.5 C75 114 +1395 −814.5 C37 76 −765 −814.5 C76 115 +1449 −814.5 C38 77 −711 −814.5 C77 116 +1503 −814.5 C39 78 −657 −814.5 C78 117 +1557 −814.5 C40 79 −603 −814.5 C79 118 +1611 −814.5 C41 80 −549 −814.5 C80 119 +1665 −814.5 C42 81 −495 −814.5 C81 120 +1719 −814.5 C43 82 −441 −814.5 C82 121 +1773 −814.5 C44 83 −387 −814.5 C83 122 +1827 −814.5 C45 84 −333 −814.5 C84 123 +1881 −814.5 C46 85 −279 −814.5 C85 124 +1935 −814.5 C47 86 −225 −814.5 C86 125 +1989 −814.5 C48 87 −171 −814.5 C87 126 +2043 −814.5 C49 88 −117 −814.5 C88 127 +2097 −814.5 C50 89 −63 −814.5 C89 128 +2151 −814.5 C51 90 −9 −814.5 C90 129 +2205 −814.5 C52 91 +45 −814.5 C91 130 +2259 −814.5 C53 92 +99 −814.5 C92 131 +2313 −814.5 C54 93 +153 −814.5 C93 132 +2367 −814.5 C55 94 +207 −814.5 C94 133 +2421 −814.5 C56 95 +261 −814.5 C95 134 +2475 −814.5 C57 96 +315 −814.5 C96 135 +2529 −814.5 C58 97 +369 −814.5 C97 136 +2583 −814.5 C59 98 +423 −814.5 C98 137 +2637 −814.5 C60 99 +477 −814.5 C99 138 +2691 −814.5 C61 100 +531 −814.5 C100 139 +2745 −814.5 C62 101 +585 −814.5 C101 140 +2799 −814.5 C63 102 +639 −814.5 R67 141 +2961 −814.5 C64 103 +801 −814.5 R66 142 +3015 −814.5 C65 104 +855 −814.5 R65 143 +3069 −814.5 C66 105 +909 −814.5 R64 144 +3123 −814.5 C67 106 +963 −814.5 R63 145 +3177 −814.5 C68 107 +1017 −814.5 R62 146 +3231 −814.5 C69 108 +1071 −814.5 R61 147 +3285 −814.5 C70 109 +1125 −814.5 R60 148 +3339 −814.5 C71 110 +1179 −814.5 R59 149 +3393 −814.5 C72 111 +1233 −814.5 R58 150 +3447 −814.5 C73 112 +1287 −814.5 R57 151 +3501 −814.5 C74 113 +1341 −814.5 R56 152 +3555 −814.5 2004 Mar 05 65 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver PCF8813 COORDINATES COORDINATES SYMBOL SYMBOL PAD x y PAD x y R55 153 +3609 −814.5 VDD3 192 +3204 +814.5 R54 154 +3663 −814.5 VDD3 193 +3150 +814.5 R53 155 +3717 −814.5 VDD3 194 +3096 +814.5 R52 156 +3771 −814.5 VDD3 195 +3042 +814.5 R51 157 +3825 −814.5 VDD3 196 +2988 +814.5 R50 158 +3879 −814.5 VDD2 197 +2934 +814.5 R49 159 +3933 −814.5 VDD2 198 +2880 +814.5 R48 160 +3987 −814.5 VDD2 199 +2826 +814.5 R32 161 +4203 −814.5 VDD2 200 +2772 +814.5 R33 162 +4257 −814.5 VDD2 201 +2718 +814.5 R34 163 +4311 −814.5 VDD2 202 +2664 +814.5 R35 164 +4365 −814.5 VDD2 203 +2610 +814.5 R36 165 +4419 −814.5 VDD2 204 +2556 +814.5 R37 166 +4473 −814.5 VDD2 205 +2502 +814.5 R38 167 +4527 −814.5 VDD2 206 +2448 +814.5 R39 168 +4581 −814.5 VDD1 207 +2286 +814.5 R40 169 +4635 −814.5 R/W/WR 208 +2124 +814.5 R41 170 +4689 −814.5 E/RD 209 +1962 +814.5 R42 171 +4743 −814.5 DB0 210 +1746 +814.5 R43 172 +4797 −814.5 DB1 211 +1530 +814.5 R44 173 +4851 −814.5 DB2/SA0 212 +1314 +814.5 R45 174 +4905 −814.5 DB3/SA1 213 +1098 +814.5 R46 175 +4959 −814.5 DB4 214 +882 +814.5 R47 176 +5013 −814.5 DB5/SDOUT 215 +666 +814.5 R67 177 +5067 −814.5 DB6/ SCLK 216 +450 +814.5 dummy and alignment 178 +5229 −814.5 DB7/SDATA 217 +234 +814.5 218 +72 +814.5 dummy 179 +5328 −814.5 VSS1 D/C 219 −90 +814.5 dummy 180 +5328 +814.5 SCE/SCLH 220 −630 +814.5 dummy 181 +5274 +814.5 SCE/SCLH 221 −684 +814.5 dummy 182 +4752 +814.5 VOTPPROG 222 −792 +814.5 SDAHOUT 183 +4500 +814.5 VOTPPROG 223 −846 +814.5 SDAH 184 +4122 +814.5 VOTPPROG 224 −900 +814.5 SDAH 185 +4068 +814.5 VDD1 225 −1008 +814.5 VDD1 186 +3528 +814.5 OSC 226 −1296 +814.5 VDD1 187 +3474 +814.5 VSS2 227 −1458 +814.5 VDD1 188 +3420 +814.5 VSS2 228 −1512 +814.5 VDD1 189 +3366 +814.5 VSS2 229 −1566 +814.5 VDD1 190 +3312 +814.5 VSS2 230 −1620 +814.5 VDD1 191 +3258 +814.5 2004 Mar 05 66 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver PCF8813 COORDINATES SYMBOL COORDINATES PAD SYMBOL x y PAD x y VSS2 231 −1674 +814.5 VDD1 253 −3618 +814.5 VSS2 232 −1728 +814.5 T4 254 −3780 +814.5 VSS2 233 −1782 +814.5 T3 255 −3942 +814.5 VSS2 234 −1836 +814.5 VLCDIN 256 −3996 +814.5 VSS2 235 −1890 +814.5 VLCDIN 257 −4050 +814.5 VSS2 236 −1944 +814.5 VLCDIN 258 −4104 +814.5 VSS1 237 −1998 +814.5 VLCDIN 259 −4158 +814.5 VSS1 238 −2052 +814.5 VLCDIN 260 −4212 +814.5 VSS1 239 −2106 +814.5 VLCDIN 261 −4266 +814.5 VSS1 240 −2160 +814.5 VLCDIN 262 −4320 +814.5 VSS1 241 −2214 +814.5 VLCDOUT 263 −4374 +814.5 VSS1 242 −2268 +814.5 VLCDOUT 264 −4428 +814.5 VSS1 243 −2322 +814.5 VLCDOUT 265 −4482 +814.5 VSS1 244 −2376 +814.5 VLCDOUT 266 −4536 +814.5 VSS1 245 −2430 +814.5 VLCDOUT 267 −4590 +814.5 VSS1 246 −2484 +814.5 VLCDOUT 268 −4644 +814.5 T5 247 −2646 +814.5 VLCDOUT 269 −4698 +814.5 T1 248 −2808 +814.5 VLCDOUT 270 −4752 +814.5 T2 249 −2970 +814.5 VLCDOUT 271 −4806 +814.5 PS0 250 −3132 +814.5 VLCDSENSE 272 −4860 +814.5 PS1 251 −3294 +814.5 RES 273 −5076 +814.5 PS2 252 −3456 +814.5 dummy 274 −5274 +814.5 2004 Mar 05 67 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver 10.845 mm handbook, halfpage PCF8813 handbook, halfpage PCF8813 1.845 mm y center d pitch y x center MGU651 x MGU650 d = 90 µm; there are two 90 µm alignment marks. Fig.56 Chip dimensions. Fig.57 Shape of alignment mark. Table 28 Bump size PARAMETER Bump width VALUE (µm) 32 Bump length 81 Bump height 17.5 Minimum pad pitch 54 Pad size, aluminium 45 × 81 Maximum wafer thickness, including bumps 430 Typical wafer thickness, without bumps 381 2004 Mar 05 68 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver PCF8813 21 TRAY INFORMATION A x handbook, full pagewidth G y C H 1,1 D x,1 1,2 B F x,y 1,y A A E K M L J SECTION A-A MGW798 Fig.58 Tray details. Table 29 Tray dimensions DIMS DESCRIPTION VALUE pocket pitch; x direction 14.66 mm B pocket pitch; y direction 3.76 mm C pocket width; x direction 10.95 mm D pocket width; y direction 1.95 mm E tray width; x direction 50.8 mm F tray width; y direction 50.8 mm G distance from cut corner to pocket (1, 1) centre 10.74 mm H distance from cut corner to pocket (1, 1) centre 4.72 mm J tray thickness 3.96 mm K tray cross section 1.78 mm L tray cross section 2.44 mm M pocket depth 0.89 mm x number of pockets in x direction 3 y number of pockets in y direction 12 2004 Mar 05 handbook, halfpage PCF8813 A MGW799 The orientation of the IC in a pocket is indicated by the position of the IC type name on the die surface with respect to the chamfer on the upper left corner of the tray. Refer to the bonding pad location diagram for the orientating and position of the type name on the die surface. Fig.59 Tray alignment. 69 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver PCF8813 22 DATA SHEET STATUS LEVEL DATA SHEET STATUS(1) PRODUCT STATUS(2)(3) Development DEFINITION I Objective data II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Production This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 23 DEFINITIONS 24 DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2004 Mar 05 70 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver PCF8813 Bare die All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of ninety (90) days from the date of Philips' delivery. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post packing tests performed on individual die or wafer. Philips Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, Philips Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used. 25 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 2004 Mar 05 71 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: [email protected]. SCA76 © Koninklijke Philips Electronics N.V. 2004 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R15/02/pp72 Date of release: 2004 Mar 05 Document order number: 9397 750 12934