INTEGRATED CIRCUITS DATA SHEET SAA5249 Integrated VIP and Teletext with Background Memory Controller (IVT1.1BMCX) Preliminary specification Supersedes data of December 1993 File under Integrated Circuits, IC02 1996 Nov 07 Philips Semiconductors Preliminary specification Integrated VIP and Teletext with Background Memory Controller SAA5249 FEATURES • Complete teletext decoder featuring a background memory controller in a single 48-pin DIP package. Capable of storing of up to 512 teletext pages in an external DRAM, giving instant access to the teletext data • Automatic processing of extension packet 26 for widest possible language decoding. All our standard language options can be available, and the language option is readable via I2C-bus. GENERAL DESCRIPTION The Integrated VIP and Teletext (IVT1.1BMCX) is a teletext decoder (contained within a single chip package) for decoding 625-line based World System Teletext transmissions. With its built-in background memory controller the device can store incoming teletext packets in the external 1M4 DRAM. With this large packet store which can be rapidly scanned, we can achieve near instantaneous access to all the pages transmitted by the broadcaster. • 100% hardware compatible with the SAA5247 plug-in replacement and with the possibility of extra market in those countries with packet 26 transmissions. Still pin-aligned to SAA5254 and SAA5244A. • 100% software compatible with the SAA5247, and SAA5244A, except if the special OSD symbols were used. Also 100% software compatible to SAA5254. In all events there is a change to the ROM ID number. This version of the decoder also contains some extra hardware to process extension packet 26 automatically, extending the markets to which the TV chassis can be shipped and offering many more language options for the set maker. • The device is pin-aligned with the other members of the new Philips teletext decoder family, i.e. SAA5281 and the SAA5254, making one hardware solution for the whole range • Low software overhead for the microprocessor • RGB interface to standard colour decoder ICs, push-pull output drive. QUICK REFERENCE DATA SYMBOL PARAMETER MIN. TYP. MAX. UNIT VDD supply voltage 4.5 5.0 5.5 V IDD supply current − 90 120 mA Vsyn sync amplitude 0.1 0.3 0.6 V Vvid video amplitude 0.7 1.0 1.4 V fXTAL crystal frequency − 27 − MHz Tamb operating ambient temperature −20 − +70 °C ORDERING INFORMATION PACKAGE TYPE NUMBER NAME SAA5249P/E DIP48 plastic dual in-line package; 48 leads (600 mil) SOT240-1 SAA5249GP/E QFP64 plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 × 20 × 2.7 mm; high stand-off height SOT319-1 1996 Nov 07 DESCRIPTION 2 VERSION Philips Semiconductors Preliminary specification Integrated VIP and Teletext with Background Memory Controller SAA5249 BLOCK DIAGRAM A0 to A9 D0 to D3 R/W CAS0 CAS1 RAS Y BLANK COR RGBREF R/G/B handbook, full pagewidth 10 3 4 42 SEL1 SEL2 VDD1 ODD/EVEN 24 23 41 21 29 27 20 17 to 19 28 46 DRAM INTERFACE 45 DISPLAY HAMMING CHECKER AND PACKET 26 PROCESSING ENGINE 3 VDD2 12 VSSn 16, 22 BACKGROUND MEMORY CONTROL SAA5249 38 MUX PAGE MEMORY TELETEXT ACQUISITION AND DECODING DATA SLICER AND CLOCK REGENERATOR 31 I 2C - BUS INTERFACE DCVBS VSS1 REF+ OSCOUT OSCIN 7 8 ANALOG TO DIGITAL CONVERTER 4 5 CRYSTAL OSCILLATOR 6 GNDO SCL TIMING CHAIN DISPLAY CLOCK PHASE LOCKED LOOP INPUT CLAMP AND SYNC SEPARATOR 9 11 BLACK IREF 10 CVBS 13 POL Fig.1 Block diagram for SOT240-1 (DIP48) package. 1996 Nov 07 30 SDA 3 15 VCR/FFB 14 STTV/LFB MLB304 Philips Semiconductors Preliminary specification Integrated VIP and Teletext with Background Memory Controller SAA5249 PINNING PIN SYMBOL DESCRIPTION SOT240-1 SOT319-1(1) n.c. 1 1 not connected n.c. 2 2 not connected VDD1 3 25 +5 V supply OSCOUT 4 27 27 MHz crystal oscillator output OSCIN 5 28 27 MHz crystal oscillator input GNDO 6 29 0 V crystal oscillator ground VSS1 7 12 0 V ground REF+ 8 32 positive reference voltage; this pin should be connected to ground via a 100 nF capacitor BLACK 9 35 video black level storage pin; this pin should be connected to ground via a 100 nF capacitor CVBS 10 36 composite video input pin; a positive-going 1 V (p-p) input is required, connected via a 100 nF capacitor IREF 11 37 reference current input pin; connected to ground via a 27 kΩ resistor VDD2 12 38 +5 V supply POL 13 39 STTV/LFB/FFB polarity selection pin STTV/LFB 14 40 sync to TV output pin/line flyback input pin; function controlled by an internal register bit (scan sync mode) VCR/FFB 15 42 PLL time constant switch/field input pin; function controlled by an internal register bit (scan sync mode) VSS2 16 30 0 V ground REF− − 31 negative reference voltage; this pin should be connected to REF+ via a 100 nF capacitor R 17 49 dot rate character output of the RED colour information G 18 50 dot rate character output of the GREEN colour information B 19 51 dot rate character output of the BLUE colour information RGBREF 20 52 input DC voltage to define the output high level on the RGB pins BLANK 21 53 dot rate fast blanking output VSS3 22 54, 55 CAS0 23 56 column address select to external DRAM for BMCX function CAS1 24 57 column address select to external DRAM for BMCX function for second DRAM where two 256 k × 4 devices are used A4 25 58 address output to external DRAM for BMCX function A3 26 59 address output to external DRAM for BMCX function COR 27 60 programmable output to provide contrast reduction of the TV picture for mixed text and picture displays or when viewing newsflash/subtitle pages; open drain output ODD/EVEN 28 61 25 Hz output synchronized with the CVBS input field sync pulses to produce a non-interlaced display by adjustment of the vertical deflection currents 1996 Nov 07 0 V ground; internally connected for SOT319 4 Philips Semiconductors Preliminary specification Integrated VIP and Teletext with Background Memory Controller SAA5249 PIN SYMBOL DESCRIPTION SOT240-1 SOT319-1(1) Y 29 62 dot rate character output of teletext foreground colour information; open drain output SCL 30 63 serial clock input for I2C-bus; it can still be driven HIGH during power-down of the device SDA 31 64 serial data port for the I2C-bus; open drain output. It can still be driven HIGH during power-down of the device A5 32 4 address output to external DRAM for BMCX function A2 33 5 address output to external DRAM for BMCX function A6 34 6 address output to external DRAM for BMCX function A1 35 8 address output to external DRAM for BMCX function A7 36 9 address output to external DRAM for BMCX function A0 37 11 address output to external DRAM for BMCX function VSS4 38 43 0 V ground A8 39 13 address output to external DRAM for BMCX function A9 40 14 address output to external DRAM for BMCX function RAS 41 15 row address select to external DRAM R/W 42 18 read/write for external DRAM D2 43 19 data input/output for external DRAM D0 44 20 data input/output for external DRAM SEL2 45 21 RAM select input to choose external DRAM size SEL1 46 22 RAM select input to choose external DRAM size D3 47 23 data input/output for external DRAM D1 48 24 data input/output for external DRAM Note 1. The remaining pins for SOT319 are not connected. 1996 Nov 07 5 Philips Semiconductors Preliminary specification Integrated VIP and Teletext with Background Memory Controller SAA5249 n.c. 1 48 D1 n.c. 2 47 D3 VDD1 3 46 SEL1 OSCOUT 4 45 SEL2 OSCIN 5 44 D0 GNDO 6 43 D2 VSS1 7 42 R/W REF 8 41 RAS BLACK 9 40 A9 CVBS 10 39 A8 38 VSS4 IREF 11 VDD2 12 37 A0 SAA5249P POL 13 36 A7 STTV/LFB 14 35 A1 VCR/FFB 15 34 A6 VSS2 16 33 A2 R 17 32 A5 G 18 31 SDA B 19 30 SCL RGBREF 20 29 Y 28 ODD/EVEN BLANK 21 VSS3 22 27 COR CAS0 23 26 A3 CAS1 24 25 A4 MLB305 Fig.2 Pin configuration; SOT240-1 (DIP48). 1996 Nov 07 6 Philips Semiconductors Preliminary specification 52 RGBREF 53 BLAN 54 V SS3 55 V SS3 56 CAS0 58 A4 57 CAS1 SAA5249 59 A3 60 COR 61 ODD/EVEN 62 Y index corner 63 SCL 64 SDA Integrated VIP and Teletext with Background Memory Controller n.c. 1 51 B n.c. 2 50 G n.c. 3 49 R A5 4 48 A2 5 47 A6 6 46 n.c. 7 45 A1 8 44 A7 9 43 SAA5249GP n.c. 10 VSS4 42 VCR/FFB 41 n.c. A0 11 VSS1 12 40 STTV/LFB A8 13 39 POL A9 14 38 VDD2 RAS 15 37 IREF n.c. 16 36 CVBS n.c. 17 35 BLACK 31 32 REF REF V SS2 30 GNDO 29 OSCIN 28 OSCOUT 27 n.c. 26 VDD1 25 D1 24 D3 23 33 n.c. SEL1 22 D2 19 SEL2 21 34 n.c. D0 20 R/W 18 Fig.3 Pin configuration; SOT319-1 (QFP64). 1996 Nov 07 n.c. 7 MLB306 Philips Semiconductors Preliminary specification Integrated VIP and Teletext with Background Memory Controller SAA5249 LIMITING VALUES In accordance with Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER MIN. MAX. UNIT VDD supply voltage (all supplies) −0.3 +6.5 V VI input voltage (any input) −0.3 VDD + 0.5 V VO output voltage (any output) −0.3 VDD + 0.5 V IO output current (each output) − ±10 mA IIOK DC input or output diode current − ±20 mA Tamb operating ambient temperature −20 +70 °C QUALITY AND RELIABILITY This device will meet Philips Semiconductors General Quality Specification for Business group “Consumer Integrated Circuits SNW-FQ-611-Part E”. The principal requirements are shown in Tables 1 to 4. 1996 Nov 07 8 Philips Semiconductors Preliminary specification Integrated VIP and Teletext with Background Memory Controller SAA5249 Group A Table 1 Acceptance tests per lot REQUIREMENTS(1) TEST Mechanical cumulative target: <100 ppm Electrical cumulative target: <100 ppm Group B Table 2 Processability tests (by package family) REQUIREMENTS(1) TEST Solderability <7% LTPD Mechanical <15% LTPD Solder heat resistance <15% LTPD Group C Table 3 Reliability tests (by process family) TEST CONDITIONS REQUIREMENTS(1) Operational life 168 hours at Tj = 150 °C <1500 FPM; equivalent to <100 FITS at Tj = 70 °C Humidity life temperature, humidity, bias (1000 hours, 85 °C, 85% RH or equivalent test) <2000 FPM Temperature cycling performance Tstg(min) to Tstg(max) <2000 FPM Table 4 Reliability tests (by device type) TEST ESD and latch-up CONDITIONS ESD Human body model 2000 V, 100 pF, 1.5 kΩ <15% LTPD ESD Machine model 200 V, 100 pF, 1.5 kΩ <15% LTPD latch-up 100 mA, 1.5 × VDD (absolute maximum) <15% LTPD Note to Tables 1 to 4 1. ppm = fraction of defective devices, in parts per million. LTPD = Lot Tolerance Percent Defective. FPM = fraction of devices failing at test condition, in Failures Per Million. FITS = Failures In Time Standard. 1996 Nov 07 REQUIREMENTS(1) 9 Philips Semiconductors Preliminary specification Integrated VIP and Teletext with Background Memory Controller SAA5249 CHARACTERISTICS VDD = 5 V ± 10%; Tamb = −20 to +70 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDD supply voltage 4.5 5.0 5.5 V IDD(tot) total supply current − 90 120 mA Vsync sync amplitude 0.1 0.3 0.6 V td(sync) delay from CVBS to TCS output from STTV buffer (nominal video, average of leading/trailing edge) −150 0 +150 ns ∆td(sync) change in sync delay between all black and all white video input at nominal levels 0 − 25 ns Vvid(p-p) video input amplitude (peak-to-peak value) 0.7 1.0 1.4 V Inputs CVBS display PLL catching range ±7 − − % Zsource source impedance − − 250 Ω Ci input capacitance − − 10 pF resistor to ground − 27 − kΩ VIL LOW level input voltage −0.3 − +0.8 V VIH HIGH level input voltage 2.0 − VDD + 0.5 V ILI input leakage current −10 − +10 µA Ci input capacitance − − 10 pF VIL LOW level input voltage −0.3 − +0.8 V VIH HIGH level input voltage 2.0 − VDD + 0.5 V ILI input leakage current Vi = 0 to VDD −10 − +10 Ii input current note 1 −1 − +1 mA td(LFB) delay between LFB front edge and input video line sync − 250 − ns VIL LOW level input voltage −0.3 − +0.8 V VIH HIGH level input voltage 2.0 − VDD + 0.5 V ILI input leakage current Vi = 0 to VDD −10 − +10 µA Ii input current note 1 −1 − +1 mA IREF Rgnd POL Vi = 0 to VDD LFB µA VCR/FFB 1996 Nov 07 10 Philips Semiconductors Preliminary specification Integrated VIP and Teletext with Background Memory Controller SYMBOL PARAMETER SAA5249 CONDITIONS MIN. TYP. MAX. UNIT RGBREF note 2 VIL LOW level input voltage ILI input leakage current IDC DC current Vi = 0 to VDD −0.3 − VDD + 0.5 V −10 − +10 µA − − 10 mA −0.3 − +0.8 V 2.0 − VDD + 0.5 V −10 − +10 µA V SEL1 AND SEL2 VIL LOW level input voltage VIH HIGH level input voltage ILI input leakage current Vi = 0 to VDD SCL VIL LOW level input voltage −0.3 − +1.5 VIH HIGH level input voltage 3.0 − VDD + 0.5 V ILI input leakage current −10 − +10 fSCL clock frequency 0 − 100 kHz tr input rise time 10% to 90% − − 2 µs tf input fall time 90% to 10% − − 2 µs Ci input capacitance − − 10 pF MHz Vi = 0 to VDD µA Inputs/outputs CRYSTAL OSCILLATOR (OSCIN; OSCOUT) fXTAL crystal frequency − 27 − Gv small signal voltage gain 3.5 − − Gm mutual conductance 1.5 − − Ci input capacitance − − 10 pF CFB feedback capacitance − − 5 pF Cblk storage capacitor to ground − 100 − nF ILI input leakage current −10 − +10 µA V fi = 100 kHz mA/V BLACK Vi = 0 to VDD SDA VIL LOW level input voltage −0.3 − +1.5 VIH HIGH level input voltage 3.0 − VDD + 0.5 V ILI input leakage current −10 − +10 µA Ci input capacitance − − 10 pF tr input rise time 10% to 90% − − 2 µs tf input fall time 90% to 10% − − 2 µs VOL LOW level output voltage IOL = 3 mA 0 − 0.5 V tf output fall time 3 V to 1 V − − 200 ns CL load capacitance − − 400 pF 1996 Nov 07 Vi = 0 to VDD 11 Philips Semiconductors Preliminary specification Integrated VIP and Teletext with Background Memory Controller SYMBOL PARAMETER SAA5249 CONDITIONS MIN. TYP. MAX. UNIT D0 TO D3 VIL LOW level input voltage −0.3 − +0.8 VIH HIGH level input voltage 2.0 − VDD + 0.5 V ILI input leakage current −10 − +10 µA Ci input capacitance − − 10 pF VOL LOW level output voltage IOL = +1.6 mA 0 − 0.4 V VOH HIGH level output voltage IOH = −0.2 mA 2.4 − VDD V tr output rise time 0.6 to 2.2 V − − 20 ns tf output fall time 2.2 to 0.6 V − − 20 ns CL load capacitance − − 50 pF Gstt gain of STTV relative to video input 0.9 1.0 1.1 VTCS TCS amplitude 0.2 0.3 0.45 V VDCs DC shift between TCS output and nominal video output − − 0.15 V IO output drive current − − 3.0 mA CL load capacitance − − 100 pF V Outputs STTV A0 TO A9 ADDRESS OUTPUT TO MEMORY A0 TO A9 VOL LOW level output voltage IOL = +1.6 mA 0 − 0.4 V VOH HIGH level output voltage IOH = −0.2 mA 2.4 − VDD V CL load capacitance − − 50 pF tr output rise time 0.6 to 2.2 V − − 20 ns tf output fall time 2.2 to 0.6 V − − 20 ns R/W, CASO AND CAS1 VOL LOW level output voltage IOL = +1.6 mA 0 − 0.4 V VOH HIGH level output voltage IOH = −0.2 mA 2.4 − VDD V CL load capacitance − − 50 pF tr output rise time 0.6 to 2.2 V − − 20 ns tf output fall time 2.2 to 0.6 V − − 20 ns 1996 Nov 07 12 Philips Semiconductors Preliminary specification Integrated VIP and Teletext with Background Memory Controller SYMBOL PARAMETER SAA5249 CONDITIONS MIN. TYP. MAX. UNIT R, G AND B − 0.2 V RGBREF RGBREF +0.25 V − − 200 Ω load capacitance − − 50 pF DC current − − −3.3 mA 10% to 90% − − 20 ns 90% to 10% − − 20 ns VOL LOW level output voltage IOL = 2 mA VOH HIGH level output voltage IOH = −1.6 mA; RGBREF RGBREF ≤ VDD − 2 V −0.25 0 |Zo| output impedance CL IDC tr output rise time tf output fall time BLANK VOL LOW level output voltage IOL = 1.6 mA 0 − 0.4 V VOH HIGH level output voltage IOH = −0.2 mA; VDD = 4.5 V 1.1 − − V VOH HIGH level output voltage IOH = 0 mA; VDD = 5.5 V − − 2.8 V VOH allowed voltage at pin with external pull-up − − VDD V CL load capacitance − − 50 pF tr output rise time 10% to 90% − − 20 ns tf output fall time 90% to 10% − − 20 ns VOL LOW level output voltage IOL = +1.6 mA 0 − 0.4 V IOH = −0.2 mA 2.4 − VDD V − − 120 pF ODD/EVEN VOH HIGH level output voltage CL load capacitance tr output rise time 0.6 to 2.2 V − − 50 ns tf output fall time 2.2 to 0.6 V − − 50 ns − − VDD V COR AND Y (OPEN-DRAIN) VOH pull-up voltage at pin VOL output voltage LOW CL load capacitance tf 0 − 1.0 V − − 25 pF output fall time load resistor of 1.2 kΩ − to VDD; measured between VDD − 0.5 V and 1.5 V − 50 ns ILO output leakage current Vi = 0 to VDD tskew skew delay between display outputs R, G, B, COR, Y and BLANK 1996 Nov 07 IOL = 5 mA 13 −10 − +10 µA − − 20 ns Philips Semiconductors Preliminary specification Integrated VIP and Teletext with Background Memory Controller SYMBOL PARAMETER SAA5249 CONDITIONS MIN. TYP. MAX. UNIT Timing DRAM INTERFACE tRC read or write cycle time 344 380 415 ns tRP RAS precharge time 125 140 155 ns tRAS RAS pulse width 194 210 230 ns tCAS CAS pulse width 113 133 153 ns tASR row address set-up time 30 60 80 ns tRAH row address hold time 50 60 92 ns tASC column address set-up time 50 60 75 ns tCAH column address hold time 50 60 70 ns tRCD RAS to CAS delay time 130 148 160 ns tRAD RAS to column address delay time 60 74 105 ns tRSH RAS hold time 15 60 70 ns tCSH CAS hold time 260 286 300 ns tCRP CAS to RAS precharge time 60 70 80 ns tDZO CAS set-up time from data input 200 225 280 ns tr, tf rise and fall times 10 15 20 ns tWCS write set-up time 193 212 235 ns tWCH write command hold time 116 137 150 ns tDS data input set-up time 193 212 235 ns tDH data input hold time 42 62 80 ns tRAC access time from RAS 165 183 220 ns tCAC access time from CAS 0 35 40 ns tAA access time from address 95 108 120 ns tRCS read command set-up time 193 212 235 ns tRCH read command hold time to CAS 0 10 20 ns tRRH read command hold time to RAS 55 65 100 ns tRAL column address to RAS lead time 90 133 150 ns tOFF1 output buffer turn-off time 20 30 40 ns tCDD CAS to data input delay time 25 35 45 ns 1996 Nov 07 14 Philips Semiconductors Preliminary specification Integrated VIP and Teletext with Background Memory Controller SYMBOL PARAMETER SAA5249 CONDITIONS MIN. TYP. MAX. UNIT I2C-BUS tLOW clock LOW period 4 − − µs tHIGH clock HIGH period 4 − − µs tSU;DAT data set-up time 250 − − ns tHD;DAT data hold time 170 − − ns tSU;STO set-up time from clock HIGH to STOP 4 − − µs tBUF START set-up time following a STOP 4 − − µs tHD;STA START hold time 4 − − µs tSU;STA START set-up time following clock LOW-to-HIGH transition 4 − − µs Notes 1. This current is the maximum allowed into the inputs when line and field flyback signals are connected to these inputs. Series current limiting resistors must be used to limit the input currents to ±1 mA. 2. RGBREF is the positive supply pin for the RGB output pins and it must be able to source the IOH current from the R, G and B pins. The leakage specification on RGBREF only applies when there is no current load on the RGB pins. 1996 Nov 07 15 1996 Nov 07 16 0 0 2.33 TCS non-interlaced TCS interlaced TCS interlaced BP (Broad Pulse) EP (Equalizing Pulse) LSP (Line Sync Pulse) 308 309 621 (308) 4.66 309 310 622 (309) 310 311 623 (310) 312 313 625 (312) 1 314 (1) 1 3 316 (3) 315 (2) 2 3 34.33 2 32 32 Fig.4 Composite sync waveforms. 311 312 624 (311) 27.33 handbook, full pagewidth 0 4 317 (4) 4 5 318 (5) 5 6 319 (6) 6 7 320 (7) 7 59.33 MLA037 - 2 64 µs 64 µs 64 µs Philips Semiconductors Preliminary specification Integrated VIP and Teletext with Background Memory Controller SAA5249 Philips Semiconductors Preliminary specification Integrated VIP and Teletext with Background Memory Controller SAA5249 handbook, full pagewidth LSP (TCS) 0 64 µs 4.66 40 µs R, G, B, Y (1) display period 0 56.67 µs 16.67 lines 42 to 291 inclusive (and 355 to 604 inclusive interlaced) R, G, B, Y (1) display period 0 312 291 line numbers 41 MLA662 - 1 (1) Also BLANK in character and box blanking. Fig.5 Display output timing (a) line rate (b) field rate. handbook, full pagewidth SDA t LOW t BUF tf SCL t HD;STA tr t HD;DAT t HIGH t SU;DAT SDA MBC764 t SU;STA Fig.6 I2C-bus timing. 1996 Nov 07 17 t SU;STO Philips Semiconductors Preliminary specification Integrated VIP and Teletext with Background Memory Controller SAA5249 t RC t RAS RAS t RSH tf t RP t CAS t RCD t CRP t CSH CAS t ASR t RAL t RAD t RAH ADDRESS t ASC ROW COLUMN t CAH t RCS t RCH WE t CAC t AA DATA OUTPUT high impedance t RRH t OFF1 DATA VALID t RAC t DZO t CDD high impedance DATA INPUT MBA732 Fig.7 DRAM interface timing; read cycle. 1996 Nov 07 18 Philips Semiconductors Preliminary specification Integrated VIP and Teletext with Background Memory Controller SAA5249 t RC t RAS RAS t RSH tf t CAS t RCD t RP t CRP t CSH CAS t ASR ADDRESS t RAH tASC ROW COLUMN t CAH t WCS t WCH WE t DS DATA INPUT DATA OUTPUT t DH DATA VALID high impedance MBA731 Fig.8 DRAM interface timing; write cycle. 1996 Nov 07 19 1996 Nov 07 20 309 310 622 (309) 311 2 µs 623 (310) 313 625 (312) 31 µs 48 µs 2 3 315 (2) 31 µs 16 µs 314 (1) 316 (3) SECOND FIELD START (ODD) 1 Fig.9 ODD/EVEN timing. 2 µs 312 624 (311) 317 (4) 4 318 (5) 5 319 (6) 6 320 (7) 7 MBA073 - 4 Integrated VIP and Teletext with Background Memory Controller ODD/EVEN output (slave sync mode) ODD/EVEN output (normal sync mode when VCS to SCS mode active) ODD/EVEN output (normal sync mode) TCS interlaced ODD/EVEN output (slave sync mode) ODD/EVEN output (normal sync mode when VCS to SCS mode active) ODD/EVEN output (normal sync mode) TCS interlaced 621 (308) FIRST FIELD START (EVEN) Philips Semiconductors Preliminary specification SAA5249 1996 Nov 07 21 STTV CVBS VCR +5 V C3 100 nF 5 4 3 2 KEY 1 X2 4 3 n.c. LK2 LINK LK1 LINK 1 NOTE : FOR +VE GOING SYNC FIT LK1 FOR - VE GOING SYNC FIT LK2 R1 10 kΩ KEY 2 +5 V X3 1 X1 KEY R3 1 kΩ R2 1 kΩ +5 V R 3 X4 B D 1 GND 4 3 SDA R6 4.7 kΩ +5 V R10 4.7 kΩ LK4 LINK LK3 LINK R8 220 Ω +5 V 46 45 47 43 48 44 39 36 34 32 25 26 33 35 37 40 42 41 23 24 R9 4.7 kΩ C10 100 nF COR ODD/EVEN D3 BLANK D2 B D1 G D0 R A8 Y A7 VCR A6 CVBS A5 STTV A4 BLACK A3 RGBREF A2 VSS2 A1 POL A0 OSCOUT A9 OSCIN R/W REF + RAS V SS1 CAS0 GNDO CAS1 IREF SCL SEL1 SDA SEL2 VSS3 , VSS4 R7 220 Ω R9 27 kΩ 27 28 21 19 18 17 29 15 10 14 9 20 16 13 4 5 8 7 6 11 30 31 22, 38 12 V DD2 3 V DD1 IC1 SAA5249 MLB307 C1 C2 100 nF 33 µF LINK 3 4 DRAM (120 nS) IC2 IC3 256K x 4 256K x 4 256K x 4 1M x 4 - IC2 IC3 D3 15 D2 V CC D1 D0 5 A8 V SS A7 1 A6 OE A5 A4 A3 A2 A1 A0 A9 WE RAS CAS C12 10 µF C11 100 nF C13 100 nF IC2 and IC3 pin-outs are for Dual In-Line Package (DIP) D3 15 D2 V CC C14 D1 100 D0 nF 5 A8 V SS A7 1 A6 OE A5 A4 A3 A2 C13 and C14 A1 are optional A0 surface mounted capacitors mounted 8 WE close to IC 9 RAS 2 CAS 4 3 7 6 10 20 19 18 17 16 14 13 12 4 3 7 6 20 19 18 17 15 14 13 12 11 10 8 9 2 +5 V Integrated VIP and Teletext with Background Memory Controller Fig.10 Application diagram; 1 or 4 Mbit DRAM. 2 SCL R5 4.7 kΩ 6 C9 L1 100 nF 3.3 µH C8 100 nF 5 BLANKING ODD/EVEN G1 27 MHz C7 1 nF C5 8.2 pF C7 R11 15 pF 3.3 kΩ C4 100 nF 2 G KEY GND Philips Semiconductors Preliminary specification SAA5249 APPLICATION INFORMATION Philips Semiconductors Preliminary specification Integrated VIP and Teletext with Background Memory Controller SAA5249 IVT1.1BMCX page memory organization The organization of the page memory is illustrated by Fig.11. The IVT1.1BMCX provides an additional row as compared with first generation decoders; this brings the display format up to 40 characters by 25 rows. Rows 0 to 23 form the teletext page; Row 24 is the extra row available for software generated status messages and FLOF/FASTEXT prompt information. 7 characters for status 7 fixed character written by IVT hardware alphanumerics white for normal alphanumerics green when looking for display page 8 characters always rolling (time) 24 8 1 24 characters from page header rolling when display page looked for MAIN PAGE DISPLAY AREA 14 bytes free for use by microcontroller 0 1 2 3 4 5 to 20 21 22 23 24 25 PACKET X / 22 PACKET X / 23 PACKET X / 24 STORED HERE IF R0D7 = 1 10 14 10 bytes for received page information ROW MBA274 Fig.11 Basic page memory organization. REMARK TO Fig.11 Row 0 Row 0 is for the page header. The first seven columns (0 to 6) are free for status messages. The eighth is an alphanumeric white or green control character, written automatically by IVT1.1BMCX to give a green rolling header when a page is being looked for. The last eight characters are for rolling time. ROW PACKET X / 24 if R0D7 = 0 0 PACKET X / 27 / 0 1 PACKETS 8 / 30 / 0 to 15 2 MBA275 - 2 Row 25 The first 10 bytes of row 25 contain control data relating to the received page as shown in Table 5. The remaining 14-bytes are free for use by the microcomputer. Fig.12 Organization of the extension memory. 1996 Nov 07 22 Philips Semiconductors Preliminary specification Integrated VIP and Teletext with Background Memory Controller Table 5 SAA5249 Row 25 received control data format D0 PU0 PT0 MU0 MT0 HU0 HT0 C7 C11 MAG0 0 D1 PU1 PT1 MU1 MT1 HU1 HT1 C8 C12 MAG1 0 D2 PU2 PT2 MU2 MT2 HU2 C5 C9 C13 MAG2 0 D3 PU3 PT3 MU3 C4 HU3 C6 C10 C14 0 0 D4 HAM.ER HAM.ER HAM.ER HAM.ER HAM.ER HAM.ER HAM.ER HAM.ER FOUND 0 D5 0 0 0 0 0 0 0 0 0 PBLF D6 0 0 0 0 0 0 0 0 0 0 D7 0 0 0 0 0 0 0 0 0 0 Column 0 1 2 3 4 5 6 7 8 9 Table 6 Page number and sub-code for Table 5 Page number MAG magazine PU page units PT page tens PBLF page being looked for FOUND LOW for page has been found HAM.ER hamming error in corresponding byte Page sub-code MU minutes units MT minutes tens HU hours units HT hours tens C4 to C14 transmitted control bits 1996 Nov 07 23 Philips Semiconductors Preliminary specification Integrated VIP and Teletext with Background Memory Controller SAA5249 Register maps IVT1.1BMCX mode registers R0 to R11 are shown in Table 7. R0 to R10 are write only; R11 is read/write. Register map (R3), for page requests, is shown in detail in Table 9. Table 7 Register map (notes 1 to 5) REGISTER D7 D6 D5 D4 D3 D2 D1 D0 AUTO ODD/ EVEN DISABLE HDR ROLL DISPLAY SRATUS ROW ONLY DISABLE ODD/ EVEN − R11/R11B SELECT 7 + P/ 8-BIT ACQ ON/OFF DISABLE PKT 26 DEW/ FULL FIELD TCS ON T1 T0 − − − − TB START START START COLUMN COLUMN COLUMN SC2 SC1 SC0 − − CLEAR B.M. PRD4 PRD3 PRD2 PRD1 PRD0 − − − − − − − − Adv. control 0 X24 POS FREE RUN PLL Mode 1 VCS TO SCS Page request address 2 Page request data 3 Display control (normal) 5 BKGND OUT BKGND IN COR OUT COR IN TEXT OUT TEXT IN PON OUT PON IN Display control (newsflash /subtitle) 6 BKGND OUT BKGND IN COR OUT COR IN TEXT OUT TEXT IN PON OUT PON IN Display mode 7 STATUS CURSOR BTM ON TOP CONCEA TOP/BTM L REVEAL HALF ON SINGLE DOUBLE HEIGHT BOX ON 24 BOX ON 1-23 BOX ON 0 − − − − − − − − Cursor row 9 − CLEAR MEM. A0 R4 R3 R2 R1 R0 Cursor column 10 − − C5 C4 C3 C2 C1 C0 Cursor data 11 Device status 1996 Nov 07 D7 11B 625/525 SYNC D6 D5 D4 D3 D2 D1 D0 ROM VER R4 ROM VER R3 ROM VER R2 ROM VER R1 ROM VER R0 TEXT SIGNAL QUALITY VCS SIGNAL QUALITY 24 Philips Semiconductors Preliminary specification Integrated VIP and Teletext with Background Memory Controller SAA5249 Notes 1. The dash (−) indicates these bits are inactive and must be written to logic 0 for future compatibility. 2. All bits in registers R0 to R10 are cleared to logic 0 on power-up except bits D0 and D1 of Registers R1, R5 and R6 which are set to logic 1. 3. All memory is cleared to space (00100000) on power-up, except Row 0 Column 7 Chapter 0, which is alpha white (00000111) as the acquisition circuit is enabled but the page is on hold. 4. TB must be set to logic 0 for normal operation. 5. The I2C-bus slave address is 0010001. Table 8 Register description R0 ADVANCED CONTROL - auto increments to register 1 R11/R11B SELECT selects reading of R11 or R11B DISABLE ODD/EVEN forces ODD/EVEN output LOW when logic 1 DISPLAY STATUS ROW when SET = 1 and R1D6 = 1 open (8-bit mode) then all the text display is blanked out apart from the status row, this allows the page memory to be used for non-textural data, such as in the German TOP system DISABLE HDR ROLL disables green rolling header and time AUTO ODD/EVEN when set forces ODD/EVEN LOW if any TV picture displayed, if DISABLE ODD/EVEN = 0 FREE RUN PLL will force the PLL to free run in all conditions X24 POS automatic display of FASTEXT prompt row when logic 1 R1 MODE - auto increments to register 2 T0, T1 interlace/non-interlace 312/313 line control (see Table 10) TCS ON text composite sync or direct sync select (see Table 10 for FFB mode selection) DEW/FULL FIELD field-flyback or full-channel mode DISABLE PKT 26 disable automatic processing of packet 26 ACQ ON/OFF acquisition circuits turned off when logic 1 7 + P/8-BIT 7-bits with parity checking or 8-bit mode VCS TO SCS when logic 1 enables display of messages with 60 Hz input signal R2 PAGE REQUEST ADDRESS - auto increments to register 3 COL SCO - SC2 point to start column for page request data (see Table 9) TB must be logic 0 for normal operation R3 PAGE REQUEST DATA - does not auto increment (see Table 9) CLEAR B.M. when set to logic 1. Useful when transmission channel changes R5 NORMAL DISPLAY CONTROL - auto increments to register 6 R6 NEWSFLASH/SUBTITLE DISPLAY CONTROL - auto increments to register 7; (note 1) PON picture on TEXT text on COR contrast reduction on BKGND background colour on 1996 Nov 07 25 Philips Semiconductors Preliminary specification Integrated VIP and Teletext with Background Memory Controller SAA5249 R7 DISPLAY MODE - does not auto increment BOX ON 0 boxing function allowed on Row 0 BOX ON 1-23 boxing function allowed on Rows 1 to 23 BOX ON 24 boxing function allowed on Row 24 DOUBLE HEIGHT to display double height text BOTTOM HALF to select bottom half of page when DOUBLE HEIGHT = 1 REVEAL ON to reveal concealed text CURSOR ON to display cursor STATUS TOP row 25 displayed above or below the main text R9 CURSOR ROW - auto increments to register 10 R0 to R4 active row for data written to or read from memory via the I2C-bus A0 selects display memory page (when = 0) or extension packet memory (when = 1) CLEAR MEM. when set to 1, clears the display memory; this bit is automatically reset R10 CURSOR COLUMN - auto increments to register 11 or 11B C0 to C5 active column for data written to or read from memory via the I2C-bus R11 CURSOR DATA - does not auto increment D0 to D7 data read from/written to memory via I2C-bus, at location pointed to by R9 and R10. This location automatically increments each time R11 is accessed R11B DEVICE STATUS - does not auto increment VCS SIGNAL QUALITY indicates that the video signal quality is good and PLL is phase locked to input video when = 1 TEXT SIGNAL QUALITY if a good teletext signal is being received when logic 1 ROM VER R0 to R4 indicated language/ROM variant. For Western European = 11 000 625/525 SYNC if the input video is a 525 line signal when logic 1 Note 1. These functions have IN and OUT referring to inside and outside the boxing function respectively. 1996 Nov 07 26 Philips Semiconductors Preliminary specification Integrated VIP and Teletext with Background Memory Controller Table 9 SAA5249 Register map for page requests (R3); notes 1 to 5 START COLUMN PRD4 0 DO CARE magazine 1 DO CARE 2 DO CARE PRD3 PRD2 PRD1 PRD0 HOLD MAG2 MAG1 MAG0 PT3 PT2 PT1 PT0 PU3 PU2 PU1 PU0 X X HT1 HT0 HU3 HU2 HU1 HU0 X MT2 MT1 MT0 MU3 MU2 MU1 MU0 page tens page units 3 DO CARE hours tens 4 DO CARE hours units 5 DO CARE minutes tens 6 DO CARE minutes units Notes 1. Abbreviations are as for Table 5 except for DO CARE bits. 2. When the DO CARE bit is set to logic 1 this means the corresponding digit is to be taken into account for page requests. If the DO CARE bit is set to logic 0 the digit is ignored. This allows, for example, normal or timed page selection. 3. If HOLD is set LOW, the page is held and not updated. 4. Columns auto-increment on successive I2C-bus transmission bytes. 5. X = don't care. Table 10 Interlace/non-interlace 312/313 line control and ODD/EVEN field detection option; notes 1 and 2 TCS ON FFB MODE T1 T0 X 0 0 interlaced 312.5/312.5 lines X 0 1 non-interlaced 312/313 lines (note 1) X 1 0 non-interlaced 312/313 lines (note 1) 0 1 1 SCS (scan composite sync) mode: FFB leading edge in first broad pulse of field 1 1 1 SCS (scan composite sync) mode: FFB leading edge in second broad pulse of field RESULT Notes 1. Reverts to interlaced mode if a newsflash or subtitle is being displayed. 2. X = Don't care. 1996 Nov 07 27 Philips Semiconductors Preliminary specification Integrated VIP and Teletext with Background Memory Controller SAA5249 CLOCK SYSTEMS Crystal oscillator The crystal is a conventional 2-pin design operating at 27 MHz. It is capable of oscillating with both fundamental and third overtone mode crystals. External components should be used to suppress the fundamental output of the third overtone as illustrated in Fig.13. VDD1 OSCOUT 3 (25) SAA5249 4 (27) 15 pF 8.2 pF 100 nF 3.3 kΩ CRYSTAL OSCILLATOR 3.3 µH OSCIN 27 MHz 3rd overtone GNDO 1 nF 5 (28) 6 (29) MLB308 Fig.13 Crystal oscillator application diagram for SOT240-1; pins in parenthesis are for SOT319-1. Table 11 Crystal characteristics (see Fig.13) SYMBOL PARAMETER MIN. TYP. MAX. UNIT Crystal (27 MHz, 3rd overtone) C1 series capacitance − 1.7 − pF C0 parallel capacitance − 5.2 − pF CL load capacitance − 20 − pF Rr resonance resistance − − 50 Ω R1 series resistance − 20 − Ω Xa ageing − − ±5 10−6/year Xj adjustment tolerance − − ±25 10−6 Xd drift − − ±25 10−6 1996 Nov 07 28 Philips Semiconductors Preliminary specification Integrated VIP and Teletext with Background Memory Controller SAA5249 CHARACTER SETS The WST specification allows the selection of national character sets via the page header transmission bits, C12 to C14. The basic 96 character sets differ only in 13 national option characters as indicated in the Tables 16, 17 and 18 with reference to their table position in the basic character matrix illustrated in Table 15. The IVT1.1BMCX automatically decodes transmission bits C12 to C14. Tables 12, 13 and 14 illustrate the character matrixes. Character bytes are listed as transmitted from b1 to b7. MLA663 handbook, full pagewidth alphanumerics and graphics 'space' character 0000010 alphanumerics character 1011010 alphanumerics or blast-through alphanumerics character 0001001 alphanumerics character 1111111 contiguous graphics character 0110111 separated graphics character 0110111 separated graphics character 1111111 contiguous graphics character 1111111 = background colour Fig.14 Character format. 1996 Nov 07 29 display = colour Philips Semiconductors Preliminary specification Integrated VIP and Teletext with Background Memory Controller SAA5249 Table 12 SAA5249P/E character data input decoding, West European languages; notes 1 to 9 For character version number (11000) see Register 11B. b8 B pagewidth handbook, full I T S 0 0 b7 0 b6 0 or 1 0 0 0 b5 0 0 b 4 b 3 b2 b 1 column r o w 0 1 1 0 0 0 0 0 0 0 1 1 alpha numerics red graphics red 0 0 1 0 2 alpha numerics green graphics green 0 0 1 1 3 alpha numerics yellow graphics yellow 0 1 0 0 4 alpha numerics blue graphics blue 0 1 0 1 5 alpha numerics magenta graphics magenta 0 1 1 0 6 alpha numerics cyan graphics cyan 0 1 1 1 7 alpha numerics white graphics white 1 0 0 0 8 flash conceal display 1 0 0 1 9 steady 1 0 1 0 10 end box separated graphics 1 0 1 1 11 start box ESC 1 1 0 0 12 normal height 1 1 0 1 13 double height 1 1 1 0 14 SO 1 1 1 1 15 SI graphics black 0 0 1 0 2 0 0 or 1 0 1 alpha numerics black 0 1 1 2a 0 0 1 1 3 0 1 0 1 3a 0 0 0 4 5 1 1 1 6a 1 0 1 7 7a 1 0 0 1 0 6 1 0 1 1 0 0 8 1 1 0 1 9 1 1 0 0 12 1 1 1 1 1 13 1 0 14 1 15 (2) (2) (2) contiguous graphics (2) (1) (2) black back ground (2) new back ground (1) hold graphics (1) (2) release graphics MBA429 1996 Nov 07 30 Philips Semiconductors Preliminary specification Integrated VIP and Teletext with Background Memory Controller SAA5249 Table 13 SAA5249P/H character data input decoding, West European languages; notes 1 to 9 For character version number (11001) see Register 11B. handbook, full B pagewidth b8 I T S 0 0 b7 0 b6 4 b 3 b 2 b 0 0 b5 b 0 or 1 0 0 0 1 column r o w 1 0 1 graphics black 0 0 0 0 0 0 0 1 1 alpha numerics red graphics red 0 0 1 0 2 alpha numerics green graphics green 0 0 1 1 3 alpha numerics yellow graphics yellow 0 1 0 0 4 alpha numerics blue graphics blue 0 1 0 1 5 alpha numerics magenta graphics magenta 0 1 1 0 6 alpha numerics cyan graphics cyan 0 1 1 1 7 alpha numerics white graphics white 1 0 0 0 8 flash conceal display 1 0 0 1 9 steady 1 0 1 0 10 end box separated graphics 1 0 1 1 11 start box ESC 1 1 0 0 12 normal height 1 1 0 1 13 double height 1 1 1 0 14 SO 1 1 1 1 15 SI 0 0 1 0 2 0 0 or 1 0 1 alpha numerics black 0 1 0 2a 0 0 1 1 3 0 1 0 1 3a 0 0 0 4 5 1 1 1 6a 1 0 1 7 7a 1 0 0 1 0 6 1 0 1 1 0 0 8 1 1 0 1 9 1 1 0 0 12 1 1 1 1 1 13 1 0 14 1 15 (2) (2) (2) contiguous graphics (2) (1) (2) black back ground (2) new back ground (1) hold graphics (1) (2) release graphics MLA961 1996 Nov 07 31 Philips Semiconductors Preliminary specification Integrated VIP and Teletext with Background Memory Controller SAA5249 Table 14 SAA5249P/T character data input decoding, West European and Turkish languages; notes 1 to 9 For character version number (11010) see Register 11B. handbook, full b8 B pagewidth I T S 0 0 b7 0 b6 0 or 1 0 0 0 b5 0 0 b 4 b 3 b2 b 1 column r o w 1 0 1 graphics black 0 0 0 0 0 0 0 1 1 alpha numerics red graphics red 0 0 1 0 2 alpha numerics green graphics green 0 0 1 1 3 alpha numerics yellow graphics yellow 0 1 0 0 4 alpha numerics blue graphics blue 0 1 0 1 5 alpha numerics magenta graphics magenta 0 1 1 0 6 alpha numerics cyan graphics cyan 0 1 1 1 7 alpha numerics white graphics white 1 0 0 0 8 flash conceal display 1 0 0 1 9 steady 1 0 1 0 10 end box separated graphics 1 0 1 1 11 start box ESC 1 1 0 0 12 normal height 1 1 0 1 13 double height 1 1 1 0 14 SO 1 1 1 1 15 SI 0 0 1 0 2 0 0 or 1 0 1 alpha numerics black 0 1 1 2a 0 0 1 1 3 0 1 0 1 3a 0 0 0 4 5 1 1 1 6a 1 0 1 7 7a 1 0 0 1 0 6 1 0 1 1 0 0 8 1 1 0 1 9 1 1 0 0 12 1 1 1 1 1 13 1 0 14 1 15 (2) (2) (2) contiguous graphics (2) (1) (2) black back ground (2) new back ground (1) hold graphics (1) (2) release graphics MBA431 1996 Nov 07 32 Philips Semiconductors Preliminary specification Integrated VIP and Teletext with Background Memory Controller SAA5249 Table 15 SAA5249P/R character data input decoding, Baltic and Cyrillic languages; notes 1 to 9 For character version number (11101) see Register 11B. B I T S b8 0 0 b7 0 b6 4 b 3 b 2 b 0 0 b5 b 0 or 1 0 1 column r o w 0 1 0 1 graphics black 0 0 0 0 0 0 0 0 1 1 alpha numerics red graphics red 0 0 1 0 2 alpha numerics green graphics green 0 0 1 1 3 alpha numerics yellow graphics yellow 0 1 0 0 4 alpha numerics blue graphics blue 0 1 0 1 5 alpha numerics magenta graphics magenta handbook, full pagewidth 0 1 1 0 6 alpha numerics cyan graphics cyan 0 0 1 0 2 alpha numerics black 0 or 1 0 1 0 0 1 1 2a 0 0 1 1 3 0 1 0 1 3a 0 1 0 0 4 6a 1 0 1 0 6 1 1 1 1 5 0 1 0 7a 8 1 1 0 0 1 7 1 0 0 1 9 1 1 0 0 12 1 1 1 1 1 13 1 0 14 1 15 (2) 0 1 1 1 7 alpha numerics white graphics white 1 0 0 0 8 flash conceal display 1 0 0 1 9 steady 1 0 1 0 10 end box separated graphics 1 0 1 1 11 start box TWIST (2) (2) contiguous graphics (2) (2) 1 1 0 0 12 normal height 1 1 0 1 13 double height 1 1 1 0 14 SO 1 1 1 1 15 SI black back ground (2) new back ground (1) hold graphics (1) (2) release graphics MBA648 - 1 1996 Nov 07 33 Philips Semiconductors Preliminary specification Integrated VIP and Teletext with Background Memory Controller SAA5249 Notes to Tables 12, 13, 14 and 15 1. These control characters are reserved for compatibility with other data codes. 2. These control characters are presumed before each row begins. 3. Control characters shown in Columns 0 and 1 are normally displayed as spaces. 4. Characters may be referred to by column and row (for example 2/5 refers to %). 5. Black represents displayed colour. White represents background. 6. The SAA5249 national option characters are illustrated in Tables 16, 17,18 and 19. 7. Characters 8/6, 8/7, 9/5, 9/6 and 9/7 are special characters for combining with character 8/5 (E, H and T codes only). 8. National option characters will be displayed according to the setting of control bits C12 to C14. These will be mapped into the basic code table into positions shown in Tables 16, 17, 18 and 19. 9. Columns 2a, 3a, 6a and 7a are displayed in graphics mode. 1996 Nov 07 34 1996 Nov 07 35 2/14 2/15 2/6 2/7 3/7 3/6 3/5 3/4 3/3 3/2 3/1 3/0 3/15 3/14 3/13 3/12 3/11 3/10 3/9 3/8 4/7 4/6 4/5 4/4 4/3 4/2 4/1 4/0 NC 4/15 4/14 4/13 4/12 4/11 4/10 4/9 4/8 5/7 5/6 5/5 5/4 5/3 5/2 5/1 5/0 NC 5/15 NC 5/14 NC 5/13 NC 5/12 NC 5/11 5/10 5/9 5/8 6/7 6/6 6/5 6/4 6/3 6/2 6/1 6/0 NC 6/15 6/13 6/12 6/11 6/10 6/9 6/8 7/7 7/6 7/5 7/4 7/3 7/2 7/1 7/0 7/15 MLA630 NC 7/14 NC 7/13 NC 7/12 NC 7/11 7/10 7/9 7/8 Integrated VIP and Teletext with Background Memory Controller 1. Where: NC = national option character position. Note 2/13 2/5 NC 2/11 2/3 2/12 2/10 2/2 2/4 2/9 2/1 NC 2/8 2/0 Table 16 SAA5249 basic character matrix; note 1 Philips Semiconductors Preliminary specification SAA5249 full pagewidth Philips Semiconductors Preliminary specification Integrated VIP and Teletext with Background Memory Controller SAA5249 Table 17 SAA5249P/E national option character set; note 1 handbook, full pagewidth PHCB (1) CHARACTER POSITION (COLUMN / ROW) LANGUAGE C12 C13 C14 2 / 3 ENGLISH 0 0 0 GERMAN 0 0 1 SWEDISH 0 1 0 ITALIAN 0 1 1 FRENCH 1 0 0 SPANISH 1 0 1 2/4 4/0 5 / 11 5 / 12 5 / 13 5 / 14 5 / 15 6/0 7 / 11 7 / 12 7 / 13 7 / 14 MLB458 Note 1. PHCB are the Page Header Control Bits. Other combinations default to English. 1996 Nov 07 36 Philips Semiconductors Preliminary specification Integrated VIP and Teletext with Background Memory Controller SAA5249 Table 18 SAA5249P/H national option character set; note 1 handbook, full pagewidth PHCB (1) CHARACTER POSITION (COLUMN / ROW) LANGUAGE C12 C13 C14 2 / 3 POLISH 0 0 0 GERMAN 0 0 1 SWEDISH 0 1 0 SERBO-CROAT 1 0 1 CZECHOSLOVAKIA 1 1 0 RUMANIAN 1 1 1 2/4 4/0 5 / 11 5 / 12 5 / 13 5 / 14 5 / 15 6/0 7 / 11 7 / 12 7 / 13 7 / 14 MLA966 Note 1. PHCB are the Page Header Control Bits. Other combinations default to German. Only the above characters change with the PHCB. All other characters in the basic set are shown in Table 15. 1996 Nov 07 37 Philips Semiconductors Preliminary specification Integrated VIP and Teletext with Background Memory Controller SAA5249 Table 19 SAA5249P/R national option character set; note 1 handbook, full pagewidth PHCB (1) CHARACTER POSITION (COLUMN / ROW) LANGUAGE C12 C13 C14 2 / 3 ESTONIAN 0 1 0 LETTISH / LITHUANIAN 0 1 1 RUSSIAN 1 0 0 2 2/4 4/0 3 4 5 / 11 5 / 12 5 / 13 5 / 14 5 / 15 5 6 6 / 0 7 / 11 7 / 12 7 / 13 7 / 14 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 MEA597 Note 1. PHCB are the Page Header Control Bits. Other combinations default to Estonian. 1996 Nov 07 38 Philips Semiconductors Preliminary specification Integrated VIP and Teletext with Background Memory Controller SAA5249 PACKAGE OUTLINES seating plane DIP48: plastic dual in-line package; 48 leads (600 mil) SOT240-1 ME D A2 L A A1 c e Z w M b1 (e 1) b MH 25 48 pin 1 index E 1 24 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.9 0.36 4.06 1.4 1.14 0.53 0.38 0.36 0.23 62.60 61.60 14.22 13.56 2.54 15.24 3.90 3.05 15.88 15.24 18.46 15.24 0.254 2.1 inches 0.19 0.014 0.16 0.055 0.045 0.021 0.015 0.014 0.009 2.46 2.42 0.56 0.53 0.10 0.60 0.15 0.12 0.63 0.60 0.73 0.60 0.01 0.083 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 92-11-17 95-01-25 SOT240-1 1996 Nov 07 EUROPEAN PROJECTION 39 Philips Semiconductors Preliminary specification Integrated VIP and Teletext with Background Memory Controller SAA5249 QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.7 mm; high stand-off height SOT319-1 c y X 51 A 33 52 32 ZE Q e E HE A A2 (A 3) A1 θ wM Lp pin 1 index bp L 20 64 detail X 19 1 w M bp e ZD v M A D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp Q v w y mm 3.3 0.36 0.10 2.87 2.57 0.25 0.50 0.35 0.25 0.13 20.1 19.9 14.1 13.9 1 24.2 23.6 18.2 17.6 1.95 1.0 0.6 1.43 1.23 0.2 0.2 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 θ Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 92-11-17 95-02-04 SOT319-1 1996 Nov 07 EUROPEAN PROJECTION 40 o 7 0o Philips Semiconductors Preliminary specification Integrated VIP and Teletext with Background Memory Controller SAA5249 Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary from 50 to 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheat for 45 minutes at 45 °C. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). WAVE SOLDERING Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. DIP SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. If wave soldering cannot be avoided, the following conditions must be observed: The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. • The footprint must be at an angle of 45° to the board direction and must incorporate solder thieves downstream and at the side corners. • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). REPAIRING SOLDERED JOINTS During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. QFP REFLOW SOLDERING A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Reflow soldering techniques are suitable for all QFP packages. REPAIRING SOLDERED JOINTS The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our “Quality Reference Handbook” (order code 9397 750 00192). 1996 Nov 07 Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 41 Philips Semiconductors Preliminary specification Integrated VIP and Teletext with Background Memory Controller SAA5249 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1996 Nov 07 42 Philips Semiconductors Preliminary specification Integrated VIP and Teletext with Background Memory Controller SAA5249 NOTES 1996 Nov 07 43 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 1949 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580/xxx France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstraße 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd. Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722 Indonesia: see Singapore Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 247 9145, Fax. +7 095 247 9144 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Rua do Rocio 220, 5th floor, Suite 51, 04552-903 São Paulo, SÃO PAULO - SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 829 1849 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH, Tel. +41 1 488 2686, Fax. +41 1 481 7730 Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West Road, Sec. 1, P.O. Box 22978, TAIPEI 100, Tel. +886 2 382 4443, Fax. +886 2 382 4444 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com © Philips Electronics N.V. 1996 SCA52 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 537021/50/02/pp44 Date of release: 1996 Nov 07 Document order number: 9397 750 01014