INTEGRATED CIRCUITS DATA SHEET SAA5252 Line twenty-one acquisition and display (LITOD) Product specification Supersedes data of March 1995 File under Integrated Circuits, IC02 1996 Jul 18 Philips Semiconductors Product specification Line twenty-one acquisition and display (LITOD) SAA5252 FEATURES • Complete ‘stand-alone’ Line 21 decoder in one package • On-chip display RAM allowing full page Text mode • Enhanced character display modes • Full colour captions • RGB interface for standard colour decoder ICs GENERAL DESCRIPTION • Automatic handling of Field 2 data The SAA5252 (LITOD) is a single-chip CMOS device, which will acquire, decode and display Line 21 Closed Captioning data from a 525-line composite video signal. Operation as an On-Screen Display (OSD) device is also possible. Normal and line progressive scan modes are supported. • Automatic selection of (1H, 1V), (2H, 1V) or (2H, 2V) scan modes • Onboard OSD facility using Character generator • RGB inputs to support existing OSD ICs • I2C-bus or ‘stand-alone’ pin control • Automatic data-ready signal generation on data acquisition • Can decode signals recorded on standard VHS and S-VHS tape. QUICK REFERENCE DATA SYMBOL PARAMETER MIN. TYP. MAX. UNIT VDD supply voltage 4.5 5.0 5.5 V IDD supply current − 30 − mA Vsyn CVBS sync amplitude 0.1 0.3 0.6 V Vvid CVBS video amplitude 0.7 1.0 1.4 V Tamb operating ambient temperature −20 − +70 °C Tstg storage temperature −55 − +125 °C ORDERING INFORMATION PACKAGE TYPE NUMBER NAME SAA5252P DIP24 plastic dual in-line package; 24 leads (600 mil) SOT101-1 SAA5252T SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 1996 Jul 18 DESCRIPTION 2 VERSION Philips Semiconductors Product specification Line twenty-one acquisition and display (LITOD) SAA5252 BLOCK DIAGRAM VSS 19 OSCIN OSCGND OSCOUT V DD 18 H 7 i.c. 8 6 17 DISPLAY TIMING 21 22 V 16 CHARACTER GENERATOR OSCILLATOR CHARACTER ROM ADDRESSING 20 SAA5252 15 ROUNDING ITALICS AND RGB MULTIPLEXOR 14 13 9 10 CODE INTERPRETER AND ADDRESSING 11 PAGE RAM 12 5 BLACK IREF CVBS 23 24 1 SYNC SEPARATOR AND ACQUISITION TIMING ADC I2C INTERFACE SERIAL/ PARALLEL AND PARITY DATA DETECTOR I 2 C/DC 1996 Jul 18 3 4 R G B BLANIN RIN GIN BIN DR SDA SCL CONTROL 2 Fig.1 Block diagram. 3 RGBREF BLAN MBB623 - 1 Philips Semiconductors Product specification Line twenty-one acquisition and display (LITOD) SAA5252 PINNING SYMBOL PIN DESCRIPTION CVBS 1 composite video input; signal should be connected via a 100 nF capacitor I2C/DC 2 input selects I2C or Direct Control SDA 3 serial data port for I2C-bus or mode select input for direct control SCL 4 serial clock input for I2C-bus or mode select input for direct control DR 5 data-ready signal to microcontroller (active-LOW) or mode select input for direct control i.c. 6 internally connected; connect to VSS for normal operation CVBS 1 24 IREF I 2 C/DC 2 23 BLACK SDA 3 22 OSCGND SCL 4 21 OSCIN DR 5 20 OSCOUT i.c. 6 V 7 vertical reference input for display timing H 8 horizontal reference input for display timing BLANIN 9 video blanking input from external OSD device RIN 10 RED video input from external OSD device GIN 11 GREEN video input from external OSD device BIN 12 BLUE video input from external OSD device RIN 10 15 B 13 BLUE video output GIN 11 14 G G 14 GREEN video output BIN 13 R 15 RED video output BLAN 16 video blanking output RGBREF 17 input voltage defining output HIGH level for RGB pins for closed captioning output VDD 18 +5 V supply VSS 19 0 V ground OSCOUT 20 oscillator output OSCIN 21 oscillator input OSCGND 22 oscillator ground BLACK 23 video black level storage input; connected to VSS via 100 nF capacitor IREF 24 reference current input; connected to VSS via 27 kΩ resistor 1996 Jul 18 19 VSS V DD SAA5252 V 7 18 H 8 17 RGBREF BLANIN 9 16 BLAN 12 R B MBB622 - 1 4 Fig.2 Pin configuration. Philips Semiconductors Product specification Line twenty-one acquisition and display (LITOD) SAA5252 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDD supply voltage (all supplies) −0.3 +6.5 VImax maximum input voltage (any input) note 1 −0.3 VDD + 0.5 V VOmax maximum output voltage (any output) note 1 − VDD + 0.5 V Vdif difference between VSS and OSCGND − ±0.25 V IIOK DC input or output diode current − ±20 mA IOmax maximum output current (each output) − ±10 mA Tamb operating ambient temperature −20 +70 °C Tstg storage temperature −55 +125 °C Ves electrostatic handling V human body model note 2 −2000 +2000 V machine model note 3 −200 +200 V Notes 1. This maximum value has an absolute maximum of 6.5 V independent of VDD. 2. The human body model ESD simulation is equivalent to discharging a 100 pF capacitor via a 1.5 kΩ resistor, which produces a single discharge transient. Reference “Philips Semiconductors Test Method UZW-BO/FQ-A302 (similar to MIL-STD 883C method 3015.7)”. 3. The machine model ESD simulation is equivalent to discharging a 200 pF capacitor via a resistor and series inductor with effective dynamic values of 25 Ω and 2.5 µH, which produces a damped oscillating discharge. Reference “Philips Semiconductors Test Method UZW-BO/FQ-B302 (similar to EIAJ IC-121 Test Method 20 condition C)”. Quality This device will meet the requirements of the “Philips Semiconductors General Quality Specification UZW-BO/FQ-0601” in accordance with “Quality Reference Handbook (order number 9397 750 00192)”. This details the acceptance criteria for all Q & R tests applied to the product. 1996 Jul 18 5 Philips Semiconductors Product specification Line twenty-one acquisition and display (LITOD) SAA5252 CHARACTERISTICS VDD = 5 to 5.5 V; VSS = 0 V; Tamb = −20 to +70 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDD supply voltage 4.5 5.0 5.5 V IDDtot total supply current − 30 − mA Inputs CVBS (PIN 1) Vsyn sync voltage amplitude 0.1 0.3 0.6 V Vvid(p-p) video voltage amplitude (peak-to-peak value) 0.7 1.0 1.4 V Vdat caption data voltage amplitude 0.25 0.35 0.49 V Zsource source impedance − − 250 Ω VI input switching voltage level of sync separator 1.7 2.0 2.3 V ZI input impedance 2.5 5 − kΩ CI input capacitance − − 10 pF − 27 − kΩ voltage on pin 24 − 1⁄ − V VIL LOW level input voltage −0.3 − +0.8 V 2.0 − VDD + 0.5 V −10 − +10 µA IREF (PIN 24) R24 V24 resistor to ground 2VDD H (PIN 8) VIH HIGH level input voltage ILI input leakage current IImax maximum input current −1 − +1 mA VI = 0 to VDD CI input capacitance − − 10 pF tr pulse rise time − − 5 µs tf pulse fall time − − 5 µs tW pulse width scan mode 1H 1 12 63 µs scan mode 2H 1 6 31 µs V (PIN 7) VIL LOW level input voltage −0.3 − +0.8 V VIH HIGH level input voltage 2.0 − VDD + 0.5 V ILI input leakage current −10 − +10 µA IImax maximum input current −1 − +1 mA CI input capacitance − − 10 pF tr pulse rise time − − 5 ns tf pulse fall time − − 5 ns tW pulse width 1 − − µs 1996 Jul 18 VI = 0 to VDD 6 Philips Semiconductors Product specification Line twenty-one acquisition and display (LITOD) SYMBOL PARAMETER CONDITIONS SAA5252 MIN. TYP. MAX. UNIT RGBREF (PIN, 17) VI input voltage ILI input leakage current VI = 0 to VDD −0.3 − VDD V −10 − +10 µA R, G AND B (PINS 15, 14 AND 13); note 1 VIL LOW level input voltage −0.3 − 0.8 V VIH HIGH level input voltage 2.0 − VDD + 0.5 V ZI input impedance 2.5 5.0 − kΩ −0.3 − 0.8 V BLANIN (PIN 9) VIL LOW level input voltage VIH HIGH level input voltage 2.0 − VDD + 0.5 V ILI input leakage current VI = 0 to VDD −10 − +10 µA tr input rise time between 10% and 90% − − 80 ns tf input fall time between 90% and 10% − − 80 ns I2C/DC (PIN 2) VIL LOW level input voltage 0 − 0.8 V VIH HIGH level input voltage 2.0 − VDD V ILI input leakage current −10 − +10 µA VI = 0 to VDD SCL (PIN 4) VIL LOW level input voltage −0.3 − 1.5 V VIH HIGH level input voltage 3.0 − VDD + 0.5 V fclk clock frequency 0 − 100 kHz tr input rise time between 10% and 90% − − 2 µs tf input fall time between 90% and 10% − − 2 µs ILI input leakage current VI = 0 to VDD −10 − +10 µA CI input capacitance − − 10 pF Inputs/outputs CERAMIC RESONATOR (PINS 20, 21 AND 22); see Fig.5 fosc oscillator frequency 11.82 12 12.18 MHz C0 parallel capacitance − 5.35 − pF C1 series capacitance − 37.4 − pF L1 series inductance − 35.5 − µH R1 series resistance − 6 25 Ω BLACK (PIN 23) Cblack storage capacitor to ground − 100 − nF Vblack black level voltage for nominal sync amplitude 1.8 2.15 2.5 V ILI input leakage current −10 − +10 µA 1996 Jul 18 VI = 0 to VDD 7 Philips Semiconductors Product specification Line twenty-one acquisition and display (LITOD) SYMBOL PARAMETER CONDITIONS SAA5252 MIN. TYP. MAX. UNIT SDA (PIN 3; OPEN DRAIN) VIL LOW level input voltage −0.3 − +1.5 V VIH HIGH level input voltage 3.0 − VDD + 0.5 V ILI input leakage current −10 − +10 µA VI = 0 to VDD CI input capacitance − − 10 pF tr input rise time between 10% and 90% − − 2 µs tf input fall time between 90% and 10% − − 2 µs VOL LOW level output voltage IOL = 3 mA 0 − 0.5 V tf output fall time between 3 V and 1 V − − 200 ns CL load capacitance − − 400 pF DR (PIN 5; OPEN DRAIN) VIL LOW level input voltage −0.3 − +1.5 V VIH HIGH level input voltage 3.0 − VDD + 0.5 V ILI input leakage current VI = 0 to VDD −10 − +10 µA VOL LOW level output voltage IOL = 1.6 mA 0 − 0.4 V tf output fall time between 4 V and 1 V with − 3.3 kΩ to 5 V − 50 ns CL load capacitance − − 100 pF Outputs R, G AND B (PINS 15, 14 AND 13; CAPTION MODE) VOL LOW level output voltage IOL = +2 mA 0 − 0.2 V VOH HIGH level output voltage IOH = −2 mA V17 − 0.3 V17 V17 + 0.4 V ZO output impedance − − 200 Ω CL load capacitance − − 50 pF tr output rise time between 10% and 90% − − 10 ns tf output fall time between 90% and 10% − − 10 ns BLAN (PIN 16) VOL LOW level output voltage IOL = +2 mA 0 − 0.4 V IOH = −2 mA 1.1 − 2.8 V − − 50 pF VOH HIGH level output voltage CL load capacitance tr output rise time between 10% and 90% − − 10 ns tf output fall time between 90% and 10% − − 10 ns tskew skew delay time between display and R, G, B, BLAN − − 10 ns 1996 Jul 18 8 Philips Semiconductors Product specification Line twenty-one acquisition and display (LITOD) SYMBOL PARAMETER CONDITIONS SAA5252 MIN. TYP. MAX. UNIT I2C timing (see Fig.3) tLOW clock LOW time 4 − − µs tHIGH clock HIGH time 4 − − µs tSU;DAT data set-up time 250 − − ns tHD;DAT data hold time 170 − − ns tSU;STO set-up time from clock HIGH-to-STOP 4 − − µs tBUF START set-up time following a STOP 4 − − µs tHD;STA START hold time 4 − − µs tSU;STA START set-up time following clock LOW-to-HIGH transition 4 − − µs tr output rise time between 10% and 90% − − 10 ns tf output fall time between 90% and 10% − − 10 ns Note 1. These inputs are analog, VIL and VIH values are quoted as a guide for digital RGB users. handbook, full pagewidth SDA t LOW t BUF tf SCL t HD;STA tr t HD;DAT t HIGH t SU;DAT SDA MBC764 t SU;STA Fig.3 I2C-bus timing diagram. 1996 Jul 18 9 t SU;STO Philips Semiconductors Product specification Line twenty-one acquisition and display (LITOD) SAA5252 APPLICATION INFORMATION 100 nF handbook, full pagewidth CVBS C5 CVBS SDA 3.3 kΩ I 2 C-bus to microcontroller SCL DR to microcontroller 24 2 23 2 I C/DC 5V 1 i.c. V 3 22 4 21 5 20 6 19 SAA5252 7 18 IREF BLACK C4 27 kΩ 100 nF 5V C3 10 nF OSCGND C3 33 pF OSCIN C2 33 pF OSCOUT 12 MHz VSS V DD C7 100 nF 5V 5V (1) H BLANIN RIN GIN BIN 8 17 9 16 10 15 11 14 12 13 RGBREF BLAN G B Fig.4 Application diagram. L1 R1 C0 MEA560 Fig.5 Ceramic resonator equivalent circuit. 1996 Jul 18 10 (1) R (1) Value dependent on application. C1 C6 10 µF MBB624 - 2 Philips Semiconductors Product specification Line twenty-one acquisition and display (LITOD) SAA5252 DISPLAY GENERATOR Display of external On-Screen Display (OSD) facilities General description The R, G, B and BLAN outputs of the display have the capability to be put in a 3-state mode allowing other OSD devices to take control of the television R, G, B and BLAN signals. The displayed characters are defined on a 5-by-12 matrix within a 7-by-13 window, allowing one blank pixel either side of the character and a blank pixel row above. There are a number of display options available controlled by Register 1, or external pins in ‘stand-alone’ mode. When the BLANIN is held HIGH then the R, G, B and BLAN outputs from display are disabled and the R, G, B and BLAN signals come directly from the RGBIN and BLANIN inputs. This will allow On-Screen Display to be placed on top of the captioning without any corruption, leaving the captions intact when the On-Screen Display is switched off (BLANIN goes LOW). In this form of operation the RGBIN and RGBOUT pins can be considered transparent; BLANIN goes through the normal output buffer to BLAN. The three display modes are video, text and caption, the device is powered up in the video mode. The display generator reads the Pre-amble Address Code (PAC) then the data associated with that row. Each character is then rounded after which it can be italicized and/or underlined, depending on the PAC or mid-row codes, before being passed on to the output circuitry. Figure 6 shows the character set. Table 1 Register map (WRITE) REGISTER D7 D6 D5 D4 D3 D2 D1 D0 00 DF1/2 RGB, BLAN H +ve/−ve +ve/−ve 01 CLEAR CH 2/1 NARROW/ WIDE 02 − − − − ROW3 ROW2 ROW1 ROW0 03 − − − COL4 COL3 COL2 COL1 COL0 04 − OSD6 OSD5 OSD4 OSD3 OSD2 OSD1 OSD0 D3 D2 Table 2 V +ve/−ve H3 H2 H1 H0 ACQ OFF EN1 EN0 M1 M0 Register map (READ) REGISTER D7 D6 D5 D4 D1 D0 80 POR 0 0 0 F1/F2 EDS PARITY SHUTDOWN DATA READY 81 PARITY ERROR DATA BIT 7 DATA BIT 6 DATA BIT 5 DATA BIT 4 DATA BIT 3 DATA BIT 2 DATA BIT 1 82 PARITY ERROR DATA BIT 7 DATA BIT 6 DATA BIT 5 DATA BIT 4 DATA BIT 3 DATA BIT 2 DATA BIT 1 1996 Jul 18 11 Philips Semiconductors Product specification Line twenty-one acquisition and display (LITOD) b6 b 0 0 0 0 0 5 b4 1 0 b 3 b 2 b 1 b0 column r o w 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 2 green 0 0 1 1 3 green underline 0 1 0 0 4 blue 0 1 0 1 5 blue underline 0 1 1 0 6 cyan 0 1 1 1 7 cyan underline 1 0 0 0 8 red 1 0 0 1 9 red underline 1 0 1 0 A yellow 1 0 1 1 B yellow underline 1 1 0 0 C magenta 1 1 0 1 D magenta underline 1 1 1 0 E italics 1 1 1 1 F italics underline 0 1 1 1 1 0 2 1 0 1 3 1 0 0 4 1 1 1 5 SAA5252 1 0 6 1 7 white signifies "flash on" command white underline signifies a transparent space MBB625 - 2 The ‘0’ and ‘zero’ use the same character, 4FH. Fig.6 Character set. 1996 Jul 18 12 Philips Semiconductors Product specification Line twenty-one acquisition and display (LITOD) SAA5252 I2C INTERFACE Description of WRITE registers The write subaddresses auto increment from 0 through to 4 at which point they stay until a new write subaddress is sent. Registers are set to all logic 0 at power-up. Table 3 Register 0 WRITE (Control Byte 1) BIT DESCRIPTION D0 to D3 H0 to H3 set the offset position from the start of the horizontal sync pulse, set to a nominal value on reset. D4 Vertical sync pulse expected to be negative going logic 0 or positive-going logic 1. D5 Horizontal sync pulse expected to be negative going logic 0 or positive-going logic 1. D6 Video outputs will be positive going logic 0 or negative-going logic 1. D7 Data field select. When set to logic 0 Field 1 is decoded, when set to logic 1 Field 2 is decoded. Table 4 Register 1 WRITE (Control Byte 2) BIT DESCRIPTION D0, D1 Display mode selection bits. Table 8 shows the possible display modes. D2, D3 Enhanced caption mode selection bits. Table 9 shows the possible enhanced caption modes. D4 When set to logic 1 acquisition of caption data is inhibited to allow the display to be used for On-Screen Display purposes. D5 Acquisition window selection. When set to logic 0 only Line 21 is checked for caption data. When set to logic 1, lines 19 to 23 of both fields are checked, allowing encrypted video signals to be handled. D6 User channel selection. D7 Clears the page memory when set HIGH. The page memory will be within two fields (30 ms). Table 5 Register 2 WRITE (On-Screen Display data row address) BIT DESCRIPTION D0 to D3 Row 0 to 3 sets the row address for On-Screen Display. This stored value will be incremented by overflow increments of Register 3. Table 6 Register 3 WRITE (On-Screen Display data column address) BIT DESCRIPTION D0 to D4 Columns 0 to 4 sets the column address for On-Screen Display. This stored value will be incremented by writes to Register 4. Table 7 Register 4 WRITE (On-Screen Display data) BIT D0 to D6 1996 Jul 18 DESCRIPTION OSD0 to OSD6, On-Screen Display data bits writing to this register causes Register 3 to increment its stored value. 13 Philips Semiconductors Product specification Line twenty-one acquisition and display (LITOD) Table 8 SAA5252 Display modes DISPLAY MODE OPTIONS M1 M0 Video only 0 0 Text mode 0 1 Normal caption mode 1 0 Enhanced caption mode 1 1 EN1 EN0 Table 9 Enhanced caption modes ENHANCED CAPTION MODES Enhanced caption modes EN1 EN0 Shadowed character/Video background 0 0 Shadowed character/Mesh background 0 1 Normal character/Video background 1 0 Normal character/Mesh background 1 1 Description of READ registers The read subaddresses auto increment from 80H through to 82H at which point they stay until a new read subaddress is sent. All the bits in Table 10 are reset to logic 0 after the register is read. Table 10 Register 80H READ (status) BIT DESCRIPTION D0 Data ready (new data has been acquired). D1 Parity error shut-down, goes HIGH when SAA5252 has a parity shut-down condition. D2 Indicates the following bytes are extended data service bytes. D3 Indicates Field 1 or Field 2 data bytes. D7 Indicates Power-On Reset (POR) has occurred, all I2C-bus write registers have been reset to logic 0. Table 11 Register 81H READ (first data byte) BIT DESCRIPTION D0 to D6 Data Bit 1 to Data Bit 7 (see note 1). D7 Parity error flag bit. Bit goes HIGH when a parity error has occurred. Note 1. In the Line 21, specification data bits are numbered D1 to D8. Table 12 Register 82H READ (second data byte) BIT DESCRIPTION D0 to D6 Data Bit 1 to Data Bit 7 (see note 1). D7 Parity error flag bit. Bit goes HIGH when a parity error has occurred. Note 1. In the Line 21, specification data bits are numbered D1 to D8. 1996 Jul 18 14 Philips Semiconductors Product specification Line twenty-one acquisition and display (LITOD) SAA5252 Interface to microcontroller using I2C-bus ‘STAND-ALONE’ (NON I2C-BUS) OPERATION The interface to the microcontroller is via the two-wire serial I2C-bus, and optionally by a Data-Ready signal (DR). On power up the microcontroller initializes the device by an I2C-bus WRITE to Registers 0 (Control Byte 1). The I2C-bus subaddress is then auto incremented to point to Register 1 (Control Byte 2). These two registers configure the device to the users requirements. To set the SAA5252 for ‘stand-alone’ operation pin 2 (I2C/DC) is tied LOW. This will change the operation of the SCL, SDA and DR pins to mode select inputs which will select as shown in Table 13. In the caption mode the SAA5252 operates in the basic Normal character/Black background mode. This complies with the FCC ruling. In the Enhanced caption mode the set-up will be Shadowed character/Video background. SDA and SCL in the ‘stand-alone’ operation act as bits M0 and M1 in Table 8. If the device is to be used for data acquisition only, then there are three methods by which the microcontroller can be informed of the arrival of valid Line 21 data: Table 13 Stand-alone modes • It can poll the DR pin, if the function has been enabled, and wait for it to go LOW. DR • It can use the negative edge of the DR signal to cause an interrupt. • It can poll the Data Ready bit (bit D0 of the status byte, I2C-bus READ Register 0). SCL SDA MODE OF OPERATION CHANNEL RECEPTION 0 0 0 video mode Channel 1 0 0 1 text mode Channel 1 Channel 1 0 1 0 normal captions When valid data is detected, the microcontroller must initiate an I2C-bus READ of Registers 80H, 81H and 82H. The first and second data bytes from the most recently received Line 21 are in Register 81H and Register 82H respectively. 0 1 1 enhanced captions Channel 1 1 0 0 video mode Channel 2 1 0 1 text mode Channel 2 1 1 0 normal captions Channel 2 The DR pin, and the Data Ready bit (Status bit D0) will be cleared after any register has been read. POR is reset after Register 80H has been read. 1 1 1 enhanced captions Channel 2 1996 Jul 18 15 Philips Semiconductors Product specification Line twenty-one acquisition and display (LITOD) SAA5252 PACKAGE OUTLINES seating plane DIP24: plastic dual in-line package; 24 leads (600 mil) SOT101-1 ME D A2 L A A1 c e Z b1 w M (e 1) b MH 13 24 pin 1 index E 1 12 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 5.1 0.51 4.0 1.7 1.3 0.53 0.38 0.32 0.23 32.0 31.4 14.1 13.7 2.54 15.24 3.9 3.4 15.80 15.24 17.15 15.90 0.25 2.2 inches 0.20 0.020 0.16 0.066 0.051 0.021 0.015 0.013 0.009 1.26 1.24 0.56 0.54 0.10 0.60 0.15 0.13 0.62 0.60 0.68 0.63 0.01 0.087 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT101-1 051G02 MO-015AD 1996 Jul 18 EIAJ EUROPEAN PROJECTION ISSUE DATE 92-11-17 95-01-23 16 Philips Semiconductors Product specification Line twenty-one acquisition and display (LITOD) SAA5252 SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 D E A X c HE y v M A Z 13 24 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 12 e detail X w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.30 0.10 2.45 2.25 0.25 0.49 0.36 0.32 0.23 15.6 15.2 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.9 0.4 0.012 0.096 0.004 0.089 0.01 0.019 0.013 0.014 0.009 0.61 0.60 0.30 0.29 0.050 0.42 0.39 0.055 0.043 0.016 0.043 0.039 0.01 0.01 0.004 0.035 0.016 inches 0.10 Z (1) θ Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT137-1 075E05 MS-013AD 1996 Jul 18 EIAJ EUROPEAN PROJECTION ISSUE DATE 92-11-17 95-01-24 17 o 8 0o Philips Semiconductors Product specification Line twenty-one acquisition and display (LITOD) Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. WAVE SOLDERING This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). Wave soldering techniques can be used for all SO packages if the following conditions are observed: • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. DIP SOLDERING BY DIPPING OR BY WAVE • The longitudinal axis of the package footprint must be parallel to the solder flow. The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. • The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. REPAIRING SOLDERED JOINTS A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. SO REFLOW SOLDERING Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. 1996 Jul 18 SAA5252 18 Philips Semiconductors Product specification Line twenty-one acquisition and display (LITOD) SAA5252 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1996 Jul 18 19 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 537021/01/04/pp20 Date of release: 1996 Jul 18 Document order number: 9397 750 00975