INTEGRATED CIRCUITS DATA SHEET SAA5264; SAA5265 10 and 1 page intelligent teletext decoders Preliminary specification Supersedes data of 1999 Oct 05 File under Integrated Circuits, IC02 2000 Jan 27 Philips Semiconductors Preliminary specification 10 and 1 page intelligent teletext decoders SAA5264; SAA5265 FEATURES The following features apply to both SAA5264 and SAA5265: • Complete 625 line teletext decoder in one chip reduces printed circuit board area and cost • Automatic detection of transmitted fastext links or service information (packet 8/30) GENERAL DESCRIPTION • On-Screen Display (OSD) for user interface menus using teletext and dedicated menu icons The SAA5264 is a single-chip ten page 625-line World System Teletext decoder with a high-level command interface, and is SAFARI compatible. • Video Programming System (VPS) decoding • Wide Screen Signalling (WSS) decoding The SAA5265 is a single-chip one page version of the SAA5264. • Pan-European, Cyrillic, Greek/Turkish and French/Arabic character sets in each chip Both devices are designed to minimize the overall system cost, due to the high-level command interface offering the benefit of a low software overhead in the TV microcontroller. • High-level command interface via I2C-bus gives easy control with a low software overhead • High-level command interface is backward compatible to Stand-Alone Fastext And Remote Interface (SAFARI) The SAA5264 has the following functionality: • 625 and 525 line display • 10 page teletext decoder with OSD, Fastext, TOP, default and list acquisition modes • RGB interface to standard colour decoder ICs, current source • Automatic channel installation support • Versatile 8-bit open-drain Input/Output (I/O) expander, 5 V tolerant • Closed caption acquisition and display • Violence Chip (VChip) support. • Single 12 MHz crystal oscillator The SAA5265 has the following functionality: • 3.3 V supply voltage. • 1 Page teletext decoder with OSD, fastext and default acquisition modes SAA5264 features • Automatic detection of transmitted pages to be selected by page up and page down • Automatic channel installation support • 8 Page fastext decoder • VChip support • Table Of Pages (TOP) decoder with Basic Top Table (BTT) and Additional Information Tables (AITs) • No EEPROM fitted (there is no list mode feature). • Closed caption acquisition and display • 4 Page user-defined list mode. 2000 Jan 27 2 Philips Semiconductors Preliminary specification 10 and 1 page intelligent teletext decoders SAA5264; SAA5265 ORDERING INFORMATION PACKAGE TYPE NUMBER(1) NAME DESCRIPTION VERSION SAA5264PS/M3/nnnn SDIP52 plastic shrink dual-in-line package; 52 leads (600 mil) SOT247-1 SAA5265PS/M4/nnnn SDIP52 plastic shrink dual-in-line package; 52 leads (600 mil) SOT247-1 Note 1. ‘nnnn’ is a unique four digit number denoting the software version. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDDX all supply voltages referenced to VSS 3.0 3.3 3.6 V IDDP periphery supply current note 1 1 − − mA IDDC core supply current normal mode − 15 18 mA idle mode − 4.6 6 mA IDDA analog supply current normal mode − 45 48 mA idle mode − 0.87 1 mA fundamental mode − 12 − MHz fxtal(nom) nominal crystal frequency Tamb ambient temperature −20 − +70 °C Tstg storage temperature −55 − +125 °C Note 1. Periphery supply current is dependent on external components and I/O voltage levels. 2000 Jan 27 3 Philips Semiconductors Preliminary specification 10 and 1 page intelligent teletext decoders SAA5264; SAA5265 BLOCK DIAGRAM handbook, full pagewidth TV CONTROL AND INTERFACE I2C-bus, general I/O ROM MICROCONTROLLER (80C51) DRAM MEMORY INTERFACE SRAM SAA5264 SAA5265 R CVBS DATA CAPTURE G DISPLAY B VDS CVBS DATA CAPTURE TIMING VSYNC DISPLAY TIMING HSYNC GSA018 Fig.1 Block diagram. 2000 Jan 27 4 Philips Semiconductors Preliminary specification 10 and 1 page intelligent teletext decoders SAA5264; SAA5265 PINNING SYMBOL PIN TYPE DESCRIPTION Port 2: 8-bit programmable bidirectional port with alternative functions P2.0/PWM 1 I/O output for 14-bit high precision Pulse Width Modulator (PWM) P2.1/PWM0 2 I/O outputs for 6-bit PWMs 0 to 6 P2.2/PWM1 3 I/O P2.3/PWM2 4 I/O P2.4/PWM3 5 I/O P2.5/PWM4 6 I/O P2.6/PWM5 7 I/O P2.7/PWM6 8 I/O Port 3: 8-bit programmable bidirectional port with alternative functions P3.0/ADC0 9 I/O P3.1/ADC1 10 I/O P3.2/ADC2 11 I/O P3.3/ADC3 12 I/O P3.4/PWM7 30 I/O VSSC 13 − inputs for the software Analog-to-Digital-Converter (ADC) facility output for 6-bit PWM7 core ground Port 0: 8-bit programmable bidirectional port I2C-bus Serial Clock input to Non-Volatile RAM SCL(NVRAM) 14 I SDA(NVRAM) 15 I/O I2C-bus Serial Data input/output (Non-Volatile RAM) P0.2 16 I/O input/output for general use P0.3 17 I/O input/output for general use P0.4 18 I/O input/output for general use P0.5 19 I/O 8 mA current sinking capability for direct drive of Light Emitting Diodes (LEDs) P0.6 20 I/O P0.7 21 I/O VSSA 22 − analog ground CVBS0 23 I CVBS1 24 I Composite Video Baseband Signal (CVBS) input; a positive-going 1 V (peak-to-peak) input is required; connected via a 100 nF capacitor SYNC_FILTER 25 I sync-pulse-filter input for CVBS; this pin should be connected to VSSA via a 100 nF capacitor IREF 26 I reference current input for analog circuits; for correct operation a 24 kΩ resistor should be connected to VSSA FRAME 27 O Frame de-interlace output synchronized with the VSYNC pulse to produce a non-interlaced display by adjustment of the vertical deflection circuits TEST 28 I not available; connect this pin to VSSA COR 29 O contrast reduction: open-drain, active LOW output which allows selective contrast reduction of the TV picture to enhance a mixed mode display 30 I/O P3.4/PWM7 (described above) VDDA 31 − analog supply voltage (3.3 V) B 32 O Blue colour information pixel rate output 2000 Jan 27 input/output for general use 5 Philips Semiconductors Preliminary specification 10 and 1 page intelligent teletext decoders SYMBOL SAA5264; SAA5265 PIN TYPE DESCRIPTION G 33 O Green colour information pixel rate output R 34 O Red colour information pixel rate output VDS 35 O video/data switch push-pull output for pixel rate fast blanking HSYNC 36 I horizontal sync pulse input: Schmitt triggered for a Transistor Transistor Level (TTL) version; the polarity of this pulse is programmable by register bit TXT1.H POLARITY VSYNC 37 I vertical sync pulse input; Schmitt triggered for a TTL version; the polarity of this pulse is programmable by register bit TXT1.V POLARITY VSSP 38 − periphery ground VDDC 39 − core supply voltage (+3.3 V) OSCGND 40 − crystal oscillator ground XTALIN 41 I 12 MHz crystal oscillator input XTALOUT 42 O 12 MHz crystal oscillator output RESET 43 I reset input; if this pin is HIGH for at least 2 machine cycles (24 oscillator periods) while the oscillator is running, the device resets; this pin should be connected to VDDP via a capacitor VDDP 44 − periphery supply voltage (+3.3 V) Port 1: 8-bit programmable bidirectional port P1.0 45 I/O input/output for general use P1.1 46 I/O input/output for general use P1.2 47 I/O input/output for general use P1.3 48 I/O SCL 49 I SDA 50 I/O I2C-bus Serial Data input/output (application) P1.4 51 I/O input/output for general use P1.5 52 I/O input/output for general use 2000 Jan 27 input/output for general use I2C-bus Serial Clock input from application 6 Philips Semiconductors Preliminary specification 10 and 1 page intelligent teletext decoders handbook, halfpage P2.0/PWM 1 52 P1.5 P2.1/PWM0 2 51 P1.4 P2.2/PWM1 3 50 SDA P2.3/PWM2 4 49 SCL P2.4/PWM3 5 48 P1.3 P2.5/PWM4 6 47 P1.2 P2.6/PWM5 7 46 P1.1 P2.7/PWM6 8 45 P1.0 P3.0/ADC0 9 44 VDDP P3.1/ADC1 10 43 RESET P3.2/ADC2 11 42 XTALOUT P3.3/ADC3 12 41 XTALIN SAA5264 VSSC 13 SAA5265 40 OSCGND SCL(NVRAM) 14 39 VDDC SDA(NVRAM) 15 38 VSSP P0.2 16 37 VSYNC P0.3 17 36 HSYNC P0.4 18 35 VDS P0.5 19 34 R P0.6 20 33 G P0.7 21 32 B VSSA 22 31 VDDA CVBS0 23 30 P3.4/PWM7 CVBS1 24 29 COR SYNC_FILTER 25 28 TEST IREF 26 27 FRAME GSA016 Fig.2 Pin configuration. 2000 Jan 27 7 SAA5264; SAA5265 Philips Semiconductors Preliminary specification 10 and 1 page intelligent teletext decoders SAA5264; SAA5265 HIGH LEVEL COMMAND INTERFACE The I2C-bus interface is used to pass control commands and data between the SAA5264/SAA5265 and the television microcontroller. The interface uses high-level commands, which are backward compatible with the SAFARI. The I2C-bus transmission formats are: Table 1 User command I2C-BUS ADDRESS START Table 2 ACK COMMAND ACK STOP PARAMETER ACK STOP DATA ACK STOP System command I2C-BUS ADDRESS WRITE START Table 3 WRITE ACK COMMAND ACK User read START I2C-BUS ADDRESS READ ACK CHARACTER SETS The following standard character sets are included in the SAA5264 and in the SAA5265: Set 0 = Pan-European Set 1 = Cyrillic Set 2 = Greek/Turkish Set 3 = French/Arabic If you require any other character sets, please discuss them with your local Regional Sales Office first. LIMITING VALUES In accordance with Absolute Maximum Rating System (IEC 60134). SYMBOL PARAMETER VDDX all supply voltages CONDITIONS MIN. MAX. −0.5 +4.0 UNIT V VI input voltage (any input) note 1 −0.5 VDD + 0.5 or +4.1 V VO output voltage (any output) note 1 −0.5 VDD + 0.5 V IO output current (each output) − 10 mA IIO(d) diode DC input or output current − 20 mA Tamb ambient temperature −20 +70 °C Tstg storage temperature −55 +125 °C Note 1. This maximum value refers to 5 V tolerant I/Os and may be 6 V maximum but only when VDD is present. 2000 Jan 27 8 Philips Semiconductors Preliminary specification 10 and 1 page intelligent teletext decoders SAA5264; SAA5265 CHARACTERISTICS VDD = 3.3 V ±10%; VSS = 0 V; Tamb = −20 to +70 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDDX all supply voltages referenced to VSS 3.0 3.3 3.6 V IDDP periphery supply current note 1 1 − − mA IDDC core supply current normal mode − 15 18 mA IDDC(idle) idle mode core supply current − 4.6 6 mA IDDA analog supply current − 45 48 mA IDDA(idle) idle mode analog supply current − 0.87 1 mA normal mode Digital inputs RESET (PIN 43) VIL LOW-level input voltage − − 1.00 V VIH HIGH-level input voltage 1.85 − − V Vhys Schmitt trigger input hysteresis voltage 0.44 − 0.58 V ILI input leakage current VI = 0 − − 0.17 µA Rpd(eq) equivalent pull-down resistance VI = VDD 55.73 70.71 92.45 kΩ HSYNC, VSYNC (PINS 36 AND 37) VIL LOW-level input voltage − − 0.96 V VIH HIGH-level input voltage 1.80 − − V Vhys Schmitt trigger input hysteresis voltage 0.40 − 0.56 V ILI Input leakage current VI = 0 to VDD − − 0.00 µA Digital outputs FRAME, VDS (PINS 27 AND 35) VOL LOW-level output voltage IOL = 3 mA − − 0.13 V VOH HIGH-level output voltage IOH = 3 mA 2.84 − − V to(r) output rise time between 10% and 7.50 90%; CL = 70 pF 8.85 10.90 ns to(f) output fall time between 10% and 6.70 90%; CL = 70 pF 7.97 10.00 ns 2000 Jan 27 9 Philips Semiconductors Preliminary specification 10 and 1 page intelligent teletext decoders SYMBOL PARAMETER CONDITIONS MIN. SAA5264; SAA5265 TYP. MAX. UNIT COR (OPEN-DRAIN OUTPUT, PIN 29) VOL LOW-level output voltage IOL = 3 mA − − 0.14 V VOH(pu) HIGH-level pull-up output voltage IOL = −3 mA; push-pull 2.84 − − V VIL LOW-level input voltage − − 0.00 V VIH HIGH-level input voltage 0.00 − 5.50 V ILI input leakage current VI = 0 to VDD − − 0.12 µA to(r) output rise time between 10% and 7.20 90%; CL = 70 pF 8.64 11.10 ns to(f) output fall time between 10% and 4.90 90%; CL = 70 pF 7.34 9.40 ns Digital input/outputs SCL(NVRAM), SDA(NVRAM), P0.4, P0.7, P1.0, P1.1, P2.1 TO P2.7, P3.0 TO P3.4 (PINS 14, 15, 18, 21, 45, 46, 2 TO 12, 30) VIL LOW-level input voltage − − 0.98 V VIH HIGH-level input voltage 1.78 − − V Vhys Schmitt trigger input hysteresis voltage 0.41 − 0.55 V ILI input leakage current VI = 0 to VDD − − 0.01 µA VOL LOW-level output voltage IOL = 4 mA − − 0.18 V VOH HIGH-level output voltage IOH = −4 mA push-pull 2.81 − − V to(r) output rise time between 10% and 6.50 90%; CL = 70 pF push-pull 8.47 10.70 ns to(f) output fall time between 10% and 5.70 90%; CL = 70 pF 7.56 10.00 ns P1.2, P1.3, P2.0 (PINS 47, 48, 1) VIL LOW-level input voltage − − 0.99 V VIH HIGH-level input voltage 1.80 − − V Vhys Schmitt trigger input hysteresis voltage 0.42 − 0.56 V ILI input leakage current − − 0.02 µA 2000 Jan 27 VI = 0 to VDD 10 Philips Semiconductors Preliminary specification 10 and 1 page intelligent teletext decoders SYMBOL PARAMETER CONDITIONS MIN. SAA5264; SAA5265 TYP. MAX. UNIT VOL LOW-level output voltage IOL = 4 mA − − 0.17 V VOH HIGH-level output voltage IOH = −4 mA push-pull 2.81 − − V to(r) output rise time between 10% and 7.00 90%; CL = 70 pF push-pull 8.47 10.50 ns to(f) output fall time between 10% and 5.40 90%; CL = 70 pF 7.36 9.30 ns P0.5, P0.6 (PINS 19, 20) VIL LOW-level input voltage − − 0.98 V VIH HIGH-level input voltage 1.82 − − V ILI input leakage current − − 0.11 µA Vhys Schmitt trigger input hysteresis voltage 0.42 − 0.58 V VOL LOW-level output voltage IOL = 8 mA − − 0.20 V VOH HIGH-level output voltage IOH = −8 mA push-pull 2.76 − − V to(r) output rise time between 10% and 7.40 90%; CL = 70 pF push-pull 8.22 8.80 ns to(f) output fall time between 10% and 4.20 90%; CL = 70 pF 4.57 5.20 ns VI = 0 to VDD P1.4, P1.5 (OPEN-DRAIN) (PINS 51, 52) VIL LOW-level input voltage − − 1.08 V VIH HIGH-level input voltage 1.99 − − V Vhys Schmitt trigger input hysteresis voltage 0.49 − 0.60 V ILI input leakage current VI = 0 to VDD − − 0.13 µA VOL LOW-level output voltage IOL = 8 mA − − 0.35 V to(f) output fall time between 10% and 69.70 83.67 90%; CL = 70 pF 103.30 ns 2000 Jan 27 11 Philips Semiconductors Preliminary specification 10 and 1 page intelligent teletext decoders SYMBOL PARAMETER CONDITIONS MIN. SAA5264; SAA5265 TYP. MAX. UNIT Analog inputs CVBS0 AND CVBS1(PINS 23 AND 24) Vsync sync voltage amplitude 0.1 0.3 0.6 V Vi(v)(p-p) video input voltage (peak-to-peak value) 0.7 1.0 1.4 V Zsource source impedance 0 − 250 Ω VIH HIGH-level input voltage 3.0 − VDDA +0.3 V Ci input capacitance − − 10 pF − 24 − kΩ IREF (PIN 26) RIREF resistance from IREF to VSSA resistor tolerance = 2% ADC0 TO ADC3 (PINS 9 TO 12) VIH HIGH-level input voltage − − VDDA V Ci input capacitance − − 10 pF Analog outputs B, G AND R (PINS 32 TO 34) Io(bl) output current (black level) VDDA = 3.3 V −10 − +10 µA Io(max) output current (maximum intensity) VDDA = 3.3 V intensity level code = 15 (Dec) 6.0 6.67 7.3 mA Io(70%max) output current (70% of maximum intensity) VDDA = 3.3 V intensity level code = 0 (Dec) 4.2 4.7 5.1 mA RL load resistance (to VSSA) resistor tolerance = 5% − 150 − Ω CL load capacitance − − 15 pF − 100 − nF 0.35 0.55 0.75 V Analog input/output SYNC_FILTER (PIN 25) Cstg storage capacitor (to VSSA) Vsync(nom) sync filter level voltage with nominal sync amplitude 2000 Jan 27 12 Philips Semiconductors Preliminary specification 10 and 1 page intelligent teletext decoders SYMBOL PARAMETER CONDITIONS MIN. SAA5264; SAA5265 TYP. MAX. UNIT Crystal oscillator XTALIN (PIN 41) VIL LOW-level input voltage VSSA − − V VIH HIGH-level input voltage − − VDDA V Ci input capacitance − − 10 pF − − 10 pF − 12 − MHz − − 30 pF XTALOUT (PIN 42) Co output capacitance Crystal specification; notes 2 and 3 fxtal(nom) nominal frequency CL load capacitance Cmot motional capacitance Tamb = 25 °C − − 20 fF Rxtal crystal resonance resistance Tamb = 25 °C − − 60 Ω Cosc capacitance at XTALIN, XTALOUT Tamb = 25 °C − 2C L – C chip – C stray − Cxtal(hold) crystal holder capacitance Tamb = 25 °C − − C osc C chip C stray pF 35 – ----------- – ------------- – --------------2 2 2 Txtal crystal temperature range −20 +25 +85 Xj adjustment tolerance − − ±50 × 10−6 Xd drift − − ±100 × 10−6 fundamental mode Tamb = 25 °C pF °C Notes 1. Periphery supply current is dependent on I/O external components and voltage levels. 2. Crystal order number 4322 143 05561. If crystal 4322 143 05561 is not used, then the formulae in the crystal specification should be used. 3. Cosc may need to be reduced from the initially selected value. Cchip = 7 pF, the mean of the capacitances due to the chip at XTALIN and at XTALOUT. Cstray is a value for the mean of the stray capacitances due to the external circuit at XTALIN and XTALOUT. The maximum value for Cxtal(hold) is to ensure start-up. 2000 Jan 27 13 Philips Semiconductors Preliminary specification 10 and 1 page intelligent teletext decoders SAA5264; SAA5265 I2C-BUS CHARACTERISTICS FAST-MODE I2C-bus SYMBOL UNIT PARAMETER MIN. MAX. fSCL SCL clock frequency 0 400 kHz tBUF bus free time between a STOP and START condition 1.3 − µs tHD;STA hold time START condition; after this period, the first clock pulse is generated 0.6 − µs tLOW SCL LOW time 1.3 − µs tHIGH SCL HIGH time 0.6 − µs tSU;STA set-up time repeated START 0.6 − µs tHD;DAT data hold time; notes 1 and 2 0 0.9 µs tSU;DAT data set-up time; note 3 100 − ns tr rise time SDA and SCL; note 4 20 300 ns tf fall time SDA and SCL; note 4 20 300 ns tSU;STO set-up time STOP condition 0.6 − µs Cb capacitive load of each bus line − 400 pF Notes 1. A device must internally provide a hold time of at least 300 ns for the SDA signal (referenced to the VIHmin of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. 2. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period of the SCL signal (tLOW(SCL)). 3. A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tSU;DAT ≥250 ns must then be met. This will automatically be the case if the device does not stretch tLOW(SCL). If such a device does stretch tLOW(SCL), it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C-bus specification) before the SCL line is released. 4. Cb = total capacitance of one bus line in pF. 2000 Jan 27 14 Philips Semiconductors Preliminary specification 10 and 1 page intelligent teletext decoders EMC GUIDELINES Using a device socket would increase the area and therefore increase the inductance of the external bypass loop. Optimization of circuit return paths and minimization of common mode emission will be assisted by using a double sided Printed Circuit Board (PCB) with low inductance ground plane. To provide a high-impedance to any high frequency signals on the VDD supplies to the IC, a ferrite bead or inductor can be connected in series with the supply line close to the decoupling capacitor. To prevent signal radiation, pull-up resistors of signal outputs should not be connected to the VDD supply on the IC side of the ferrite bead or inductor. On a single-sided PCB a local ground plane under the whole IC should be present as shown in Fig.3. This should have the widest possible connection between the PCB ground and bulk electrolytic decoupling capacitor. Preferably, the PCB local ground plane connection should not be connected to other grounds on route to the PCB ground. Do not use wire links. Wire links cause ground inductance which increases ground bounce. OSCGND should only be connected to the crystal load capacitors and not to any other ground connection. Distances to physical connections of associated active devices should be as short as possible. The supply pins can be decoupled at the ground pin plane below the IC. This is easily achieved by using surface mount capacitors, which, at high frequency, are more effective than components with leads. handbook, full pagewidth GND +3.3 V SAA5264; SAA5265 PCB output tracks should have close proximity, mutually coupled, ground return paths. electrolytic decoupling capacitor (2 µF) ferrite beads VDDA VDDC VSSP VDDP other GND connections under-IC GND plane under-IC GND plane GND connection note: no wire links VSSC VSSA Fig.3 Power supply connections for EMC. 2000 Jan 27 SM decoupling capacitors (10 to 100 nF) 15 IC MBK979 Philips Semiconductors Preliminary specification 10 and 1 page intelligent teletext decoders SAA5264; SAA5265 QUALITY AND RELIABILITY This device will meet Philips Semiconductors general quality specification for business group “Consumer Integrated Circuits SNW-FQ-611-Part E”. The principal requirements are shown in Tables 4 to 7. Group A Table 4 Acceptance tests per lot; note 1 TEST REQUIREMENTS Mechanical Electrical cumulative target: <80 ppm cumulative target: <100 ppm Note 1. ppm = fraction of defective devices, in parts per million. Group B Table 5 Processability tests (by package family) TEST REQUIREMENTS Solderability Mechanical Solder heat resistance 0/16 on all lots 0/15 on all lots 0/15 on all lots Group C Table 6 Reliability tests (by package family); note 1 TEST CONDITIONS 168 hours at Tj = 150 °C temperature, humidity, bias 1000 hours; Tamb = 85 °C, 85% RH (or equivalent test) Temperature cycling performance Tstg(min) to Tstg(max) Operational life Humidity life REQUIREMENTS <1000 FPM at Tj = 150 °C <2000 FPM <2000 FPM Note 1. FPM = fraction of devices failing at test condition, in Failures Per Million. Table 7 Reliability tests (by device type) TEST ESD and latch-up 2000 Jan 27 CONDITIONS ESD Human body model 100 pF, 1.5 kΩ ESD Machine model 200 pF, 0 Ω latch-up 16 REQUIREMENTS 2000 V 200 V 100 mA, 1.5 × VDD (absolute maximum) This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... P2.3/PWM2 user ports P2.4/PWM3 P2.5/PWM4 P2.6/PWM5 P2.7/PWM6 P3.0/ADC0 P3.1/ADC1 VDD A0 VDD A1 RC EEPROM P3.2/ADC2 P3.3/ADC3 VSSC 17 A2 PCF8582E SCL SCL(NVRAM) VSS SDA SDA(NVRAM) P0.2 P0.3 VDD P0.4 1 kΩ P0.5 P0.6 1 kΩ P0.7 VSSA CVBS CVBS 100 nF CVBS0 100 nF CVBS1 SYNC_FILTER 100 nF 2 51 3 50 4 49 5 48 6 47 7 46 8 45 9 44 10 43 11 42 12 41 13 14 SAA5264 SAA5265 40 39 15 38 16 37 17 36 18 35 19 34 20 33 21 32 22 31 23 30 24 29 25 28 26 27 24 kΩ Fig.4 Application diagram. P1.4 SDA SDA SCL SCL P1.3 P1.2 P1.1 P1.0 VDDP VDD RESET VDD XTALOUT XTALIN 10 µF VDD 12 MHz 56 pF OSCGND VDDC VSSP 47 µF 100 nF VDD VSYNC field flyback HSYNC line flyback VDS R G B VDDA P3.4/PWM7 VDD 150 Ω VDD COR TEST FRAME GSA035 Preliminary specification Bi-directional ports have been configured as open-drain. Output ports have been configured as push-pull. P1.5 SAA5264; SAA5265 IREF 52 Philips Semiconductors P2.2/PWM1 1 10 and 1 page intelligent teletext decoders P2.0/PWM P2.1/PWM0 VDD APPLICATION INFORMATION handbook, full pagewidth 2000 Jan 27 VDD Philips Semiconductors Preliminary specification 10 and 1 page intelligent teletext decoders SAA5264; SAA5265 PACKAGE OUTLINE seating plane SDIP52: plastic shrink dual in-line package; 52 leads (600 mil) SOT247-1 ME D A2 L A A1 c e Z b1 (e 1) w M MH b 27 52 pin 1 index E 1 26 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 5.08 0.51 4.0 1.3 0.8 0.53 0.40 0.32 0.23 47.9 47.1 14.0 13.7 1.778 15.24 3.2 2.8 15.80 15.24 17.15 15.90 0.18 1.73 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT247-1 2000 Jan 27 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 95-03-11 99-12-27 MS-020 18 Philips Semiconductors Preliminary specification 10 and 1 page intelligent teletext decoders SAA5264; SAA5265 The total contact time of successive solder waves must not exceed 5 seconds. SOLDERING Introduction to soldering through-hole mount packages The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. This text gives a brief insight to wave, dip and manual soldering. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). Wave soldering is the preferred method for mounting of through-hole mount IC packages on a printed-circuit board. Manual soldering Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. Soldering by dipping or by solder wave The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joints for more than 5 seconds. Suitability of through-hole mount IC packages for dipping and wave soldering methods SOLDERING METHOD PACKAGE DIPPING DBS, DIP, HDIP, SDIP, SIL WAVE suitable(1) suitable Note 1. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. 2000 Jan 27 19 Philips Semiconductors Preliminary specification 10 and 1 page intelligent teletext decoders SAA5264; SAA5265 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 2000 Jan 27 20 Philips Semiconductors Preliminary specification 10 and 1 page intelligent teletext decoders NOTES 2000 Jan 27 21 SAA5264; SAA5265 Philips Semiconductors Preliminary specification 10 and 1 page intelligent teletext decoders NOTES 2000 Jan 27 22 SAA5264; SAA5265 Philips Semiconductors Preliminary specification 10 and 1 page intelligent teletext decoders NOTES 2000 Jan 27 23 SAA5264; SAA5265 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 753504/02/pp24 Date of release: 2000 Jan 27 Document order number: 9397 750 06789