PD - 97125
IRF1018EPbF
IRF1018ESPbF
IRF1018ESLPbF
Applications
l High Efficiency Synchronous Rectification in
SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
HEXFET® Power MOSFET
VDSS
RDS(on) typ.
max.
ID
D
G
S
Benefits
l Improved Gate, Avalanche and Dynamic
dv/dt Ruggedness
l Fully Characterized Capacitance and
Avalanche SOA
l Enhanced body diode dV/dt and dI/dt
Capability
D
D
D
G
D
S
G
D
S
G
D2Pak
IRF1018ESPbF
TO-220AB
IRF1018EPbF
60V
7.1m:
8.4m:
79A
D
S
TO-262
IRF1018ESLPbF
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
ID @ TC = 25°C
Parameter
Max.
Continuous Drain Current, VGS @ 10V
Units
79
ID @ TC = 100°C
Continuous Drain Current, VGS @ 10V
56
IDM
Pulsed Drain Current c
315
PD @TC = 25°C
Maximum Power Dissipation
110
W
Linear Derating Factor
0.76
VGS
Gate-to-Source Voltage
± 20
W/°C
V
dv/dt
TJ
Peak Diode Recovery e
21
Operating Junction and
-55 to + 175
TSTG
Storage Temperature Range
A
V/ns
°C
300
Soldering Temperature, for 10 seconds
(1.6mm from case)
10lbxin (1.1Nxm)
Mounting torque, 6-32 or M3 screw k
Avalanche Characteristics
EAS (Thermally limited)
Single Pulse Avalanche Energy d
88
mJ
IAR
Avalanche Current c
47
A
EAR
Repetitive Avalanche Energy f
11
mJ
Thermal Resistance
Typ.
Max.
RθJC
Symbol
Junction-to-Case j
–––
1.32
RθCS
Case-to-Sink, Flat Greased Surface , TO-220
0.50
–––
RθJA
Junction-to-Ambient, TO-220 j
–––
62
RθJA
Junction-to-Ambient (PCB Mount) , D Pak ij
–––
40
www.irf.com
Parameter
2
Units
°C/W
1
2/28/08
IRF1018E/S/SLPbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
V(BR)DSS
ΔV(BR)DSS/ΔTJ
RDS(on)
VGS(th)
IDSS
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Drain-to-Source Leakage Current
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Min. Typ. Max. Units
60
––– –––
––– 0.073 –––
–––
7.1
8.4
2.0
–––
4.0
––– –––
20
––– ––– 250
––– ––– 100
––– ––– -100
Conditions
V VGS = 0V, ID = 250μA
V/°C Reference to 25°C, ID = 5mAc
mΩ VGS = 10V, ID = 47A f
V VDS = VGS, ID = 100μA
μA VDS = 60V, VGS = 0V
VDS = 48V, VGS = 0V, TJ = 125°C
nA VGS = 20V
VGS = -20V
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
Min. Typ. Max. Units
gfs
Qg
Qgs
Qgd
Qsync
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Qg - Qgd)
110
–––
–––
–––
–––
–––
46
10
12
34
–––
69
–––
–––
–––
RG(int)
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Coss eff. (ER)
Coss eff. (TR)
Internal Gate Resistance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
–––
0.73
13
35
55
46
2290
270
130
390
630
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Effective Output Capacitance (Energy Related)h –––
–––
Effective Output Capacitance (Time Related)g
S
nC
Conditions
VDS = 50V, ID = 47A
ID = 47A
VDS = 30V
VGS = 10V f
ID = 47A, VDS =0V, VGS = 10V
Ω
ns
pF
VDD = 39V
ID = 47A
RG = 10Ω
VGS = 10V f
VGS = 0V
VDS = 50V
ƒ = 1.0MHz
VGS = 0V, VDS = 0V to 60V h
VGS = 0V, VDS = 0V to 60V g
Diode Characteristics
Symbol
Parameter
Min. Typ. Max. Units
IS
Continuous Source Current
–––
–––
79
ISM
(Body Diode)
Pulsed Source Current
–––
–––
315
VSD
trr
(Body Diode)c
Diode Forward Voltage
Reverse Recovery Time
Qrr
Reverse Recovery Charge
IRRM
ton
Reverse Recovery Current
Forward Turn-On Time
Notes:
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.08mH
RG = 25Ω, IAS = 47A, VGS =10V. Part not recommended for
use above this value.
ISD ≤ 47A, di/dt ≤ 1668A/μs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
Pulse width ≤ 400μs; duty cycle ≤ 2%.
2
A
Conditions
MOSFET symbol
showing the
integral reverse
D
G
S
p-n junction diode.
––– –––
1.3
V TJ = 25°C, IS = 47A, VGS = 0V f
VR = 51V,
–––
26
39
ns TJ = 25°C
IF = 47A
TJ = 125°C
–––
31
47
di/dt = 100A/μs f
–––
24
36
nC TJ = 25°C
=
125°C
T
–––
35
53
J
–––
1.8
–––
A TJ = 25°C
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
Rθ is measured at TJ approximately 90°C.
This is only applied to TO-220
www.irf.com
IRF1018E/S/SLPbF
1000
1000
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
100
BOTTOM
4.5V
10
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
100
BOTTOM
4.5V
10
≤60μs PULSE WIDTH
≤60μs PULSE WIDTH
Tj = 25°C
Tj = 175°C
1
1
0.1
1
10
100
0.1
100
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
2.5
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID, Drain-to-Source Current (A)
10
VDS, Drain-to-Source Voltage (V)
1000
100
TJ = 175°C
10
TJ = 25°C
1
VDS = 25V
≤60μs PULSE WIDTH
0.1
ID = 47A
VGS = 10V
2.0
1.5
1.0
0.5
2
3
4
5
6
7
8
9
-60 -40 -20 0 20 40 60 80 100120140160180
VGS, Gate-to-Source Voltage (V)
TJ , Junction Temperature (°C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance vs. Temperature
4000
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
VGS, Gate-to-Source Voltage (V)
16
Coss = Cds + Cgd
3000
C, Capacitance (pF)
1
VDS, Drain-to-Source Voltage (V)
Ciss
2000
1000
Coss
Crss
0
1
VDS = 48V
VDS = 30V
12
VDS = 12V
8
4
0
10
100
VDS , Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
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ID= 47A
0
10
20
30
40
50
60
QG Total Gate Charge (nC)
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
3
IRF1018E/S/SLPbF
10000
100
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
1000
TJ = 175°C
10
TJ = 25°C
1
OPERATION IN THIS AREA
LIMITED BY R DS (on)
1000
100
1msec
10
10msec
1
Tc = 25°C
Tj = 175°C
Single Pulse
VGS = 0V
0.0
0.5
1.0
1.5
0.1
2.0
ID , Drain Current (A)
60
40
20
0
75
100
125
150
175
V(BR)DSS, Drain-to-Source Breakdown Voltage (V)
80
50
10
100
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode Forward Voltage
25
1
VDS , Drain-toSource Voltage (V)
VSD , Source-to-Drain Voltage (V)
80
Id = 5mA
75
70
65
60
-60 -40 -20 0 20 40 60 80 100120140160180
TC , CaseTemperature (°C)
TJ , Temperature ( °C )
Fig 10. Drain-to-Source Breakdown Voltage
Fig 9. Maximum Drain Current vs. Case Temperature
400
EAS, Single Pulse Avalanche Energy (mJ)
0.8
0.6
Energy (μJ)
DC
0.1
0.1
0.4
0.2
0.0
ID
5.3A
11A
BOTTOM 47A
350
TOP
300
250
200
150
100
50
0
0
10
20
30
40
50
60
VDS, Drain-to-Source Voltage (V)
4
100μsec
Fig 11. Typical COSS Stored Energy
25
50
75
100
125
150
175
Starting TJ, Junction Temperature (°C)
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
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IRF1018E/S/SLPbF
Thermal Response ( Z thJC )
10
1
D = 0.50
0.20
0.10
0.1
τJ
0.05
0.02
0.01
R1
R1
τJ
τ1
R2
R2
R3
R3
R4
R4
τC
τ2
τ1
τ3
τ2
τ4
τ3
Ci= τi/Ri
Ci i/Ri
0.01
SINGLE PULSE
( THERMAL RESPONSE )
τ4
τ
Ri (°C/W)
0.026741
0.28078
0.606685
0.406128
τι (sec)
0.000007
0.000091
0.000843
0.005884
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
100
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔTj = 150°C and
Tstart =25°C (Single Pulse)
Avalanche Current (A)
Duty Cycle = Single Pulse
0.01
10
0.05
0.10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔΤ j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
EAR , Avalanche Energy (mJ)
100
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ΔT = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
TOP
Single Pulse
BOTTOM 10% Duty Cycle
ID = 47A
80
60
40
20
0
25
50
75
100
125
150
175
Starting TJ , Junction Temperature (°C)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Fig 15. Maximum Avalanche Energy vs. Temperature
www.irf.com
5
IRF1018E/S/SLPbF
14
ID = 1.0A
4.0
ID = 1.0mA
12
IF = 32A
VR = 51V
3.5
ID = 100μA
10
TJ = 25°C
TJ = 125°C
ID = 250μA
3.0
8
IRR (A)
VGS(th) Gate threshold Voltage (V)
4.5
2.5
6
2.0
4
1.5
2
1.0
-75
-50 -25
0
25
50
75
0
100 125 150 175
0
200
TJ , Temperature ( °C )
600
800
1000
diF /dt (A/μs)
Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage vs. Temperature
14
320
12
IF = 47A
VR = 51V
280
IF = 32A
VR = 51V
10
TJ = 25°C
TJ = 125°C
240
TJ = 25°C
TJ = 125°C
200
8
QRR (A)
IRR (A)
400
6
160
120
4
80
2
40
0
0
0
200
400
600
800
1000
0
200
diF /dt (A/μs)
400
600
800
1000
diF /dt (A/μs)
Fig. 18 - Typical Recovery Current vs. dif/dt
Fig. 19 - Typical Stored Charge vs. dif/dt
320
IF = 47A
VR = 51V
TJ = 25°C
280
240
TJ = 125°C
QRR (A)
200
160
120
80
40
0
0
200
400
600
800
1000
diF /dt (A/μs)
6
Fig. 20 - Typical Stored Charge vs. dif/dt
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IRF1018E/S/SLPbF
Driver Gate Drive
D.U.T
+
-
-
*
RG
•
•
•
•
D.U.T. ISD Waveform
Reverse
Recovery
Current
VDD
**
P.W.
Period
***
+
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
D=
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
Period
P.W.
+
+
-
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
ISD
Ripple ≤ 5%
* Use P-Channel Driver for P-Channel Measurements
** Reverse Polarity for P-Channel
*** VGS = 5V for Logic Level Devices
Fig 21. Diode Reverse Recovery Test Circuit for HEXFET® Power MOSFETs
V(BR)DSS
15V
D.U.T
RG
VGS
20V
DRIVER
L
VDS
tp
+
V
- DD
IAS
tp
A
0.01Ω
I AS
Fig 22a. Unclamped Inductive Test Circuit
RD
VDS
Fig 22b. Unclamped Inductive Waveforms
VDS
90%
VGS
D.U.T.
RG
+
-VDD
10%
VGS
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
td(on)
Fig 23a. Switching Time Test Circuit
td(off)
tr
tf
Fig 23b. Switching Time Waveforms
Id
Vds
Vgs
L
DUT
0
20K
1K
VCC
S
Vgs(th)
Qgodr
Fig 24a. Gate Charge Test Circuit
www.irf.com
Qgd
Qgs2 Qgs1
Fig 24b. Gate Charge Waveform
7
IRF1018E/S/SLPbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
TO-220AB Part Marking Information
EXAMPLE: T HIS IS AN IRF 1010
LOT CODE 1789
AS S EMBLED ON WW 19, 2000
IN T HE AS S EMBLY LINE "C"
Note: "P" in as s embly line pos ition
indicates "Lead - Free"
INT ERNAT IONAL
RECT IFIER
LOGO
AS S EMBLY
LOT CODE
PART NUMB ER
DAT E CODE
YEAR 0 = 2000
WEEK 19
LINE C
TO-220AB packages are not recommended for Surface Mount Application.
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
8
www.irf.com
IRF1018E/S/SLPbF
TO-262 Package Outline (Dimensions are shown in millimeters (inches))
TO-262 Part Marking Information
EXAMPLE: THIS IS AN IRL3103L
LOT CODE 1789
AS S EMBLED ON WW 19, 1997
IN T HE AS S EMBLY LINE "C"
PART NUMBER
INT ERNATIONAL
RECTIFIER
LOGO
DAT E CODE
YEAR 7 = 1997
WEEK 19
LINE C
AS S EMBLY
LOT CODE
OR
INT ERNATIONAL
RECTIFIER
LOGO
AS S EMBLY
LOT CODE
PART NUMBER
DAT E CODE
P = DES IGNATES LEAD-FREE
PRODUCT (OPT IONAL)
YEAR 7 = 1997
WEEK 19
A = AS S EMBLY S ITE CODE
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
www.irf.com
9
IRF1018E/S/SLPbF
D2Pak Package Outline (Dimensions are shown in millimeters (inches))
D2Pak Part Marking Information
T HIS IS AN IRF530S WIT H
LOT CODE 8024
AS S EMBLED ON WW 02, 2000
IN T HE AS S EMBLY LINE "L"
INT ERNAT IONAL
RECT IFIER
LOGO
PART NUMBER
F530S
DAT E CODE
YEAR 0 = 2000
WEEK 02
LINE L
AS S EMBLY
LOT CODE
T HIS IS AN IRF530S WIT H
LOT CODE 8024
For GB Production
AS S EMBLED ON WW 02, 2000
IN T HE AS S EMBLY LINE "L"
INT ERNAT IONAL
RECT IFIER
LOGO
PART NUMBER
F530S
LOT CODE
DAT E CODE
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
10
www.irf.com
IRF1018E/S/SLPbF
D2Pak Tape & Reel Information
TRR
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
FEED DIRECTION 1.85 (.073)
1.65 (.065)
1.60 (.063)
1.50 (.059)
11.60 (.457)
11.40 (.449)
0.368 (.0145)
0.342 (.0135)
15.42 (.609)
15.22 (.601)
24.30 (.957)
23.90 (.941)
TRL
10.90 (.429)
10.70 (.421)
1.75 (.069)
1.25 (.049)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
60.00 (2.362)
MIN.
26.40 (1.039)
24.40 (.961)
3
30.40 (1.197)
MAX.
4
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.2/08
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11