TDA8262HN Fully integrated satellite tuner Rev. 01 — 14 December 2004 Product data sheet 1. General description The direct conversion QPSK demodulator is the front-end receiver dedicated to digital TV broadcasting, satisfying both DVB-S and DBS TV standards. The wide range oscillator (from 950 MHz to 2175 MHz) covers the American, European and Asian satellite bands, as well as the SMA-TV US standard. The Zero-IF (ZIF) concept discards traditional IF filtering and intermediate conversion techniques. Gain-controlled amplifiers in the RF guarantee optimum signal level. The variable gain is controlled by the signal returned from the Satellite Demodulator and Decoder (SDD) and applied to pin AGC. The integrated LNA allows the IC to be directly connected to the LNB output. The LNA can be by-passed by an I2C-bus selectable attenuation, providing a 20 dB extra attenuation in order to handle higher input signal levels of up to 0 dBm per channel. An integrated loop-through realizes a copy of the input RF signal for another downconverter. This feature offers a BOM reduction and simplifies the application for dual channel demodulation like watch and record. Connected at the RF input, an RMS level detector provides through I2C-bus read mode the full band input signal level. The LO quadrature outputs are derived from a high performance integrated LC oscillator. f LO f XTAL Its frequency is: -------- = --------------- . Thanks to the low phase noise performance of the N R integrated LC oscillator which controls the LO frequency, the synthesizer offers a good performance for phase noise in the satellite band. The step size of the LO output frequency is equal to the comparison frequency. Control data is entered via the I2C-bus. The bus can be either 5.0 V or 3.3 V, allowing compatibility with most of existing microcontrollers. An 8-byte frame is required to address the device and to program the main divider ratio, the reference divider ratio, the charge-pump current and the operating mode. A flag is set when the loop is in-lock, readable during read operations, as well as the Power-on reset flag and RF input level. The device has four selectable I2C-bus addresses. Applying a specific voltage to pin AS selects an address. This feature gives the possibility to use up to four TDA8262HN ICs in the same system. TDA8262HN Philips Semiconductors Fully integrated satellite tuner 2. Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Direct conversion QPSK and 8PSK demodulation (ZIF) 3.3 V DC supply voltage (no 30 V required) Power-down modes selectable by bus 950 MHz to 2175 MHz frequency range High range input level; ◆ −70 dBm to −15 dBm at 75 Ω (normal mode) ◆ Up to 0 dBm (20 dB attenuation configuration). Low noise RF input (integrated LNA) RF loop-through 0 dB to 55 dB continuous variable gain on RF input RF input level detector Switchable 0 dB to 9 dB additional gain on baseband output amplifier High AGC linearity (< 0.7 dB/step when used with an 8-bit DAC), AGC controlled voltage between 0.3 V and 3 V Programmable 5 MHz to 36 MHz 5th-order baseband filters for I and Q paths Fully integrated PLL frequency synthesizer Low phase noise fully integrated oscillator Operation from a 16 MHz crystal or external clock 5 frequency steps from 125 kHz to 2 MHz Crystal frequency output to drive the demodulator IC Compatible with 5 V and 3.3 V I2C-bus Fully compatible and easy to interface with the PS digital satellite demodulators family 32-pin low thermal resistance package. 3. Applications ■ ■ ■ ■ Direct Broadcasting Satellite (DBS) QPSK demodulation Digital Video Broadcasting (DVB) QPSK demodulation BS digital 8PSK demodulation DVB-S2 8PSK demodulation. 4. Quick reference data Table 1: Quick reference data Symbol Parameter VCC supply voltage ICC supply current fosc oscillator frequency ∆Φ absolute quadrature error Vo(I/Q)(rms) recommended I and Q output voltage RMS value (QPSK signals) fLPF LPF cut-off frequency Conditions measured at 10 MHz [1] 5-bit controlled 9397 750 13194 Product data sheet Min Typ Max Unit 3.15 3.3 3.45 V - 175 - mA 950 - 2175 MHz 0 - 5 degree - 200 - mV - 5 to 36 - MHz © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 01 — 14 December 2004 2 of 30 TDA8262HN Philips Semiconductors Fully integrated satellite tuner Table 1: Quick reference data …continued Symbol Parameter Conditions Min Typ Max Unit ΦNosc oscillator phase noise in the satellite band 100 kHz offset; fcomp = 1 MHz [2] - −100 −94 dBc/Hz SNFSB synthesizer noise floor in the satellite band 1 kHz and 10 kHz offset; fcomp = 1 MHz [2] - - −78 dBc/Hz AGC amplifier gain control range 55 60 - dB Tamb ambient temperature −20 - +85 °C [1] The product is qualified with an output voltage of 550 mV (p-p) differential, however larger values can be used at baseband outputs that might have impact on the product performance. [2] Phase noise in optimal conditions, see related application note. 5. Typical performances • Noise figure at maximum gain: 8 dB • High linearity: – IIP2 = +2 dBm at −20 dBm input and 2.15 GHz – IIP3 = +6 dBm at −20 dBm input and 2.15 GHz. • Low synthesizer noise floor: −78 dBc/Hz at 1 kHz and 10 kHz offset with fcomp = 1 MHz • • • • AGC linearity: < 0.7 dB/step with a 8-bit DAC Maximum I/Q amplitude mismatch: 1 dB Maximum I/Q quadrature mismatch: 5° Symbol rates: from 1 MBd to 45 MBd. 6. Ordering information Table 2: Ordering information Type number Package Name TDA8262HN Description HVQFN32 plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 × 5 × 0.85 mm 9397 750 13194 Product data sheet Version SOT617-1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 01 — 14 December 2004 3 of 30 TDA8262HN Philips Semiconductors Fully integrated satellite tuner 7. Block diagram AGC PORT0 9 8 loop-through RFOUT VCC(LT) GND(LT) RFIN PORT1 32 10 6 15 TDA8262HN buffer 4 5 MHz to 36 MHz filter 2 0 dB to +9 dB variation gain 14 LNA 13 3 11 ATT VCC(RF) GND(RF) 7 IP IN QP QN 1 5 LEVEL DETECTOR 3 GND(DIE) 12 AGC control 5 VCC(BB) GND(BB) 1 3 LATCH AND CONTROL BIT 0° 90° I 2 C-BUS INTERFACE 29 30 17 SDA SCL AS 15-BIT DIVIDER XTOUT 15 × I/Q outputs wide band integrated oscillator 19 21 VCC(VCO) GND(VCO) XTOUT 3 26 LOW-NOISE INTEGRATED LC OSCILLATOR N2 N1 25 REFERENCE DIVIDER CRYSTAL OSCILLATOR 27 16 XT XTN MS 3, 2 LOCK DETECTOR 23 24 VCC(PLL) 18 20 CAPVCO 1 22 VT CP POWER-ON RESET 28 1 31 VCC(DIG) 001aab034 GND(DIG) GND(PLL) Fig 1. Block diagram 9397 750 13194 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 01 — 14 December 2004 4 of 30 TDA8262HN Philips Semiconductors Fully integrated satellite tuner 8. Pinning information 25 XTOUT 26 XT 27 XTN 28 VCC(DIG) 29 SDA 30 SCL terminal 1 index area 31 GND(DIG) 32 PORT1 8.1 Pinning GND(DIE) 1 24 GND(PLL) GND(LT) 2 23 VCC(PLL) RFIN 3 22 CP VCC(LT) 4 GND(RF) 5 RFOUT 6 19 VCC(VCO) VCC(RF) 7 18 CAPVCO PORT0 8 17 AS 21 GND(VCO) MS 16 20 VT GND(BB) 15 IP 14 IN 13 QN 12 QP 11 9 AGC VCC(BB) 10 TDA8262HN 001aab001 Transparent top view Fig 2. Pin configuration 8.2 Pin description Table 3: Pin description Symbol Pin Description GND(DIE) 1 isolation ground GND(LT) 2 LNA and loop-through ground RFIN 3 RF input VCC(LT) 4 LNA and loop-through supply voltage GND(RF) 5 RF ground RFOUT 6 RF output VCC(RF) 7 RF supply voltage PORT0 8 pull-down port 0 AGC 9 automatic gain control input VCC(BB) 10 baseband supply voltage QP 11 Q positive output QN 12 Q negative output IN 13 I negative output IP 14 I positive output GND(BB) 15 baseband ground MS 16 master/slave crystal oscillator mode input AS 17 address select input CAPVCO 18 internal LC VCO regulation capacitor 9397 750 13194 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 01 — 14 December 2004 5 of 30 TDA8262HN Philips Semiconductors Fully integrated satellite tuner Table 3: Pin description …continued Symbol Pin Description VCC(VCO) 19 VCO supply voltage VT 20 VCO tuning voltage input GND(VCO) 21 VCO ground CP 22 charge pump output VCC(PLL) 23 PLL supply voltage GND(PLL) 24 PLL ground XTOUT 25 16 MHz frequency for external ICs output XT 26 16 MHz crystal oscillator input XTN 27 16 MHz crystal oscillator input VCC(DIG) 28 digital supply voltage SDA 29 I2C-bus data input/output SCL 30 I2C-bus clock input GND(DIG) 31 digital ground PORT1 32 pull-down port 1 9. Tuner configuration 16 MHz RF input MPEG2 stream I/Q base band AGC control RF output TDA8262HN 16 MHz I 2 C-bus TDA10086 I 2 C-bus 001aab032 Fig 3. Tuner configuration for one channel 9397 750 13194 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 01 — 14 December 2004 6 of 30 TDA8262HN Philips Semiconductors Fully integrated satellite tuner RF loop-through RF input 16 MHz TDA8262HN RF output TDA8262HN I 2 C-bus AGC control I/Q base band AGC control I/Q base band I 2 C-bus 16 MHz MPEG2 streams TDA10093 I 2 C-bus 001aab033 Fig 4. Tuner configuration for two channels (watch and record) 10. Functional description The TDA8262HN contains the core of the RF analog part of a digital satellite receiver. The signal coming from the LNB is coupled to the RF inputs. The internal circuitry performs the Zero-IF quadrature frequency conversion and two in-phase (IP/IN) and two quadrature (QP/QN) output signals can directly be used to feed a Satellite Demodulator and Decoder circuit (SDD). Low pass filter cut-off frequency can be adjusted from 5 MHz to 36 MHz in 32 steps. This allows a large flexibility in the SDD input. 10 gain values are present at output amplifier to compensate cut-off frequency adjustment and single output application. The IC gain controlled amplifier before the mixer is controlled by the SDD through pin AGC. An input level detector gives the wide band RF level. This information is available through I2C-bus in read mode. The internal loop controls a fully integrated VCO, to cover the range from 950 MHz to 2175 MHz. This VCO provides both in phase and quadrature signals to drive the two mixers. The output of the 15-bit programmable divider passes through the phase comparator where it is compared in both phase and frequency to the comparison frequency (fcomp). This fcomp is derived from the signal present at the XT/XTN pins (fXTAL), divided down in the reference divider. The buffered signal on pin XTOUT is able to drive the crystal frequency input of the SDD, which saves a crystal in the application. 9397 750 13194 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 01 — 14 December 2004 7 of 30 TDA8262HN Philips Semiconductors Fully integrated satellite tuner The output of the phase comparator drives the charge pump and loop amplifier section. Pin CP is the output of the charge pump, and pin VT drives the tuning voltage to the varicap diode of the voltage controlled oscillator. The loop filter has to be connected between pins CP and VT. For test and alignment purposes, it is possible to release the tuning voltage output and to apply an external voltage on the VT pin, as well as to select the charge pump sink, source or off. Three independent area of power-down are available by programming I2C-bus: • Loop-through part • RF and synthesizer part • Crystal oscillator and XTOUT part. 10.1 Gain distribution RFATT AGC LNA/ATT AGC 12 dB −8 dB 24 dB BBGAIN [3:0] 10.2 dB 9 dB 10.2 dB 10.2 dB −37 dB 001aaa977 Fig 5. Gain distribution; typical values 11. Programming The programming of the TDA8262HN is done through the I2C-bus. The READ/WRITE selection is done through the R/W bit (address LSB). The TDA8262 fulfils the fast mode I2C-bus specification, according to the Philips I2C-bus specification, see document 9398 393 40011. 11.1 I2C-bus inputs The I2C-bus lines SCL and SDA can be connected to an I2C-bus system tied to either 3.3 V or 5.0 V, which allows direct connection to most of existing microcontrollers. Data transfer format should be MSB first, and 8-bit word + acknowledge bit. Pins used for the I2C-bus: • Pin SCL is the clock input • Pin SDA is the data input/output 9397 750 13194 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 01 — 14 December 2004 8 of 30 TDA8262HN Philips Semiconductors Fully integrated satellite tuner • Pin AS is for address selection. 11.2 Address selection Table 4: Address selection (pin AS) Voltage on pin AS Write address Read address 0 V to 0.1 × VCC C0 C1 0.2 × VCC to 0.3 × VCC or open pin C2 C3 0.4 × VCC to 0.6 × VCC C4 C5 0.9 × VCC to VCC C6 C7 11.3 Master-slave selection Table 5: Master-slave selection (pin MS) Voltage on pin MS Crystal oscillator mode 0 V to 0.1 × VCC master 0.9 × VCC to VCC slave 11.4 Data transfer in write mode The data transfer in write mode use the following pattern: I2C-bus write mode data transfer pattern Table 6: START address ack subaddress ack data 1 ack data 2 ack data n ack STOP Subaddress is automatically incremented starting from the initial value. 11.5 I2C-bus table in write mode Table 7: I2C-bus write mode map Subaddress (hex) MSB 0X LSB 7 6 PDPLL PDZIF 5 4 PDLOOPT PDXTOUT 3 2 1 0 PDRSSI PDLNA PDXTAL TEST1 1X R2 R1 R0 D4 D3 D2 D1 D0 2X N14 N13 N12 N11 N10 N9 N8 N7 3X N6 N5 N4 N3 N2 N1 N0 CALMANUAL 4X FC4 FC3 FC2 FC1 FC0 - - - 5X BBGAIN3 BBGAIN2 BBGAIN1 BBGAIN0 - - - RFATT 6X CPCURSEL CPTST FUP FDN CP2TST FPFD2 CPHIGH - 7X AMPVCO2 AMPVCO1 AMPVCO0 - - - PORT1 PORT0 8X CALTIME - - SELVTH1 SELVTH0 SELVTL1 SELVTL0 - 9X BBIAS3 BBIAS2 BBIAS1 BBIAS0 - - - - 9397 750 13194 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 01 — 14 December 2004 9 of 30 TDA8262HN Philips Semiconductors Fully integrated satellite tuner 11.6 I2C-bus table in write mode (default at POR) Table 8: I2C-bus write mode map (default at POR) [1] Subaddress (hex) MSB LSB 7 6 5 4 3 2 1 0 0X 0 0 0 0 1 0 0 1 1X 0 0 1 0 0 0 0 0 2X 0 0 0 0 0 0 0 1 3X 0 0 0 0 0 0 0 1 4X 0 0 0 0 0 - - - 5X 0 0 0 0 - - - 0 6X 0 0 X X 0 X 0 - 7X 1 0 0 - - - 0 0 8X 0 - - 0 0 0 0 - 9X 0 0 0 0 - - - - [1] X means don’t care. 11.7 Bit description I2C-bus write mode Table 9: Power-down section Bit Description State PDPLL power-down of all the synthesizer part 0 = function on; 1 = function off PDZIF power-down of all signal decoding part except LNA, RSSI and loop-through 0 = function on; 1 = function off PDLOOPT power-down of the loop-through 0 = function on; 1 = function off PDXTOUT power-down of the XTOUT output 0 = function on; 1 = function off PDRSSI power-down of the input level detector (RSSI) 0 = function on; 1 = function off PDLNA power-down of the low noise amplifier 0 = function on; 1 = function off PDXTAL power-down of the crystal oscillator 0 = function on; 1 = function off TEST1 used for test purposes only must be logic 1 Table 10: Reference divider range; bits R[2:0] These bits select the ratio between the comparison frequency and the crystal frequency. R2 R1 R0 Decimal Comparison frequency 0 0 0 0 2 MHz 0 0 1 1 1 MHz 0 1 0 2 500 kHz 0 1 1 3 250 kHz 1 0 0 4 125 kHz 1 0 1 5 125 kHz 1 1 0 6 125 kHz 1 1 1 7 125 kHz 9397 750 13194 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 01 — 14 December 2004 10 of 30 TDA8262HN Philips Semiconductors Fully integrated satellite tuner Table 11: VCO preprogramming range; bits D[4:0] These bits are also called Dword: It determines the ratio between LO frequency and VCO frequency. The bits are used for the calibration protocol of the internal VCO. D4 D3 D2 D1 D0 Decimal Ratio fLO to fVCO 0 0 0 0 0 0 0.27 0 0 0 0 1 1 0.29 0 0 0 1 0 2 0.31 0 0 0 1 1 3 0.33 0 0 1 0 0 4 0.36 0 0 1 0 1 5 0.36 0 0 1 1 0 6 0.38 0 0 1 1 1 7 0.40 0 1 0 0 0 8 0.42 0 1 0 0 1 9 0.43 0 1 0 1 0 10 0.44 0 1 0 1 1 11 0.45 0 1 1 0 0 12 0.46 0 1 1 0 1 13 0.47 0 1 1 1 0 14 0.50 0 1 1 1 1 15 0.54 1 0 0 0 0 16 0.55 1 0 0 0 1 17 0.56 1 0 0 1 0 18 0.58 1 0 0 1 1 19 0.60 1 0 1 0 0 20 0.63 1 0 1 0 1 21 0.64 1 0 1 1 0 22 0.67 1 0 1 1 1 23 0.70 1 1 0 0 0 24 0.75 1 1 0 0 1 25 0.78 1 1 0 1 0 26 0.88 1 1 0 1 1 27 0.88 1 1 1 0 0 28 0.88 1 1 1 0 1 29 0.88 1 1 1 1 0 30 0.88 1 1 1 1 1 31 0.88 Table 12: Main divider range; bits N[14:0] These bits control the ratio between the LO frequency and the comparison frequency. N[14:0] Ratio Binary value The ratio N is equal to N14 × 214 + N13 × 213 + ...N1 × 21 + N0 9397 750 13194 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 01 — 14 December 2004 11 of 30 TDA8262HN Philips Semiconductors Fully integrated satellite tuner Table 13: Selects manual or automatic LC oscillator calibration; bit CALMANUAL This bit controls the LC VCO frequency programming mode. CALMANUAL Action 0 automatic process control; the LC VCO searches the better ratio of the Dword to have the optimum tuning frequency 1 manual process control; the LC VCO is tuned by selecting the programmed Dword Table 14: RX baseband cut-off frequency control; bits FC[4:0]: The register selects the cut-off frequency of the RX baseband filter. The cut-off frequency can be set from 5 MHz to 36 MHz in 32 steps of 1 MHz FC4 FC3 FC2 FC1 FC0 Decimal Baseband cut-off frequency (MHz) [1] 0 0 0 0 0 0 5 0 0 0 0 1 1 6 0 0 0 1 0 2 7 0 0 0 0 1 1 3 8 0 1 0 0 4 9 0 0 1 0 1 5 10 0 0 1 1 0 6 11 0 0 1 1 1 7 12 0 1 0 0 0 8 13 0 1 0 0 1 9 14 0 1 0 1 0 10 15 0 1 0 1 1 11 16 0 1 1 0 0 12 17 0 1 1 0 1 13 18 0 1 1 1 0 14 19 0 1 1 1 1 15 20 1 0 0 0 0 16 21 1 0 0 0 1 17 22 1 0 0 1 0 18 23 1 0 0 1 1 19 24 1 0 1 0 0 20 25 1 0 1 0 1 21 26 1 0 1 1 0 22 27 1 0 1 1 1 23 28 1 1 0 0 0 24 29 1 1 0 0 1 25 30 1 1 0 1 0 26 31 1 1 0 1 1 27 32 1 1 1 0 0 28 33 9397 750 13194 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 01 — 14 December 2004 12 of 30 TDA8262HN Philips Semiconductors Fully integrated satellite tuner Table 14: RX baseband cut-off frequency control; bits FC[4:0]: …continued The register selects the cut-off frequency of the RX baseband filter. The cut-off frequency can be set from 5 MHz to 36 MHz in 32 steps of 1 MHz [1] FC4 FC3 FC2 FC1 FC0 Decimal Baseband cut-off frequency (MHz) [1] 1 1 1 0 1 1 1 1 1 29 34 0 30 35 1 1 1 1 1 31 36 Typical values at nominal process and room temperature. Table 15: RX baseband gain control; bits BBGAIN[3:0] These bits control the additional gain of the baseband between 0 dB and 9dB BBGAIN2 BBGAIN1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 2 0 0 0 1 1 3 0 0 1 0 0 4 0 0 1 0 1 5 1.6 0 1 1 0 6 3 0 1 1 1 7 4.6 1 0 0 0 8 6.3 1 0 0 1 9 7.3 1 0 1 0 10 8.2 1 0 1 1 11 8.5 1 1 0 0 12 8.8 1 1 0 1 13 8.8 1 1 1 0 14 9 1 1 1 1 15 9 [1] BBGAIN0 Decimal Additional gain in dB [1] BBGAIN3 Typical values at nominal process and room temperature. Table 16: 20 dB RF attenuation control; bit RFATT This bit controls the RF attenuation inside the LNA amplifier. RFATT Table 17: Action 0 normal gain of RF path 1 20 dB attenuation. When active, the LNA works in attenuation (−8 dB gain). The loop-through signal is also attenuated by 20 dB. Select main loop charge-pump current; bit CPCURSEL CPCURSEL Action 0 low charge-pump current 1 high charge-pump current 9397 750 13194 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 01 — 14 December 2004 13 of 30 TDA8262HN Philips Semiconductors Fully integrated satellite tuner Table 18: Main loop charge pump test; bits CPTST, FUP and FDN These bits force the inputs of the main loop charge pump. Thus the current and leakage measurement could be done. This test could be used also to force the LC VCO at its maximum or minimum tuning voltage. CPTST FUP FDN Actions 0 X X test disable 1 0 0 sink and source off; leakage measurement 1 0 1 sink off and source on; source measurement 1 1 0 sink on and source off; sink measurement 1 1 1 sink on and source on Table 19: Second loop charge pump test; bits CP2TST and FPFD2 These bits force the inputs of the second loop charge pump. This test could be used to force the LO VCO at its maximum or minimum tuning voltage. CP2TST FPFD2 0 X test disable 1 0 sink on and source off; LO VCO maximum frequency measurement 1 1 sink off and source on; LO VCO minimum frequency measurement Table 20: Actions Select main loop charge-pump current; bit CPHIGH CPHIGH Action 0 first charge pump active (low currents) 1 second charge pump active (high currents) Table 21: Amplitude of the internal VCO; bits AMPVCO[2:0] These bits control the amplitude of the internal LC VCO. AMPVCO[2:0] Value Binary value The allowed value is AMPVCO[2:0] = 100 (decimal 4). The product is specified only with this value, other settings may lead to different performance. Table 22: Control port output; bits PORT[1:0] Bit PORT1 controls the use of PORT1 and bit PORT0 controls the use of PORT0. Outputs PORTn are realized with open-drain NMOS transistors. PORTn Action 0 PORTn at high-impedance 1 PORTn in sink mode; minimum 9 mA drive capability Table 23: Calibration wait time control; bit CALTIME This bit controls the duration of the wait time of the calibration. This time is used to wait PLL locking after programming a Dword. The reference clock of the time is the comparison frequency of the PLL CALTIME fc divider ratio Wait time for fcomp = 1 MHz (ms) 0 28673 28.673 1 32769 32.769 9397 750 13194 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 01 — 14 December 2004 14 of 30 TDA8262HN Philips Semiconductors Fully integrated satellite tuner Table 24: Maximum voltage tuning threshold for calibration control; bits SELVTH[1:0] These bits control the voltage threshold for the ACUP comparator. The ACUP and ACDN comparators sense the LC VCO tuning voltage at pin VT. SELVTH1 SELVTH0 Decimal Threshold VTH (V) [1] [2] 0 0 0 1.8 0 1 1 1.9 1 0 2 2.0 1 1 3 2.1 [1] Typical values at nominal process and room temperature. [2] The recommended value is SELVTH[1:0] = 11 (decimal 3). Table 25: Minimum voltage tuning threshold for calibration control; bits SELVTL[1:0] These bits control the voltage threshold for the ACDN comparator. The ACUP and ACDN comparators sense the LC VCO tuning voltage at pin VT. SELVTL1 SELVTL0 Decimal Threshold VTL (V) [1] [2] 0 0 0 0.6 0 1 1 0.5 1 0 2 0.4 1 1 3 0.3 [1] Typical values at nominal process and room temperature. [2] The recommended value is SELVTL[1:0] = 01 (decimal 1). Table 26: Baseband bias current control; bits BBIAS[3:0] This register modifies the baseband bias current through different parts: Output buffer or other amplifier. BBIAS[3:0] Value Binary value The allowed value is BBIAS[3:0] = 1101 (decimal 13). The product is specified only with this value, other settings may lead to different performance. 11.8 Data transfer in read mode The data transfer in read mode use the following pattern. Table 27: I2C-bus read mode data transfer pattern START address ack data 1 ack data 2 ack STOP 11.9 I2C-bus table in read mode Table 28: Byte I2C-bus read mode map [1] MSB LSB 7 6 5 4 3 2 1 0 0 POR LOCK ACUP ACDN ERRORCAL X X X 1 1 INLEVEL1 INLEVEL0 DW4 DW3 DW2 DW1 DW0 [1] X can be 1 or 0 and needs to be masked in the microcontrollers’ software; MSB is transmitted first. 9397 750 13194 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 01 — 14 December 2004 15 of 30 TDA8262HN Philips Semiconductors Fully integrated satellite tuner 11.10 Bit description I2C-bus read mode Table 29: Power-on reset; bit POR POR Action 0 Normal operation 1 This bit is set to logic 1 at the VCC(DIG) power supply ramp-up. It is reset to logic 0 after the first read of the IC. When VCC(DIG) falls below 2 V typical, this bit is set to logic 1. This is to prevent loss in internal I2C-bus registers programming. Table 30: Synthesizer lock indicator; bit LOCK LOCK Action 0 synthesizer is not locked 1 synthesizer is locked Table 31: Auto calibration up threshold control; bit ACUP ACUP Action 0 LC VCO tuning voltage is lower than VTH (see Table 24) 1 LC VCO tuning voltage is higher than VTH (see Table 24) Table 32: Auto calibration down threshold control; bit ACDN ACDN Action 0 LC VCO tuning voltage is higher than VTL (see Table 25) 1 LC VCO tuning voltage is lower than VTL (see Table 25) Table 33: Calibration defect detection; bit ERRORCAL ERRORCAL Action 0 no defect detected 1 calibration unit control tries to go lower than the minimum or higher than the maximum Dword ratio Table 34: RF input level indicator; bits INLEVEL[1:0] This register gives the RF input level in dBm INLEVEL1 INLEVEL0 Decimal [1] RF power (dBm) [1] 0 0 0 < −30 0 1 1 −30 to −20 1 0 2 −20 to −15 1 1 3 > −15 Typical values at nominal process and room temperature. Values are valid only when LNA path is selected (bit RFATT = 0). Table 35: Internal Dword register; bits DW[4:0] This register gives the internal Dword value. This value could be the programmed D[4:0] value in manual mode or the calculated value after LC VCO calibration in automatic mode. DW[4:0] Description Binary value The fLO to fVCO ratio is the same as shown in Table 11 9397 750 13194 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 01 — 14 December 2004 16 of 30 TDA8262HN Philips Semiconductors Fully integrated satellite tuner 12. Internal circuitry Table 36: Internal circuitry Symbol Pin RFIN 3 Equivalent circuit RFIN 001aaa979 GND(RF) RFOUT 6 RFOUT GND(RF) 001aab036 PORT0 8 PORT0 test GND(RF) AGC 001aaa980 9 50 kΩ 21 kΩ AGC GND(BB) 35 kΩ 001aaa981 QP 11 QP GND(BB) 001aaa982 QN 12 QN GND(BB) 001aaa983 9397 750 13194 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 01 — 14 December 2004 17 of 30 TDA8262HN Philips Semiconductors Fully integrated satellite tuner Table 36: Internal circuitry …continued Symbol Pin IN 13 Equivalent circuit IN GND(BB) 001aaa984 IP 14 IP GND(BB) 001aaa985 MS 16 500 Ω MS GND(BB) AS 001aaa986 17 500 Ω AS GND(PLL) test 001aaa987 CAPVCO 18 5 kΩ CAPVCO GND(PLL) 001aaa988 VT 20 100 Ω VT GND(PLL) 001aaa989 9397 750 13194 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 01 — 14 December 2004 18 of 30 TDA8262HN Philips Semiconductors Fully integrated satellite tuner Table 36: Internal circuitry …continued Symbol Pin CP 22 Equivalent circuit CP GND(PLL) 001aaa990 XTOUT 25 XTOUT GND(PLL) 001aaa991 XT 26 XT GND(PLL) 001aaa992 XTN 27 XTN GND(PLL) 001aaa993 SDA 29 500 Ω SDA GND(DIG) 001aaa994 SCL 30 500 Ω SCL GND(DIG) 001aaa995 9397 750 13194 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 01 — 14 December 2004 19 of 30 TDA8262HN Philips Semiconductors Fully integrated satellite tuner Table 36: Internal circuitry …continued Symbol Pin PORT1 32 Equivalent circuit 500 Ω CMOS logic PORT1 test GND(DIG) test 001aaa996 13. Limiting values Table 37: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). [1] Symbol Parameter Conditions VCC supply voltage VI input voltage Min Max Unit −0.5 +3.6 V pins SDA, SCL, PORT1 and PORT0 −0.3 +5.5 V pin RFIN −0.3 VCC − 0.3 V VCC < 3.3 V −0.3 VCC + 0.3 V VCC ≥ 3.3 V all other pins −0.3 +3.6 V Tamb ambient temperature −20 +85 °C Tstg storage temperature −40 +125 °C Tj junction temperature - 125 °C - 10 s tsc short circuit time Vesd electrostatic discharge voltage [2] human body model - ±1000 V all other pins [3] - ±2000 V machine model [4] - ±200 V pin PORT0 (pin 8) [1] Maximum ratings cannot be exceeded, not even momentarily without causing irreversible damages to the IC. Maximum ratings cannot be accumulated. [2] Each pin to VCC or GND; except RFIN pin which should never exceed VCC − 0.3 V. [3] Test in accordance with JEDEC specification EIA/JESD22-114B. [4] Test in accordance with JEDEC specification EIA/JESD22-A115-A. 14. Thermal characteristics Table 38: Thermal characteristics Symbol Parameter Conditions Typ Unit Rth(j-a) thermal resistance junction to ambient JEDEC 4 layer test board with 9 thermal vias (exposed die pad soldered on board) 43 K/W 9397 750 13194 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 01 — 14 December 2004 20 of 30 TDA8262HN Philips Semiconductors Fully integrated satellite tuner 15. Characteristics Table 39: Characteristics Tamb = 25 °C; VCC = 3.3 V; output level on differential I/Q output is 550 mV (p-p); unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Supply VCC supply voltage ICC supply current VPOR 3.15 3.3 3.45 V all power-down bits are 0 - 175 - mA all power-down bits are 1 - 6 - mA only bits PDXTOUT and PDXTAL are 0 - 30 - mA only bits PDLNA and PDLOOPT are 0 - 45 - mA 1.5 - 2.5 V - −85 - dBm voltage limit when POR is active RF and Baseband LOL(RFIN) LO leakage through RF inputs Zi input impedance - 75 - Ω Zo(l-t)i loop-through output impedance - 75 - Ω ZL(I/Q)(max) maximum load on each IP, IN, QP and QN output single mode LNA to loop-through gain GLT between 950 MHz and 2175 MHz - 10 - pF - 1 - kΩ LNA configuration −2 - 2 dB attenuated configuration - −18 - dB LOL(RFOUT) LO leakage on pin RFOUT - −85 - dBm RFisolation isolation between loop-through and RF input - 30 - dB VO(I/Q) DC voltage on I/Q output - 1.65 - V between 950 MHz and 2175 MHz ∆Gv(BB)(min) minimum baseband additional gain BBGAIN [3:0] = 0h - 0 - dB ∆Gv(BB)(max) maximum baseband additional gain BBGAIN [3:0] = Fh - 9 - dB Vo(I/Q)(p-p) typical AC output voltage on differential voltage differential I/Q output; peak-to-peak value - 550 - mV Vo(I/Q)(rms) recommended I and Q output voltage RMS value (QPSK signals) [1] - 200 - mV IIP2 second-order interception point at RF input fi = 2150 MHz; PRFIN = −20 dBm [2] - 2 - dBm IIP3 third-order interception point at RF input PRFIN = −20 dBm [3] fi = 2150 MHz - 6 - dBm fi = 950 MHz - 0 - dBm F noise figure maximum gain; VAGC = 3 V - 7.7 8.5 dB Gv(I-Q)(M) voltage gain mismatch between I and Q measured at 10 MHz; fLPF = 36 MHz - - 1 dB Gv(I/Q)(R) voltage gain ripple for I or Q fLPF = 36 MHz; 22.5 MHz band - - 2 dB ∆Φ absolute quadrature error measured at 10 MHz; fLPF = 36 MHz 0 - 5 degree td(g)(I-Q) group delay mismatch in between I and Q fLPF = 36 MHz; 22.5 MHz band - 0 - ns 9397 750 13194 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 01 — 14 December 2004 21 of 30 TDA8262HN Philips Semiconductors Fully integrated satellite tuner Table 39: Characteristics …continued Tamb = 25 °C; VCC = 3.3 V; output level on differential I/Q output is 550 mV (p-p); unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit td(g)(I/Q)(R) group delay ripple for I or Q fLPF = 36 MHz; 22.5 MHz band - 5 - ns α60(I/Q) rejection at 60 MHz for I and Q fLPF = 36 MHz - 30 - dB fLPF(min) minimum filter cut-off frequency FC [4:0] = 00h - 5 - MHz fLPF(max) maximum filter cut-off frequency FC [4:0] = 1Fh - 36 - MHz Voltage gain from RF input to IP, IN, QP and QN outputs; differential output; fLPF = 36 MHz; BBGAIN[3:0] = 0h. Gv(LNA)(min) minimum voltage gain for LNA configuration Gv(LNA)(max) maximum voltage gain for LNA configuration VAGC = 0.3 V - 6 - dB VAGC = 3 V - 67 - dB Gv(a)(min) minimum voltage gain for attenuated configuration VAGC = 0.3 V - −14 - dB Gv(a)(max) maximum voltage gain for attenuated configuration VAGC = 3 V - 47 - dB AGC amplifier gain control range 55 60 - dB 2175 MHz VCO and synthesizer VCO oscillator frequency range fosc ΦNosc oscillator phase noise in the satellite band 100 kHz offset, out of the PLL bandwidth [4] SNFSB synthesizer noise floor in the satellite band 1 kHz and 10 kHz offset; fcomp = 1 MHz [4] MDR main divider ratio 950 - - −100 −94 dBc/Hz - - −78 dBc/Hz 128 - 32767 500 - - Ω Crystal oscillator and XTOUT Zosc crystal oscillator negative impedance absolute value fXTAL crystal frequency 16 16 16 MHz ZXTAL recommended crystal series resistance - - 150 Ω Vo(p-p) output voltage (peak-to-peak value) crystal oscillator output 550 750 - mV Ih high level input current VMS = VCC −50 - +50 µA Il low level input current VMS = 0 V −50 - +50 µA −10 0 +10 nA MS input Charge pump and tuning voltage IL charge pump leakage current Il(min) charge pump low; min current CPHIGH = 0 and CPCURSEL = 0 0.67 0.9 1.13 mA Il(max) charge pump low; max current CPHIGH = 0 and CPCURSEL = 1 0.97 1.3 1.63 mA Ih(min) charge pump high, min current CPHIGH = 1 and CPCURSEL = 0 1.27 1.7 2.13 mA Ih(max) charge pump high, max current CPHIGH = 1 and CPCURSEL = 1 1.87 2.5 3.13 mA I2C-bus and PORTn SDA/SCL input VIL LOW-level input voltage 5 V and 3.3 V bus - - 0.99 V VIH HIGH-level input voltage 5 V and 3.3 V bus 2.3 - - V 9397 750 13194 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 01 — 14 December 2004 22 of 30 TDA8262HN Philips Semiconductors Fully integrated satellite tuner Table 39: Characteristics …continued Tamb = 25 °C; VCC = 3.3 V; output level on differential I/Q output is 550 mV (p-p); unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit IHI HIGH-level leakage current VIH = 3.3 V; VCC = 0 V or 3.3 V - - 10 µA ILI LOW-level leakage current VIL = 0 V; VCC = 3.3 V −10 - - µA fSCL input clock frequency - - 400 kHz - - 0.4 V SDA output output voltage during acknowledge VO Isink = 3 mA AS input IASh high level input current VAS = VCC −100 - +100 µA IASl low level input current VAS = 0 V −100 - +100 µA PORTn maximum output voltage Isink = 9 mA - - 0.4 V PORTn VO [1] The product is qualified with an output voltage of 550 mV (p-p) differential, however larger values can be used at baseband outputs that might have impact on the product performance. [2] IIP2 = −20 + (P1 − P2) [dBm]. Wanted signal: RF1 is 2140 MHz, PRFIN = −20 dBm, and the AGC adjusted to get 550 mV (p-p) on the differential output. The output level is P1. Unwanted signal: RF1 is 1040 MHz and PRFIN = −20 dBm and RF2 is 1100 MHz and PRFIN = −20 dBm. The output level of (RF1 + RF2) on the output pins is P2. [3] IIP3 = −23 + ----------- [dBm], see Figure 6 IM3 2 Wanted signal: RF1 is LO + 5 MHz, PRFIN = −20 dBm, and the AGC adjusted to get 550 mV (p-p) on the differential output. Unwanted signal: RF1 is LO + 5 MHz and PRFIN = −23 dBm and RF2 is LO + 7 MHz and Pin = −23 dBm [4] Phase noise in optimal conditions, see related application note. 3 MHz 5 MHz 7 MHz 9 MHz IM3 f1 f2 001aac085 IM3 is the difference between the wanted signal and the unwanted signal (2f1 − f2) and (2f2 − f1) on output pins Fig 6. Base band spectrum 9397 750 13194 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 01 — 14 December 2004 23 of 30 TDA8262HN Philips Semiconductors Fully integrated satellite tuner 16. Application information SCL SDA 16 MHz 3.3 V 39 pF GND(DIE) GND(LT) 10 pF RFIN RFIN VCC(LT) GND(RF) XTOUT 25 XT 26 XTN 27 VCC(DIG) 28 SDA 29 SCL 23 3 22 4 21 TDA8262HN 5 20 RFOUT 6 VCC(RF) 7 PORT0 8 19 18 1 kΩ VCC(PLL) 1 nF CP 68 nF GND(VCO) VT 4.7 kΩ VCC(VCO) 100 pF CAPVCO AS 100 nF 39 pF 16 15 14 13 12 GND(PLL) 3.3 V MS GND(BB) IP IN QN AGC AGC 11 17 VCC(BB) 3.3 V 39 pF 2 9 39 pF 3.3 V 24 10 RFOUT XTOUT 1 QP 10 pF 30 GND(DIG) 32 39 pF 100 nF 31 PORT1 3.3 V 39 pF 39 pF 001aab035 39 pF 3.3 V IP IN QN QP Fig 7. Typical application circuit 9397 750 13194 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 01 — 14 December 2004 24 of 30 TDA8262HN Philips Semiconductors Fully integrated satellite tuner 17. Package outline HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm A B D SOT617-1 terminal 1 index area A A1 E c detail X C e1 e 1/2 e 16 y y1 C v M C A B w M C b 9 L 17 8 e e2 Eh 1/2 e 1 terminal 1 index area 24 32 25 X Dh 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D (1) Dh E (1) Eh e e1 e2 L v w y y1 mm 1 0.05 0.00 0.30 0.18 0.2 5.1 4.9 3.25 2.95 5.1 4.9 3.25 2.95 0.5 3.5 3.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT617-1 --- MO-220 --- EUROPEAN PROJECTION ISSUE DATE 01-08-08 02-10-18 Fig 8. Package outline SOT617-1 (HVQFN32) 9397 750 13194 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 01 — 14 December 2004 25 of 30 TDA8262HN Philips Semiconductors Fully integrated satellite tuner 18. Handling information Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be completely safe, it is desirable to take normal precautions appropriate to handling integrated circuits. 19. Soldering 19.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 19.2 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 °C to 270 °C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: • below 225 °C (SnPb process) or below 245 °C (Pb-free process) – for all BGA, HTSSON..T and SSOP..T packages – for packages with a thickness ≥ 2.5 mm – for packages with a thickness < 2.5 mm and a volume ≥ 350 mm3 so called thick/large packages. • below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. 19.3 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: 9397 750 13194 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 01 — 14 December 2004 26 of 30 TDA8262HN Philips Semiconductors Fully integrated satellite tuner • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 19.4 Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 °C and 320 °C. 19.5 Package related soldering information Table 40: Suitability of surface mount IC packages for wave and reflow soldering methods Package [1] Soldering method Wave Reflow [2] BGA, LBGA, LFBGA, SQFP, SSOP..T [3], TFBGA, VFBGA, XSON not suitable suitable DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS not suitable [4] suitable PLCC [5], SO, SOJ suitable suitable HTSSON..T [3], suitable LQFP, QFP, TQFP not SSOP, TSSOP, VSO, VSSOP not recommended [7] suitable CWQCCN..L [8], not suitable not suitable [1] PMFP [9], WQCCN..L [8] For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. 9397 750 13194 Product data sheet recommended [5] [6] © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 01 — 14 December 2004 27 of 30 TDA8262HN Philips Semiconductors Fully integrated satellite tuner [2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. [3] These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. [4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [5] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. [6] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [7] Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. [8] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. [9] Hot bar soldering or manual soldering is suitable for PMFP packages. 20. Revision history Table 41: Revision history Document ID Release date Data sheet status TDA8262HN_1 20041214 Product data sheet Change notice 9397 750 13194 Product data sheet Doc. number Supersedes 9397 750 13194 - © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 01 — 14 December 2004 28 of 30 TDA8262HN Philips Semiconductors Fully integrated satellite tuner 21. Data sheet status Level Data sheet status [1] Product status [2] [3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 22. Definitions customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 23. Disclaimers 24. Licenses Purchase of Philips I2C-bus components Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors Purchase of Philips I2C-bus components conveys a license under the Philips’ I2C-bus patent to use the components in the I2C-bus system provided the system conforms to the I2C-bus specification defined by Koninklijke Philips Electronics N.V. This specification can be ordered using the code 9398 393 40011. 25. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: [email protected] 9397 750 13194 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 01 — 14 December 2004 29 of 30 TDA8262HN Philips Semiconductors Fully integrated satellite tuner 26. Contents 1 2 3 4 5 6 7 8 8.1 8.2 9 10 10.1 11 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 11.10 12 13 14 15 16 17 18 19 19.1 19.2 19.3 19.4 19.5 20 21 22 23 24 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Typical performances . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Tuner configuration . . . . . . . . . . . . . . . . . . . . . . 6 Functional description . . . . . . . . . . . . . . . . . . . 7 Gain distribution . . . . . . . . . . . . . . . . . . . . . . . . 8 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 I2C-bus inputs . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Address selection . . . . . . . . . . . . . . . . . . . . . . . 9 Master-slave selection . . . . . . . . . . . . . . . . . . . 9 Data transfer in write mode. . . . . . . . . . . . . . . . 9 I2C-bus table in write mode. . . . . . . . . . . . . . . . 9 I2C-bus table in write mode (default at POR) . 10 Bit description I2C-bus write mode . . . . . . . . . 10 Data transfer in read mode . . . . . . . . . . . . . . . 15 I2C-bus table in read mode . . . . . . . . . . . . . . . 15 Bit description I2C-bus read mode . . . . . . . . . 16 Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 17 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 20 Thermal characteristics. . . . . . . . . . . . . . . . . . 20 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 21 Application information. . . . . . . . . . . . . . . . . . 24 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 25 Handling information. . . . . . . . . . . . . . . . . . . . 26 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 26 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 26 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 27 Package related soldering information . . . . . . 27 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 28 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 29 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 25 Contact information . . . . . . . . . . . . . . . . . . . . 29 © Koninklijke Philips Electronics N.V. 2004 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 14 December 2004 Document number: 9397 750 13194 Published in The Netherlands