PHILIPS TDA8261TW

INTEGRATED CIRCUITS
DATA SHEET
TDA8261TW
Satellite Zero-IF QPSK/8PSK
downconverter with PLL
synthesizer
Product specification
Supersedes data of 2004 Oct 25
2004 Dec 02
Philips Semiconductors
Product specification
Satellite Zero-IF QPSK/8PSK
downconverter with PLL synthesizer
TDA8261TW
FEATURES
• Direct conversion Quadrature Phase Shift Keying
(QPSK) and 8PSK demodulation (Zero-IF)
• 950 to 2175 MHz frequency range
• High-level asymmetrical RF input
• 0 to 50 dB variable gain on RF input
Optimum signal level is guaranteed by gain controlled
amplifiers in the RF path. The 0 to 50 dB variable gain is
controlled by the signal returned from the Satellite
Demodulator and Decoder (SDD) and applied to
pin AGCIN.
• Loop-controlled 0° to 90° phase shifter
• High AGC linearity (<1 dB per bit with an 8-bit DAC),
AGC between 0 and 3 V
• External baseband filters for In-phase (I) and
Quadrature (Q) signal paths
The PLL synthesizer is built on a dual-loop concept. The
first loop controls a fully integrated L-band oscillator, using
the LC VCO as a reference which runs at a quarter of the
synthesized frequency.
• I2C-bus controlled PLL frequency synthesizer
• Low phase noise
• Operation from a 4 MHz crystal (allowing the use of an
SMD crystal)
The second loop controls the tuning voltage of the VCO
and improves the phase noise of the carrier within the loop
bandwidth. The step size is equal to the comparison
frequency. The input of the main divider of the PLL
synthesizer is connected internally to the VCO output.
• Five frequency steps from 125 kHz to 2 MHz
• Crystal frequency output to drive demodulator IC
• Compatible with 5, 3.3 and 2.5 V I2C-bus
The comparison frequency of the second loop is obtained
from an oscillator driven by an external 4 MHz crystal. The
4 MHz output available at pin XTOUT may be used to drive
the crystal inputs of the SDD, saving an additional crystal
in the application.
• Fully compatible and easy to interface with digital
satellite demodulators of the Philips Semiconductors
family
• 5 V DC supply voltage
• 32-pin high heat-dissipation package.
Both the divided and the comparison frequencies of the
second loop are compared in a fast phase detector which
drives the charge pump. The TDA8261TW includes a loop
amplifier with an internal high-voltage transistor to drive an
external 33 V tuning voltage.
APPLICATIONS
• Direct Broadcasting Satellite (DBS) QPSK
demodulation
Control data is entered via the I2C-bus. The I2C-bus
voltage can be 5, 3.3 or 2.5 V, allowing compatibility with
most of the existing microcontrollers.
• Digital Video Broadcasting (DVB) QPSK demodulation
• BS digital 8PSK demodulation.
A 5-byte frame is required to address the device and to
program the main divider ratio, the reference divider ratio,
the charge pump current and the operating mode.
GENERAL DESCRIPTION
The direct conversion QPSK demodulator is the front-end
receiver dedicated to digital TV broadcasting, satisfying
both DVB and DBS TV standards. The wide range
oscillator (from 950 to 2175 MHz) covers the American,
European and Asian satellite bands, as well as the
Satellite Master Antennae (SMA) TV US standard.
A flag is set when the loop is ‘in-lock’. This flag can be read
during read operations, as well as the Power-On Reset
(POR) flag.
The device has four selectable I2C-bus addresses. The
selection is done by applying a specific voltage to pin AS.
This feature gives the possibility to use up to four
TDA8261TW ICs in the same system.
The Zero-IF concept discards traditional IF filtering and
intermediate conversion techniques. It also simplifies the
signal path.
2004 Dec 02
2
Philips Semiconductors
Product specification
Satellite Zero-IF QPSK/8PSK
downconverter with PLL synthesizer
TDA8261TW
Performance summary
System performance, for example, in a tuner application
with the TDA8261TW placed after a low-cost discrete
LNA:
TDA8261TW performance:
• Noise figure at maximum gain = +18 dB
• Noise figure at maximum gain = 8 dB
• High linearity; IP2 = +19 dBm and IP3 = +14 dBm
• High linearity; IP2 = 15 dBm and IP3 = 5 dBm
• Low phase noise on baseband outputs: −78 dBc/Hz
(foffset = 1 and 10 kHz; fCOMP = 1 MHz)
• 0 to 50 dB variable gain with AGC control.
• 0 to 50 dB variable gain with AGC control
Specification limitation
• AGC linearity <1 dB/bit with an 8-bit DAC
Please note that this data sheet applies to versions C2 and
above only, it does not apply to version C1. For further
information, please contact your Philips Semiconductors
representative.
• Maximum I-to-Q amplitude mismatch = 1 dB
• Maximum I-to-Q phase mismatch = 3°
• Signal rates from 1 to 45 Msymbol/s (depending on the
external filter).
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VCC
supply voltage
4.75
5.0
5.25
V
ICC
supply current
−
130
−
mA
Vo(p-p)
output voltage
(peak-to-peak value)
−
750
−
mV
∆Φ
quadrature error
−
−
3
deg
fosc
oscillator frequency
950
−
2175
MHz
ϕn
phase noise on baseband
outputs
−
−78
dBc/Hz
∆Gv
dynamic range of voltage gain from pins RFA or RFB to 48
pins IBBOUT or QBBOUT
50
−
dB
VXTOUT(p-p)
crystal oscillator output
voltage on pin XTOUT
(peak-to-peak value)
500
650
−
mV
Tamb
ambient temperature
−20
−
+85
°C
−
foffset = 1 and 10 kHz;
fCOMP = 1 MHz with
appropriate loop filter and
charge pump
T2 = 1; T1 = 0; T0 = 0;
driving a load of
CL = 10 pF; RL = 1 MΩ
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
TDA8261TW
2004 Dec 02
NAME
DESCRIPTION
VERSION
HTSSOP32
plastic, thermal enhanced thin shrink small outline package;
32 leads; body width 6.1 mm; lead pitch 0.65 mm; exposed die pad
SOT549-3
3
Philips Semiconductors
Product specification
Satellite Zero-IF QPSK/8PSK
downconverter with PLL synthesizer
TDA8261TW
BLOCK DIAGRAM
QBBIN
IOUT
handbook, full pagewidth
RFGND2
BIASN1
11
BBGND1
BIASN2
6
18
VCC(BB)
13
15
QOUT
21
12
IBBIN BBGND2
14
19
20
17
RFA
RFB
RFGND1
VCC(RF)
VCOGND
VCC(VCO)
TKA
TKB
IBBOUT
9
10
7
16
QBBOUT
8
22
Q
24
23
5
AGC
CONTROL
25
VCO
AGCIN
I
integrated
oscillator
FAST PHASE/
FREQUENCY
COMPARATOR
TDA8261TW
DIVIDE-BY-4
15-BIT DIVIDER
f DIV
XT1
XT2
PLLGND
VCC(PLL)
SDA
SCL
AS
BVS
1
2
f XTAL
OSCILLATOR
REFERENCE
DIVIDER
DIGITAL PHASE
COMPARATOR
28
f COMP
CHARGE PUMP
4
33 V
AMP
27
VT
3
32
31
30
29
26
I2C-BUS
CONTROL LOGIC
AND LATCH
POWER-ON
RESET
MBL859
Fig.1 Block diagram.
2004 Dec 02
CP
4
XTOUT
Philips Semiconductors
Product specification
Satellite Zero-IF QPSK/8PSK
downconverter with PLL synthesizer
TDA8261TW
PINNING
SYMBOL
PIN
DESCRIPTION
XT1
1
4 MHz crystal oscillator input 1
XT2
2
4 MHz crystal oscillator input 2
VCC(PLL)
3
supply voltage for PLL circuit (5 V)
PLLGND
4
ground for PLL circuit
AGCIN
5
AGC input from satellite
demodulator and decoder
BIASN1
6
RF isolation input 1 (5 V)
RFGND1
7
ground 1 for RF circuit
VCC(RF)
8
supply voltage for RF stage (5 V)
RFA
9
RF signal input A
RFB
10
RF signal input B
RFGND2
11
ground 2 for RF circuit
QOUT
12
quadrature output for external
filtering
BBGND1
13
ground 1 for baseband stage
QBBIN
14
quadrature baseband input after
external filtering
VCC(BB)
15
supply voltage for baseband stage
(5 V)
QBBOUT
16
quadrature baseband output to
satellite demodulator and decoder
IBBOUT
17
in-phase baseband output to
satellite demodulator and decoder
BIASN2
18
RF isolation input 2 (5 V)
IBBIN
19
in-phase baseband input after
external filtering
BBGND2
20
ground 2 for baseband stage
IOUT
21
in-phase output for external filtering
VCOGND
22
ground for VCO circuit
TKB
23
VCO tank circuit input B
TKA
24
VCO tank circuit input A
VCC(VCO)
25
supply voltage for VCO circuit (5 V)
BVS
26
bus voltage select input
VT
27
tuning voltage output for VCO
CP
28
charge pump output
AS
29
address selection input
SCL
30
I2C-bus clock input
SDA
31
I2C-bus data input and output
XTOUT
32
4 MHz crystal oscillator output to
satellite demodulator and decoder
2004 Dec 02
handbook, halfpage
XT1
1
32 XTOUT
XT2
2
31 SDA
VCC(PLL)
3
30 SCL
PLLGND
4
29 AS
AGCIN
5
28 CP
BIASN1
6
27 VT
RFGND1
7
26 BVS
VCC(RF)
8
RFA
9
24 TKA
RFB 10
23 TKB
TDA8261TW
25 VCC(VCO)
22 VCOGND
RFGND2 11
21 IOUT
QOUT 12
20 BBGND2
BBGND1 13
QBBIN 14
19 IBBIN
VCC(BB) 15
18 BIASN2
QBBOUT 16
17 IBBOUT
MBL855
Fig.2 Pin configuration.
5
Philips Semiconductors
Product specification
Satellite Zero-IF QPSK/8PSK
downconverter with PLL synthesizer
TDA8261TW
The TDA8261TW has a gain controlled amplifier which is
controlled by the SDD.
FUNCTIONAL DESCRIPTION
The TDA8261TW contains the core of the RF analog part
of a digital satellite receiver. The signal coming from the
Low Noise Block (LNB) is coupled through a Low Noise
Amplifier (LNA) to the RF inputs. The circuitry in the
TDA8261TW performs the Zero-IF quadrature frequency
conversion and the two in-phase (IBBOUT) and
quadrature (QBBOUT) output signals can be used directly
to feed a SDD circuit.
An external VCO tank circuit is connected between
pins TKA and TKB. The main elements of the external
tank circuit are an SMD coil and a varactor diode. The
tuning voltage of 0 to 30 V covers the whole frequency
range from 237.5 to 543.75 MHz. The internal loop
controls a fully integrated VCO to cover the range
950 to 2175 MHz. The VCO provides both in-phase and
quadrature signals to drive the two mixers.
The relative phase of I and Q signals is measured on the
baseband outputs, when a sine wave unmodulated carrier
at flo + 1 MHz is present at the RF input of the
TDA8261TW (see Fig.3).
handbook, halfpage
output phase
The TDA8261TW integrates all elements necessary to
control the varactor tuned oscillator except a 4 MHz crystal
and a loop filter. It includes a fast phase detector with high
comparison frequency to get the lowest phase noise level
in the local oscillator.
The fDIV output of the15-bit programmable divider passes
through the fast phase comparator where it is compared in
both phase and frequency with the comparison frequency
(fCOMP). fCOMP is derived from the signal present at the
pins XT1 and XT2 (fXTAL) divided-down by the reference
divider. The buffered XTOUT signal can drive the crystal
frequency input of the SDD, saving a crystal in the
application.
MBL864
input
spectrum
flo
output
signal
fRF = flo +1 MHz
frequency
The output of the phase comparator drives the charge
pump and loop amplifier section. The loop amplifier
includes a high voltage transistor to handle the 30 V tuning
voltage at pin VT, this drives a variable capacitance diode
in the external circuit of the voltage controlled oscillator.
Pin CP is the output of the charge pump. The loop filter is
connected between pins CP and VT and the post-filter
section is connected between pin VT and the variable
capacitance diode.
channel I
channel Q
90°
For test and alignment purposes, it is possible to release
the tuning voltage output and apply an external voltage on
pin VT and to select the charge pump function to sink
current, source current or to be switched off.
t
Fig.3 Relative phase of I and Q signals.
2004 Dec 02
6
Philips Semiconductors
Product specification
Satellite Zero-IF QPSK/8PSK
downconverter with PLL synthesizer
TDA8261TW
PROGRAMMING
I2C-bus write mode
Programming of the TDA8261TW is performed via the
I2C-bus. The read or write selection is made with bit R/W
(address LSB). The TDA8261TW fulfils the I2C-bus fast
mode, according to the Philips I2C-bus specification.
I2C-bus write mode: bit R/W = 0; see Table 2.
After the transmission of the address (first byte), four data
bytes can be sent to fully program the TDA8261TW. The
bus transceiver has an auto-increment facility that permits
to program the TDA8261TW with a single transmission:
one address byte followed by four data bytes (PD1, PD2,
CD1 and CD2).
I2C-bus voltage
The I2C-bus lines SCL and SDA can be connected to an
I2C-bus system tied to either 2.5, 3.3 or 5.0 V, that will
allow direct connection to most of the existing
microcontrollers. The choice of the threshold voltage for
the I2C-bus lines is made with pin BVS that needs to be
connected to the supply voltage, to ground or needs an
open-circuit; see Table 1.
Table 1
I2C-bus voltage selection
PIN BVS
I2C-BUS VOLTAGE
GND
2.5 V
Open-circuit
3.3 V
VCC
Table 2
The TDA8261TW can be partly programmed provided that
the first data byte following the address is PD1 or CD1.
The first bit of the first data byte transmitted indicates
whether PD1 (first bit = 0) or CD1 (first bit = 1) will follow.
Until an I2C-bus STOP condition is sent by the controller,
additional data bytes can be entered without the need to
re-address the device. Each byte is loaded after the
corresponding 8th clock pulse. Programmable divider data
(contents of PD1 and PD2) becomes valid only after the
8th clock pulse of PD2, or after a STOP condition if only
PD1 needs to be programmed.
5V
I2C-bus write data format
BYTE
MSB(1)
BITS(2)
LSB
ACK(3)
Programmable address
1
1
0
0
0
MA1
MA0
0
A
Programmable Divider 1 (PD1)
0
N14
N13
N12
N11
N10
N9
N8
A
Programmable Divider 2 (PD2)
N7
N6
N5
N4
N3
N2
N1
N0
A
Control Data 1 (CD1)
1
T2
T1
T0
R2
R1
R0
X
A
Control Data 2 (CD2)
C1
C0
X
X
X
X
X
X
A
Notes
1. MSB is transmitted first.
2. X = undefined.
3. Acknowledge bit (A).
2004 Dec 02
7
Philips Semiconductors
Product specification
Satellite Zero-IF QPSK/8PSK
downconverter with PLL synthesizer
TDA8261TW
PROGRAMMABLE ADDRESS
REFERENCE DIVIDER
The programmable address bits MA1 and MA0 offer the
possibility of having up to four TDA8260TW devices in the
same system. The relationship between the voltage
applied on pin AS and the value of bits MA1 and MA0 is
given in Table 3.
Five reference divider ratios allow to adjust the
comparison frequency to different values, depending on
the compromise which has to be found between step size
and phase noise. The reference divider ratios and the
corresponding comparison frequencies are programmed
using bits R2, R1 and R0, as described in Table 5.
Table 3
I2C-bus address selection
VAS
MA1
MA0
0 to 0.1VCC
0
0
open-circuit
0
1
0.4VCC to 0.6VCC
1
0
0.9VCC to VCC
1
1
Table 5
PROGRAMMABLE MAIN DIVIDER RATIO
Program bytes PD1 and PD2 contain the fifteen bits
N14 to N0 that set the main divider ratio. The ratio
N = N14 × 214 + N13 × 213 +...+ N1 × 2 + N0.
Reference divider ratio
R2
R1
R0
DIVIDER RATIO
COMPARISON
FREQUENCY
0
0
0
2
2 MHz
0
0
1
4
1 MHz
0
1
0
8
500 kHz
0
1
1
not allowed
not allowed
1
0
0
not allowed
not allowed
1
0
1
16
250 kHz
1
1
0
not allowed
not allowed
1
1
1
32
125 kHz
OPERATING AND TEST MODES
CHARGE PUMP CURRENT
The mode of operation is set using bits T2, T1 and T0 in
control byte CD1; see Table 4.
Table 4
Four values of charge pump current can be chosen using
bits C1 and C0, according to Table 6.
Mode selection
T2
T1
T0
TEST MODE
0
0
0
0
0
1
POR state = CP sink(1) fXTAL
normal operation
× fDIV
Table 6
XTOUT
off
× fDIV
Typical charge pump current
C1
C0
ICP (ABSOLUTE VALUE)
0
0
420 µA
0
1
900 µA
0
1
0
1/
0
1
1
CP sink
fXTAL
1
0
1320 µA
1
0
0
normal operation
fXTAL
1
1
2320 µA
1
0
1
2 × fref
2 × fref
1
1
0
CP off
fXTAL
1
1
1
CP source
fXTAL
2
1/
2
Note
1. Status at power-on: the tuning voltage output is
released and pin VT is in the high-impedance mode.
2004 Dec 02
8
Philips Semiconductors
Product specification
Satellite Zero-IF QPSK/8PSK
downconverter with PLL synthesizer
TDA8261TW
then release the data line to allow the microcontroller to
generate a STOP condition.
I2C-bus read mode
If bit R/W = 1 the data can be read from the TDA8261TW
(see Table 7). After recognition of its slave address, the
TDA8261TW generates an acknowledge pulse and
transfers the status byte onto the SDA line (MSB first).
Data is valid on the SDA line when the SCL clock signal is
HIGH.
The POR flag is set to logic 1 at power-on and when
VCC < 2.7 V. It is reset to logic 0 when an end-of-data
condition is detected by the TDA8261TW (end of a read
sequence).
The in-lock flag FL indicates that the loop is phase-locked
when set to logic 1.
A second data byte can be read from the TDA8261TW if
the microcontroller generates an acknowledge on the SDA
line. End of transmission will occur if no acknowledge is
received from the microcontroller. The TDA8261TW will
Table 7
When a read sequence is started, all eight bits of the status
byte must be read.
I2C-bus read data format
BYTE
Address
Status byte
BITS(1)
MSB
LSB
ACK(2)
1
1
0
0
0
MA1
MA0
1
A
POR
FL(3)
X
X
X
X
X
X
−
Notes
1. X can be 1 or 0 and needs to be masked in the microcontrollers’ software; MSB is transmitted first.
2. Acknowledge bit (A).
3. FL is valid only in normal mode.
POWER-ON RESET
At power-on (bit POR = 1) or when the supply voltage drops below 2.7 V, internal registers are set according to Table 8.
Table 8
Status at POR
BYTE
BITS(1)
MSB
LSB
Programmable divider 1 (PD1)
0
N14 = X
N13 = X
N12 = X
N11 = X
N10 = X
N9 = X
N8 = X
Programmable divider 2 (PD2)
N7 = X
N6 = X
N5 = X
N4 = X
N3 = X
N12 = X
N1 = X
N0 = X
Control data 1 (CD1)
1
T2 = 0
T1 = 0
T0 = 1
R2 = X
R1 = X
R0 = X
X
Control data 1 (CD2)
C1 = X
C0 = X
X
X
X
X
X
X
Note
1. X = not set.
2004 Dec 02
9
Philips Semiconductors
Product specification
Satellite Zero-IF QPSK/8PSK
downconverter with PLL synthesizer
TDA8261TW
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); note 1.
SYMBOL
PARAMETER
VCC
supply voltage
Vi
input voltage
Vo
output voltage
CONDITIONS
MIN.
MAX.
UNIT
−0.3
+6.0
V
pin SDA
−0.3
+6.0
V
pin SCL
−0.3
+6.0
V
all other pins
−0.3
VCC + 0.3
V
pin SDA
−0.3
+6.0
V
pin VT
−0.3
+35
V
−0.3
VCC + 0.3
V
Tamb
ambient temperature
−20
+85
°C
Tstg
storage temperature
−40
+150
°C
Tj
junction temperature
−
150
°C
tsc
short-circuit time
−
10
s
all other pins
each pin short-circuited to
VCC or GND
Note
1. Maximum ratings cannot be exceeded, not even momentarily without causing irreversible damages to the
TDA8261TW. Maximum ratings cannot be accumulated.
THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
PARAMETER
CONDITIONS
thermal resistance from junction to ambient
in free air
VALUE
UNIT
41.4
K/W
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be completely safe, it
is desirable to take normal precautions appropriate to handle integrated circuits. Every pin withstands 2000 V in the ESD
test in accordance with “JEDEC Specification EIA/JESD22-A114A”, HBM model (category 1c), except for pin 1 (XT1)
which withstands 500 V, pin 2 (XT2) which withstands 1000 V and pin 8 (VCC(RF)) which withstands 1500 V. Identically,
every pin withstands 200 V in the ESD test in accordance with “JEDEC Specification EIA/JESD22-A115A”, MM model
(category A).
2004 Dec 02
10
Philips Semiconductors
Product specification
Satellite Zero-IF QPSK/8PSK
downconverter with PLL synthesizer
TDA8261TW
CHARACTERISTICS
Tamb = 25 °C; VCC = 5 V; unless otherwise specified; RL = 1 kΩ on base band output IBBOUT and QBBOUT;
Vo(p-p) = 750 mV on IBBOUT and QBBOUT.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VCC
supply voltage
4.75
5.00
5.25
V
ICC
supply current
−
130
−
mA
VPOR
voltage limit where POR active
−
2.7
−
V
−
−75
−
dBm
Performances from pins RFA or RFB to pins IBBOUT or QBBOUT
LOleak
LO leakage through pins RFA
and RFB
∆Gv
dynamic voltage gain range
VAGC = 0 to 3 V
48
50
−
dB
Gv(max)
maximum voltage gain
VAGC = 3 V;
see Figs 4 and 5
55
57
−
dB
Vo(p-p)
output voltage (peak-to-peak)
recommended value
−
750
−
mV
IP2i
2nd-order interception point
at RF input; VAGC = 0 V
−
19
−
dBm
IP3i
3rd-order interception point
at RF input; VAGC = 0 V
−
14
−
dBm
F
noise figure
at maximum gain;
VAGC = 3 V; see Fig.6
−
18
−
dB
Zo
output impedance on pin IOUT
and QOUT
−
35
−
Ω
Zi
input impedance on pin IBBIN
and QBBIN
−
1.0
−
kΩ
Gv(I-Q)
voltage gain mismatch between in 22.5 MHz band with
−
I and Q
bypass capacity 100 nF
between IOUT and IBBIN,
QOUT and QBBIN
−
1
dB
∆Φ
absolute quadrature error
−
0
3
deg
VAGC = 1.5 V;
Vo = 750 mV (peak to
peak value); measured in
baseband
Pulling sensitivity
3/4LO
sensitivity to pulling on the third see Table 9 and Fig.8
harmonic of the external VCO
−
−40
−35
dBc
5/4LO
sensitivity to pulling on the fifth
harmonic of the external VCO
−
−40
−35
dBc
950
−
2175
MHz
see Table 9 and Fig.8
VCO and synthesizer
fosc
oscillator frequency
ϕn(osc)
oscillator phase noise in the
satellite band
foffset = 100 kHz; out of
PLL loop bandwidth
−
−100
−94
dBc/Hz
ϕn
phase noise on baseband
outputs
foffset = 1 and 10 kHz;
fCOMP = 1 MHz; see Fig.7
−
−
−78
dBc/Hz
MDR
main divider ratio
64
−
32767
2004 Dec 02
11
Philips Semiconductors
Product specification
Satellite Zero-IF QPSK/8PSK
downconverter with PLL synthesizer
SYMBOL
PARAMETER
Zosc
crystal oscillator negative
impedance (absolute value)
TDA8261TW
CONDITIONS
MIN.
TYP.
MAX.
UNIT
1.0
1.5
−
kΩ
fxtal
crystal frequency
−
4
−
MHz
Zxtal
crystal series resistance
recommended value
−
−
200
Ω
VXTOUT(p-p)
crystal oscillator output voltage
on pin XTOUT (peak-to-peak
value)
T2 = 1; T1 = 0; T0 = 0;
driving a load of
CL = 10 pF; RL = 1 MΩ
500
650
−
mV
T2 = 1; T1 = 1; T0 = 0
−10
0
+10
nA
Charge pump output; pin CP
IL
leakage current
Tuning voltage output; pin VT
IL(off)
leakage current when switch off T2 = 0; T1 = 0; T0 = 1;
Vtune = 33 V
−
−
10
µA
Vo(VT)
output voltage when the loop is
locked
normal mode;
Vtune = 33 V
0.2
−
32.7
V
Bus voltage select input; pin BVS
ILIH
HIGH-level leakage current
VBVS = VCC
−
−
100
µA
ILIL
LOW-level leakage current
VBVS = 0 V
−100
−
−
µA
VBVS = open
−
−
0.2VCC
V
VBVS = 0 V
−
−
0.15VCC V
VBVS = 5 V
−
−
0.3VCC
V
VBVS = open
0.46VCC −
−
V
VBVS = 0 V
0.35VCC −
−
V
VBVS = 5 V
0.6VCC
−
−
V
VIH = 5.5 V; VCC = 5.5 V
−
−
10
µA
VIH = 5.5 V; VCC = 0 V
−
−
10
µA
VIL = 0 V; VCC = 5.5 V
−10
−
−
µA
−
−
400
kHz
SCL and SDA inputs
VIL
VIH
LOW-level input voltage
HIGH-level input voltage
ILIH
HIGH-level leakage current
ILIL
LOW-level leakage current
fSCL
SCL input frequency
SDA output
output voltage during
acknowledge
Isink = 3 mA
−
−
0.4
V
IIH
HIGH-level input current
VAS = VCC
−
−
10
µA
IIL
LOW-level input current
VAS = 0 V
−10
−
−
µA
VACK
AS input
2004 Dec 02
12
Philips Semiconductors
Product specification
Satellite Zero-IF QPSK/8PSK
downconverter with PLL synthesizer
TDA8261TW
MBL863
70
G
(dB)
G
(dB)
60
40
50
20
40
950
Fig.4
MBL861
60
handbook, halfpage
handbook, halfpage
0
1150
1350
1550
1750
1950
f (MHz)
0
2150
Overall gain as function of frequency
response.
Fig.5
MGU798
1
2
3
Overall gain as function of AGC input
voltage.
MGU796
−70
20
handbook, halfpage
VAGC (V)
handbook, halfpage
ϕn
(dBc/Hz)
F
(dB)
18
−80
(1)
16
−90
(2)
14
−100
12
10
950
Fig.6
1150
1350
1550
1750
−110
950
1950
2150
f (MHz)
Noise figure as function of frequency
response.
2004 Dec 02
Fig.7
13
1150
1350
1550
1750
1950
f (MHz)
2150
Phase noise on I and Q band outputs as
function of frequency response.
Philips Semiconductors
Product specification
Satellite Zero-IF QPSK/8PSK
downconverter with PLL synthesizer
TDA8261TW
RF SIGNAL wanted signal
GENERATOR
handbook, full pagewidth
ANZAC
TDA8261TW
RF SIGNAL unwanted signal
GENERATOR
SPECTRUM
ANALYSER
MBL860
Fig.8 Measurement method for pulling sensitivity.
Table 9
Test signal conditions for pulling measurements
SIGNAL
3/4LO test
5/4LO test
FREQUENCY
LEVEL
REMARK
wanted
fw = 2161 MHz
−10 dBm
unwanted
fuw = 1613 MHz
−2 dBm
fuw = flo × 3/4 + 500 kHz
local oscillator
flo = 2150 MHz
−
−
wanted
fw = 1761 MHz
−10 dBm
fw = flo + 11 MHz
unwanted
fuw = 2188 MHz
−2 dBm
fuw = flo × 5/4 + 500 kHz
local oscillator
flo = 1750 MHz
−
−
fw = flo + 11 MHz
The level of the wanted and unwanted signal mentioned in the table are measured at the outputs of the RF signal
generators. The sensitivity to pulling is measured in baseband by the difference expressed in dB (∆) between the level
of the wanted signal and the spurious generated by pulling. The ANZAC reference is HH128.
handbook, halfpage
∆Vsignal
11.5
spurious
signal
11
wanted
signal
f (MHz)
MGU794
Fig.9 Base band spectrum.
2004 Dec 02
14
Philips Semiconductors
Product specification
Satellite Zero-IF QPSK/8PSK
downconverter with PLL synthesizer
TDA8261TW
APPLICATION INFORMATION
handbook, full pagewidth 4MHz
C2
39 pF
X1
C38
39 pF
XT1
XT2
VCC(PLL)
+5 V
PLLGND
AGCIN
VAGC
BIASN1
+5 V
RFGND1
VCC(RF)
+5 V
C3
RFIN
2.2 pF
C10
2.2 pF
RFA
RFB
RFGND2
1
32
2
31
3
30
4
29
5
28
6
27
7
26
8
25
TDA8261TW
9
24
10
23
11
22
12
21
13
20
14
19
15
18
XTOUT
4 MHz
SDA
SCL
AS
C2
C1
330 pF
R10
12 nF
R1
22 kΩ
CP
VT
4.7 kΩ
BVS
VCC(VCO)
C21
R3
TKA
R2
1.5 kΩ
+5 V
33 Ω
TKB
VCOGND
R5
4.7 kΩ
82 pF
L1
18 nH
C22
D1
BB178
82 pF
QOUT
BBGND1
QBBIN
+5 V
VCC(BB)
QBBOUT
16
17
R4
4.7 kΩ
IOUT
BBGND2
IBBIN
BIASN2
+5 V
IBBOUT
HEATSINK
MBL858
Fig.10 Typical application.
handbook, halfpage
R0
R2
L1
L2
35 Ω
56 Ω
470 nH
680 nH
C0
33 pF
C1
82 pF
C3
68 pF
Zout
LPF
C2
100 nF
DC
coupling
R1
1 kΩ
Zin
MBL856
Fig.11 Typical 36 MHz low-pass filter.
2004 Dec 02
15
C3
330 pF
+ 30 V
Philips Semiconductors
Product specification
Satellite Zero-IF QPSK/8PSK
downconverter with PLL synthesizer
TDA8261TW
andbook, full pagewidth
AGCIN
12
14
5
32
PWM
4 MHz clock
1
4 MHz
INPUT
MATCHING
LNA
RFA
9
2
TDA8261TW
17
16
21
TDA10086
IBBOUT
I
QBBOUT
Q
MPEG2 TS
19
I2C-bus
I2C-bus
MBL857
Fig.12 Tuner configuration with a TDA8261TW.
Application design
notes for TDA8261TW together with associated channel
decoders. Please contact your local Philips
Semiconductors sales office for more information.
The performance of the application using the TDA8261TW
strongly depends on the application design itself.
Furthermore the printed-circuit board design and the
soldering conditions should take into account the exposed
die pad underneath the device, as this requires an
optimum electrical ground path for electrical performance,
together with the capability to dissipate into the application
the heat created in the device. Philips Semiconductors can
provide support through reference designs and application
2004 Dec 02
Wave soldering is not suitable for the TDA8261TW
package. This is because the heatsink needs to be
soldered to the printed-circuit board underneath the
package but with wave soldering the solder cannot
penetrate between the printed-circuit board and the
heatsink.
16
Philips Semiconductors
Product specification
Satellite Zero-IF QPSK/8PSK
downconverter with PLL synthesizer
TDA8261TW
PACKAGE OUTLINE
HTSSOP32: plastic thermal enhanced thin shrink small outline package; 32 leads;
body width 6.1 mm; lead pitch 0.65 mm; exposed die pad
SOT549-3
E
D
A
X
c
y
HE
exposed die pad side
v M A
Dh
Z
32
17
A2
Eh
(A3)
A
A1
θ
Lp
pin 1 index
L
detail X
16
1
w M
bp
e
2.5
0
5 mm
scale
DIMENSIONS (mm are the original dimensions).
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
Dh
E (2)
Eh
e
HE
L
Lp
v
w
y
Z
θ
mm
1.1
0.15
0.05
0.95
0.85
0.25
0.30
0.19
0.20
0.09
11.1
10.9
3.65
3.45
6.2
6.0
2.85
2.65
0.65
8.3
7.9
1
0.75
0.50
0.2
0.1
0.1
0.78
0.48
8
o
0
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
ISSUE DATE
04-01-22
SOT549-3
2004 Dec 02
EUROPEAN
PROJECTION
17
o
Philips Semiconductors
Product specification
Satellite Zero-IF QPSK/8PSK
downconverter with PLL synthesizer
TDA8261TW
To overcome these problems the double-wave soldering
method was specifically developed.
SOLDERING
Introduction to soldering surface mount packages
If wave soldering is used the following conditions must be
observed for optimal results:
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Driven by legislation and environmental forces the
worldwide use of lead-free solder pastes is increasing.
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 seconds and 200 seconds
depending on heating method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 °C to 270 °C depending on solder paste material. The
top-surface temperature of the packages should
preferably be kept:
Typical dwell time of the leads in the wave ranges from
3 seconds to 4 seconds at 250 °C or 265 °C, depending
on solder material applied, SnPb or Pb-free respectively.
• below 225 °C (SnPb process) or below 245 °C (Pb-free
process)
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
– for all BGA, HTSSON..T and SSOP..T packages
– for packages with a thickness ≥ 2.5 mm
Manual soldering
– for packages with a thickness < 2.5 mm and a
volume ≥ 350 mm3 so called thick/large packages.
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
• below 240 °C (SnPb process) or below 260 °C (Pb-free
process) for packages with a thickness < 2.5 mm and a
volume < 350 mm3 so called small/thin packages.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 seconds to 5 seconds
between 270 °C and 320 °C.
Moisture sensitivity precautions, as indicated on packing,
must be respected at all times.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
2004 Dec 02
18
Philips Semiconductors
Product specification
Satellite Zero-IF QPSK/8PSK
downconverter with PLL synthesizer
TDA8261TW
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE(1)
WAVE
REFLOW(2)
BGA, HTSSON..T(3), LBGA, LFBGA, SQFP, SSOP..T(3), TFBGA,
VFBGA, XSON
not suitable
suitable
DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON,
HTQFP, HTSSOP, HVQFN, HVSON, SMS
not suitable(4)
suitable
PLCC(5), SO, SOJ
suitable
suitable
not
recommended(5)(6)
suitable
SSOP, TSSOP, VSO, VSSOP
not
recommended(7)
suitable
CWQCCN..L(8), PMFP(9), WQCCN..L(8)
not suitable
LQFP, QFP, TQFP
not suitable
Notes
1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account
be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature
exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package body peak temperature
must be kept as low as possible.
4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
5. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
6. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
8. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted
on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar
soldering process. The appropriate soldering profile can be provided on request.
9. Hot bar soldering or manual soldering is suitable for PMFP packages.
2004 Dec 02
19
Philips Semiconductors
Product specification
Satellite Zero-IF QPSK/8PSK
downconverter with PLL synthesizer
TDA8261TW
DATA SHEET STATUS
LEVEL
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
Development
DEFINITION
I
Objective data
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Production
This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
DEFINITIONS
DISCLAIMERS
Short-form specification  The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Life support applications  These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition  Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes  Philips Semiconductors
reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2004 Dec 02
20
Philips Semiconductors
Product specification
Satellite Zero-IF QPSK/8PSK
downconverter with PLL synthesizer
TDA8261TW
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
2004 Dec 02
21
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: [email protected]
SCA76
© Koninklijke Philips Electronics N.V. 2004
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R25/04/pp22
Date of release: 2004
Dec 02
Document order number:
9397 750 14376