INTEGRATED CIRCUITS DATA SHEET TDA8060TS Satellite ZERO-IF QPSK down-converter Product specification Supersedes data of 1998 May 29 File under Integrated Circuits, IC02 1999 Aug 30 Philips Semiconductors Product specification Satellite ZERO-IF QPSK down-converter FEATURES TDA8060TS wide range oscillator covers American, European and Asian satellite bands as well as the future SMA-TV US standard. • Direct conversion QPSK demodulation (Zero IF) • 920 to 2200 MHz range Accurate QPSK demodulation is ensured by the on-chip loop-controlled phase shifter. The Zero-IF concept discards traditional IF filtering and intermediate conversion techniques. It also simplifies the signal path. • On-chip loop-controlled 0 or 90° phase shifter • Variable gain on RF input • 60 MHz, at −1 dB, bandwidth for baseband I and Q amplifiers The baseband I and Q signal bandwidth only depends, to a certain extent, on the external filter used in the application. • Local oscillator output to PLL satellite or terrestrial • 5 V supply voltage. Optimum signal level is guaranteed by a gain-controlled amplifier at the RF input. The GAIN pin sets the gain for both I and Q channels, providing a 30 dB range. APPLICATIONS • Direct Broadcasting Satellite (DBS) QPSK demodulation The chip also offers a selectable internal LO prescaler (divide-by-2) and buffer that has been designed to be compatible with the input of a terrestrial or satellite frequency synthesizer. • Digital Video Broadcasting (DVB) QPSK deSupersedes data of 1998 May 29 modulation. GENERAL DESCRIPTION The direct conversion QPSK demodulator is the front-end receiver dedicated to digital TV broadcasting, satisfying both DVB and DBS TV standards. The 920 to 2200 MHz QUICK REFERENCE DATA SYMBOL PARAMETER MIN. TYP. MAX. UNIT VCC supply voltage 4.75 5.00 5.25 V ∆Φ quadrature error − − 3 deg fosc oscillator frequency 920 − 2200 MHz Vo(p-p) output voltage (peak-to-peak value) − 0.75 − V Tamb operating ambient temperature −20 − +85 °C ORDERING INFORMATION TYPE NUMBER TDA8060TS 1999 Aug 30 PACKAGE NAME DESCRIPTION VERSION SSOP24 plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1 2 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... VCC(RF) RFGND VCC(LO1) LOGND1 VCC(LO2) LOGND2 IOUT IBBIN 6 16 2 24 9 15 19 CONVERSION STAGE × 22 I CONVERTER SYM ASYM AMP 23 IBBOUT 14 QBBOUT 1 VCC(BB1) 12 VCC(BB2) 3 BBGND1 10 BBGND2 100 MHz RFA 8 RFB 7 BASEBAND STAGE LNA Q CONVERTER × COMGAIN 4 3 QUADRATURE GENERATOR SYM AMP ASYM 100 MHz STABILIZED LO PLL AND AMPLIFIER TDA8060TS PEN 5 DIVIDE-BY-2 OSCILLATOR 13 20 21 18 17 11 LOOUT LOOUTC TKA TKB QOUT QBBIN Philips Semiconductors LOW-PASS FILTER Satellite ZERO-IF QPSK down-converter BLOCK DIAGRAM 1999 Aug 30 handbook, full pagewidth MGM318 LOW-PASS FILTER Product specification TDA8060TS Fig.1 Block diagram. Philips Semiconductors Product specification Satellite ZERO-IF QPSK down-converter TDA8060TS PINNING SYMBOL PIN DESCRIPTION VCC(BB1) 1 supply voltage 1 for baseband circuit (+5 V) IOUT 2 ‘I’ output from demodulator BBGND1 3 ground 1 for baseband circuit COMGAIN 4 RF amplifier gain control input PEN 5 prescaler enable VCC(RF) 6 supply voltage for RF circuit (+5 V) RFB 7 RF signal input B RFA 8 RF signal input A RFGND 9 ground for RF circuit BBGND2 10 ground 2 for baseband circuit QOUT 11 ‘Q’ output from demodulator VCC(BB2) 12 supply voltage 2 for baseband circuit (+5 V) QBBIN 13 ‘Q’ baseband amplifier input QBBOUT 14 ‘Q’ baseband amplifier output LOGND1 15 ground 1 for local oscillator circuit VCC(LO1) 16 supply voltage 1 for local oscillator circuit (+5 V) TKB 17 tank circuit input B TKA 18 tank circuit input A VCC(LO2) 19 supply voltage 2 for local oscillator circuit (+5 V) LOOUT 20 LOOUTC 21 local oscillator output to synthesizer divided or not according to PEN voltage LOGND2 22 ground 2 for local oscillator circuit IBBOUT 23 ‘I’ baseband amplifier output IBBIN 24 ‘I’ baseband amplifier input 1999 Aug 30 handbook, halfpage VCC(BB1) 1 24 IBBIN 23 IBBOUT IOUT 2 BBGND1 3 22 LOGND2 COMGAIN 4 21 LOOUTC 20 LOOUT PEN 5 VCC(RF) 6 19 VCC(LO2) TDA8060TS RFB 7 18 TKA RFA 8 17 TKB 16 VCC(LO1) RFGND 9 BBGND2 10 15 LOGND1 QOUT 11 14 QBBOUT VCC(BB2) 12 13 QBBIN MGM317 Fig.2 Pin configuration. 4 Philips Semiconductors Product specification Satellite ZERO-IF QPSK down-converter TDA8060TS LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER MIN. MAX. UNIT VCC supply voltage −0.3 +6.0 V Vi(max) maximum input voltage on all pins −0.3 VCC V tsc(max) maximum short-circuit time − 10 s Tamb operating ambient temperature −20 +85 °C Tstg storage temperature −55 +150 °C Tj junction temperature − 150 °C HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER CONDITIONS thermal resistance from junction to ambient VALUE UNIT 120 K/W MAX. UNIT in free air DC CHARACTERISTICS Tamb = 25 °C; VCC = 5 V; unless otherwise specified. SYMBOL PARAMETER VCC supply voltage ICC supply current CONDITIONS MIN. TYP. 4.75 5.00 5.25 V PEN = 5 V 63 73 83 mA PEN = 0 V 60 70 80 mA Conversion stage VI(RFA) DC input voltage on pin RFA − 0.9 − V VI(RFB) DC input voltage on pin RFB − 0.9 − V VO(IOUT) DC output voltage on pin IOUT − 2.0 − V VO(QOUT) DC output voltage on pin QOUT − 2.0 − V Quadrature generator VO(LOOUT) DC output voltage on pin LOOUT − 4.7 − V VO(LOOUTC) DC output voltage on pin LOOUTC − 4.7 − V Baseband stage VI(IBBIN) DC input voltage on pin IBBIN − 2.5 − V VI(QBBIN) DC input voltage on pin QBBIN − 2.5 − V VO(IBBOUT) DC output voltage on pin IBBOUT − 2.5 − V VO(QBBOUT) DC output voltage on pin QBBOUT − 2.5 − V 1999 Aug 30 5 Philips Semiconductors Product specification Satellite ZERO-IF QPSK down-converter TDA8060TS AC CHARACTERISTICS Tamb = 25 °C; VCC = 5 V; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT 920 − 2200 MHz Quadrature generator fosc oscillator frequency range ΦNosc oscillator phase noise at 10 kHz offset; note 1 − −80 −75 dBc/Hz ∆Φ absolute quadrature error note 2 − 0 3 deg fLOOUT output frequency VPEN = 0 V − fosc − MHz VPEN = VCC − 1⁄ − MHz RL = 100 Ω differential −30 −22 − dBm − 60 − Ω Vo(diff)(LOOUT) differential output voltage at pin LOOUT Zo(diff)(LOOUT) differential output impedance at pin LOOUT 2fosc Conversion stage Ri(diff) series real part of differential input impedance at pins RFA and RFB note 3 − 34 − Ω Li(diff) series inductance of differential input impedance at pins RFA and RFB note 3 − 5 − nH Pi(max) maximum input power per channel − −22 − dBm Pi(min) minimum input power per channel − −52 − dBm ∆Gv/∆V(slope) AGC slope − 30 40 dB/V ∆Gv(I-Q) voltage gain mismatch between I and Q − − 1 dB ∆td(g)(RF-IOUT) group delay variation per channel (40 MHz) from RF input to pin IOUT − 0.5 2 ns ∆td(g)(RF-QOUT) group delay variation per channel (40 MHz) from RF input to pin QOUT − 0.5 2 ns td(g)(I-Q)(40) group delay mismatch per channel (40 MHz) between I and Q − 0 0.5 ns B(−1dB)(RF-IOUT) channel −1 dB bandwidth from RF input to pin IOUT 40 50 − MHz B(−1dB)(RF-QOUT) channel −1 dB bandwidth from RF input to pin QOUT 40 50 − MHz B(−3dB)(RF-IOUT) channel −3 dB bandwidth from RF input to pin IOUT 70 80 − MHz B(−3dB)(RF-QOUT) channel −3 dB bandwidth from RF input to pin QOUT 70 80 − MHz Zo(IOUT) output impedance at pin IOUT − 65 − Ω Zo(QOUT) output impedance at pin QOUT − 65 − Ω Vo(IOUT) nominal output voltage level at pin IOUT per channel − 25 − dBmV Vo(QOUT) nominal output voltage level at pin QOUT per channel − 25 − dBmV RoL(IOUT) resistive load at pin IOUT 400 − − Ω RoL(QOUT) resistive load at pin QOUT 400 − − Ω 1999 Aug 30 at Gv(RF-IOUT)(min) 6 Philips Semiconductors Product specification Satellite ZERO-IF QPSK down-converter SYMBOL PARAMETER TDA8060TS CONDITIONS MIN. TYP. MAX. UNIT SYMMETRICAL RF INPUT (Fig.3) Gv(RF-IOUT)(min) minimum voltage gain from RF input to pin IOUT VAGC = 0.1 x VCC; note 4 − − −1 dB Gv(RF-IOUT)(max) maximum voltage gain from RF input to pin IOUT VAGC = 0.9 x VCC; note 4 28 29 − dB Gv(RF-QOUT)(min) minimum voltage gain from RF input to pin QOUT VAGC = 0.1 x VCC; note 4 − − −1 dB Gv(RF-QOUT)(max) maximum voltage gain from RF input to pin QOUT VAGC = 0.9 x VCC; note 4 28 29 − dB IP3i(I) I 3rd-order interception point at RF input 1 4 − dBm IP2i(I) I 2nd-order interception point at RF input 12 15 − dBm IP3i(Q) Q 3rd-order interception point at RF input 1 4 − dBm IP2i(Q) Q 2nd-order interception point at RF input 12 15 − dBm Fi noise figure at maximum gain VAGC = 0.9 x VCC; Zsource = 50 Ω − 12 15 dB ASYMMETRICAL RF INPUT (Fig.4) Gv(RF-IOUT)(min) minimum voltage gain from RF input to pin IOUT VAGC = 0.1 x VCC; note 5 − − −1 dB Gv(RF-IOUT)(max) maximum voltage gain from RF input to pin IOUT VAGC = 0.9 x VCC; note 5 − 29 − dB Gv(RF-QOUT)(min) minimum voltage gain from RF input to pin QOUT VAGC = 0.1 x VCC; note 5 − − −1 dB Gv(RF-QOUT)(max) maximum voltage gain from RF input to pin QOUT VAGC = 0.9 x VCC; note 5 − 29 − dB IP3i(I) I 3rd-order interception point at RF input − 3 − dBm IP2i(I) I 2nd-order interception point at RF input − 15 − dBm IP3i(Q) Q 3rd-order interception point at RF input − 3 − dBm IP2i(Q) Q 2nd-order interception point at RF input Fi noise figure at maximum gain VAGC = 0.9 x VCC; Zsource = 50 Ω − 15 − dBm − 13 − dB − 10 − kΩ − 25 − dBmV Baseband stages Zi input impedance Vi nominal input voltage level NTXi number of channels at input − 2 − − Gv(IBBIN-IBBOUT) voltage gain from pin IBBIN to pin IBBOUT 19 20 22 dB Gv(QBBIN-QBBOUT) voltage gain from pin QBBIN to pin QBBOUT 19 20 22 dB Gv(I-Q) voltage gain mismatch between I and Q − 0 1 dB per channel IP3i 3rd-order interception point at IQBBIN input 54 59 − dBmV IP2i 2nd-order interception point at IQBBIN input 72 79 − dBmV ∆td(g)(40) group delay variation in 40 MHz bandwidth − 0.5 2 ns td(g)(I-Q)(40) group delay mismatch in 40 MHz band between I and Q − 0.5 2 ns 1999 Aug 30 7 Philips Semiconductors Product specification Satellite ZERO-IF QPSK down-converter SYMBOL TDA8060TS PARAMETER CONDITIONS MIN. TYP. MAX. UNIT 40 65 − MHz B(−1dB) channel −1 dB bandwidth B(−3dB) channel −3 dB bandwidth 70 100 − MHz Zo output impedance − 50 − Ω Vo(p-p) nominal output voltage level − 750 − mV Ro(L) resistive load at output 400 − − Ω 2 ns Overall with a 100 nF capacitor instead of LP1 and LP2 td(g)(I-Q)(40) group delay mismatch in 40 MHz band between I and Q − 0.5 td(g)(I-Q)(R40) group delay ripple in 40 MHz band for I or Q − 0.5 1 ns Gv(I-Q)(40) voltage gain mismatch in 40 MHz band between I and Q − − 1 dB GR(I-Q)(40) voltage gain ripple in 40 MHz band for I or Q − − 1 dB SYMMETRICAL RF INPUT Gv(RF-IBBOUT)(min) minimum voltage gain from RF input to pin IBBOUT VAGC = 0.1 x VCC; − − 19 dB Gv(RF-IBBOUT)(max) maximum voltage gain from RF input to pin IBBOUT VAGC = 0.9 x VCC; 48 49 − dB Gv(RF-QBBOUT)(min) minimum voltage gain from RF input to pin QBBOUT VAGC = 0.1 x VCC; − − 19 dB Gv(RF-QBBOUT)(max) maximum voltage gain from RF input to pin QBBOUT VAGC = 0.9 x VCC; 48 49 − dB VAGC = 0.9 x VCC; Zsource = 50 Ω − 13 16 dB Fi noise figure at maximum gain ASYMMETRICAL RF INPUT Gv(RF-IBBOUT)(min) minimum voltage gain from RF input to pin IBBOUT VAGC = 0.1 x VCC − − 19 dB Gv(RF-IBBOUT)(max) maximum voltage gain from RF input to pin IBBOUT VAGC = 0.9 x VCC − 49 − dB Gv(RF-QBBOUT)(min) minimum voltage gain from RF input to pin QBBOUT VAGC = 0.1 x VCC − − 19 dB Gv(RF-QBBOUT)(max) maximum voltage gain from RF input to pin QBBOUT VAGC = 0.9 x VCC − 49 − dB Fi VAGC = 0.9 x VCC; Zsource = 50 Ω − 14 − dB noise figure at maximum gain Notes 1. Measured in baseband (at pin IOUT or pin QOUT) on a carrier at 2 MHz and 25 dBmV. 2. Quadrature error with respect to 90°. 3. The differential input impedance of the IC is 34 Ω in series with the IC pins which give an inductance of 5 nH. For optimum performance, this inductance should be cancelled by a matching network. Coupling capacitors of 1 pF give an acceptable result. 4. Gain = Vo(dB) − Vi(dB) (see Fig.3). Gain for symmetrical RF input 5. Gain = Vo(dB) − Vi(dB) (see Fig.3). Gain for asymmetrical RF input 1999 Aug 30 8 Philips Semiconductors Product specification Satellite ZERO-IF QPSK down-converter handbook, full pagewidth TDA8060TS 50 Ω 100 Ω RF SOURCE Vi (dB) 50 Ω 50 Ω 1 pF RFA 1 pF RFB IOUT TDA8060TS QOUT RF SOURCE 50 Ω high impedance probe Vo (dB) MGM319 Fig.3 Gain control diagram for symmetrical RF input. handbook, full pagewidth 50 Ω 1.5 pF RFB 1.5 pF RFA IOUT TDA8060TS QOUT RF SOURCE FCE406 50 Ω RF SOURCE 50 Ω Vi (dB) Fig.4 Gain control diagram for asymmetrical RF input 1999 Aug 30 9 high impedance probe Vo (dB) Philips Semiconductors Product specification Satellite ZERO-IF QPSK down-converter APPLICATION INFORMATION Nevertheless, TDA8060 internally filters the baseband at 100 MHz and the nominal levels at inputs and outputs mentioned in the specification table should be respected. The input impedance of LP1 and LP2 must exceed 400 Ω to avoid signal distortion. Close attention should be paid to the design of the external tank circuit of the VCO so that it covers the 920 to 2200 MHz frequency range. Both series 6 Ω resistors kill all parasitic oscillations that could alter this frequency range. The BB835 Siemens varicap diodes are mentioned because they provide the highest Cmax/Cmin ratio as well as the least parasitic elements in our frequency range. The U-shaped inductance can be printed with a total length of approximately 20 mm. The converter outputs (pin IOUT and pin QOUT) must be AC-coupled via the low-pass filter to the baseband amplifiers inputs (pin IBBIN and pin QBBIN). Because of the high impedance at pin IQBBIN, a 100 nF capacitor gives a high-pass frequency of 160 Hz. Filters LP1 and LP2 are not detailed in this data sheet because their design only depends on the global system. As the TDA8060 has been designed to be compatible with DVB, DSS and Asian DVB, the cut-off frequencies and the tolerance in group delay, the orders of the filters cannot be globally established. 1999 Aug 30 TDA8060TS 10 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... VCC(LO1) LOGND1 VCC(LO2) LOGND2 6 16 9 19 15 CONVERSION STAGE 1 pF × RFA 8 RFB 7 COMGAIN 4 RF (2) RF IOUT IBBIN 2 24 I CONVERTER SYM ASYM AMP 23 IBBOUT LOW-PASS FILTER(3) to I channel ADC 14 QBBOUT LOW-PASS FILTER(3) to Q channel ADC 1 VCC(BB1) 12 VCC(BB2) 3 BBGND1 10 BBGND2 100 MHz BASEBAND STAGE LNA Q CONVERTER 1 pF gain(1) 22 × SYM AMP ASYM 100 MHz 100 nF STABILIZED LO PLL AND AMPLIFIER 11 QUADRATURE GENERATOR TDA8060TS 0 to 5 V PEN 5 DIVIDE-BY-2 OSCILLATOR 20 21 18 17 11 LOOUT LOOUTC TKA TKB QOUT QBBIN 6Ω 6Ω 13 Philips Semiconductors 100 nF VCC(RF) RFGND Satellite ZERO-IF QPSK down-converter pagewidth 1999 Aug 30 LOW-PASS FILTER(3) MGM320 100 nF 1 pF LOW-PASS FILTER(3) to PLL synthesizer IC 20 kΩ BB835 (2×) 20 kΩ Fig.5 Application diagram. Product specification (1) Gain control voltage; minimum gain at 0.1 x VCC, maximum gain at 0.9 x VCC; 30 dB range. (2) Differential RF input 950 to 2200 MHz; level = −22 to −52 dBm per channel. (3) The filter input impedance is 400 Ω minimum. TDA8060TS Vtune from PLL synthesizer IC Philips Semiconductors Product specification Satellite ZERO-IF QPSK down-converter TDA8060TS PACKAGE OUTLINE SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm D SOT340-1 E A X c HE y v M A Z 24 13 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 12 bp e detail X w M 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2.0 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 8.4 8.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 0.8 0.4 8 0o Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT340-1 1999 Aug 30 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 93-09-08 95-02-04 MO-150AG 12 o Philips Semiconductors Product specification Satellite ZERO-IF QPSK down-converter SOLDERING TDA8060TS If wave soldering is used the following conditions must be observed for optimal results: Introduction to soldering surface mount packages • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. Reflow soldering The footprint must incorporate solder thieves at the downstream end. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Wave soldering Manual soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. To overcome these problems the double-wave soldering method was specifically developed. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 1999 Aug 30 13 Philips Semiconductors Product specification Satellite ZERO-IF QPSK down-converter TDA8060TS Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE REFLOW(1) WAVE BGA, SQFP not suitable HLQFP, HSQFP, HSOP, HTSSOP, SMS not PLCC(3), SO, SOJ suitable suitable(2) suitable suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1999 Aug 30 14 Philips Semiconductors Product specification Satellite ZERO-IF QPSK down-converter NOTES 1999 Aug 30 15 TDA8060TS Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 545004/25/03/pp16 Date of release: 1999 Aug 30 Document order number: 9397 750 04984