PHILIPS PCA9516

INTEGRATED CIRCUITS
PCA9516
5-channel I2C hub
Product data
Supersedes data of 2002 Mar 01
2002 May 13
Philips Semiconductors
Product data
5-channel I2C hub
PCA9516
PIN CONFIGURATION
SCL0 1
DESCRIPTION
The PCA9516 is a BiCMOS integrated circuit intended for
application in I2C and SMBus systems.
I2C
While retaining all the operating modes and features of the
system, it permits extension of the I2C bus by buffering both the data
(SDA) and the clock (SCL) lines, thus enabling five buses of 400 pF.
The I2C bus capacitance limit of 400 pF restricts the number of
devices and bus length. Using the PCA9516 enables the system
designer to divide the bus into five segments off of a hub where any
segment to segment transition sees only one repeater delay.
16
VCC
SDA0
2
15
EN4
SCL1
3
14
SDA4
SDA1
4
13
SCL4
EN1
5
12
EN3
SCL2
6
11
SDA3
SDA2
7
10
SCL3
GND
8
9
EN2
SU01395
Figure 1. Pin configuration
It can also be used to run different buses at 5 V and 3.3 V or
400 kHz and 100 kHz buses where the 100 kHz bus is isolated
when 400 kHz operation of the other bus is required.
PIN DESCRIPTION
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
FEATURES
• 5 channel, bi-directional buffer
• I2C-bus and SMBus compatible
• Active high individual repeater enable input
• Open-drain input/outputs
• Lock-up free operation
• Supports arbitration and clock stretching across the repeater
• Accommodates standard mode and fast mode I2C devices and
multiple masters
• Powered-off high impedance I2C pins
• Operating supply voltage range of 3.0 V to 3.6 V
• 5 V tolerant I2C and enable pins
• 0 to 400 kHz clock frequency1
• ESD protection exceeds 2000 V HBM per JESD22-A114,
SYMBOL
SCL0
SDA0
SCL1
SDA1
EN1
SCL2
SDA2
GND
EN2
SCL3
SDA3
EN3
SCL4
SDA4
EN4
VCC
FUNCTION
Serial clock bus 0
Serial data bus 0
Serial clock bus 1
Serial data bus 1
Active High Bus 1 enable Input
Serial clock bus 2
Serial data bus 2
Supply ground
Active High Bus 2 enable Input
Serial clock bus 3
Serial data bus 3
Active High Bus 3 enable Input
Serial clock bus 4
Serial data bus 4
Active High Bus 4 enable Input
Supply power
200 V MM per JESD22-A115, and 1000 V CDM per
JESD22-C101.
• Latch-up testing is done to JEDEC Standard JESD78 which
exceeds 100 mA.
• Package offerings: SO and TSSOP
ORDERING INFORMATION
DESCRIPTION
16-pin plastic SO (narrow)
TEMPERATURE RANGE
ORDER CODE
DRAWING NUMBER
–40 to +85 °C
PCA9516D
SOT109-1
16-pin plastic TSSOP
–40 to +85 °C
PCA9516PW
Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging.
1.
SOT403-1
The maximum system operating frequency may be less than 400 KHz because of the delays added by the repeater.
2002 May 13
2
853–2234 28185
Philips Semiconductors
Product data
5-channel I2C hub
PCA9516
VCC
PCA9516
Buffer
SCL0
Buffer
SCL1
SCL2
Buffer
SDA0
Buffer
SDA1
Buffer
SDA2
Buffer
Buffer
SCL4
Buffer
SCL3
Buffer
SDA4
Buffer
SDA3
Hub
Logic
Hub
Logic
EN1
EN4
EN2
EN3
SU01396
GND
Figure 2. Block Diagram: PCA9516
A more detailed view of Figure 2 buffer is shown in Figure 3.
To output
Data
z
In
Inc
Enable
SW00712
Figure 3.
The output pull-down of each internal buffer is set for approximately
0.5 V, while the input threshold of each internal buffer is set about
0.07 V lower, when the output is internally driven low. This prevents
a lock-up condition from occurring.
2002 May 13
3
Philips Semiconductors
Product data
5-channel I2C hub
PCA9516
the other side to also go low. The side driven low by the PCA9516
will typically be at VOL = 0.5 V.
FUNCTIONAL DESCRIPTION
The PCA9516 BiCMOS integrated circuit is a five way hub repeater,
which enables I2C and similar bus systems to be expanded with
only one repeater delay and no functional degradation of system
performance.
In order to illustrate what would be seen in a typical application,
refer to Figures 5 and 6. If the bus master in Figure 4 were to write
to the slave through the PCA9516, we would see the waveform
shown in Figure 5 on Bus 0. This looks like a normal I2C
transmission until the falling edge of the 8th clock pulse. At that
point, the master releases the data line (SDA) while the slave pulls it
low through the PCA9516. Because the VOL of the PCA9516 is
typically around 0.5 V, a step in the SDA will be seen. After the
master has transmitted the 9th clock pulse, the slave releases the
data line.
The PCA9516 BiCMOS integrated circuit contains five bi-directional,
open drain buffers specifically designed to support the standard
low-level-contention arbitration of the I2C-bus. Except during
arbitration or clock stretching, the PCA9516 acts like five pairs of
non-inverting, open drain buffers, one for SDA and one for SCL.
Enable
The enable pins EN1 through EN4 are active high and have internal
pull-up resistors. Each enable pin ENn controls its associated SDAn
and SCLn ports. When low the ENn pin blocks the inputs from SDAn
and SCLn as well as disabling the output drivers on the SDAn and
SCLn pins. The enable pins should only change state when both the
global bus and the local port are in an idle state to prevent system
failures.
3.3 V
The active high enable pins allow the use of open drain drivers
which can be wire-ORed to create a distributed enable where either
centralized control signal (master) or spoke signal (submaster) can
enable the channel when it is idle.
SDA
5V
SDA0
SDA1
SDA
SCL0
SCL1
SCL
SLAVE 1
SCL
BUS
MASTER
PCA9516
I2C Systems
EN1
As with the standard I2C system, pull-up resistors are required to
provide the logic HIGH levels on the Buffered bus. (Standard
open-collector configuration of the I2C-bus). The size of these
pull-up resistors depends on the system, but each side of the
repeater must have a pull-up resistor. This part designed to work
with standard mode and fast mode I2C devices in addition to SMBus
devices. Standard mode I2C devices only specify 3 mA output drive,
this limits the termination current to 3 mA in a generic I2C system
where standard mode devices and multiple masters are possible.
Under certain conditions higher termination currents can be used.
Please see Application Note AN255 “I 2C & SMBus Repeaters, Hubs
and Expanders” for additional information on sizing resistors and
precautions when using more than one PCA9515/PCA9516 in a
system or using the PCA9515/16 in conjunction with the P82B96.
EN2
400 kHz
3.3 V
EN3
EN4
400 kHz
SDA2
SDA
SCL2
SCL
SLAVE 2
400 kHz
5V
SDA3
SDA
SCL3
SCL
SLAVE 3
APPLICATION INFORMATION
100 kHz
5V
A typical application is shown in Figure 4. In this example, the
system master is running on a 3.3 V I2C-bus while the slave is
connected to a 5 V bus. All buses run at 100 kHz unless slave 3 and
4 are isolated and then the master bus and slave 1 and 2 can run at
400 kHz.
Any segment of the hub can talk to any other segment of the hub.
Bus masters and slaves can be located on all five segments with
400 pF load allowed on each segment.
SDA4
SDA
SCL4
SCL
SLAVE 4
100 kHz
The PCA9516 is 5 V tolerant so it does not require any additional
circuitry to translate between the different bus voltages.
SW00923
When one side of the PCA9516 is pulled low by a device on the
I2C-bus, a CMOS hysteresis type input detects the falling edge and
causes an internal driver on the other side to turn on, thus causing
2002 May 13
Figure 4. Typical application
4
Philips Semiconductors
Product data
5-channel I2C hub
PCA9516
2 V/DIV
9th CLOCK PULSE
VOL OF PCA9516
VOL OF MASTER
SW00965
Figure 5. Bus 0 waveform
On the Bus 1 side of the PCA9516, the clock and data lines would
have a positive offset from ground equal to the VOL of the PCA9516.
After the 8th clock pulse, the data line will be pulled to the VOL of the
slave device that is very close to ground in our example.
It is important to note that any arbitration or clock stretching events
on Bus 1 require that the VOL of the devices on Bus 1 be 70 mV
below the VOL of the PCA9516 (see VOL – Vilc in the DC
Characteristics section) to be recognized by the PCA9516 and then
transmitted to Bus 0.
2 V/DIV
9th CLOCK PULSE
VOL OF PCA9516
VOL OF SLAVE
SW00966
Figure 6. Bus 1 waveform
2002 May 13
5
Philips Semiconductors
Product data
5-channel I2C hub
PCA9516
ABSOLUTE MAXIMUM RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134).
Voltages with respect to pin GND.
LIMITS
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
V
VCC to GND
Supply voltage range VCC
–0.5
+7
Vbus
Voltage range I2C-bus, SCL or SDA
–0.5
+7
V
I
DC current (any pin)
—
50
mA
Ptot
Power dissipation
—
300
mW
Tstg
Storage temperature range
–55
+125
°C
Tamb
Operating ambient temperature range
–40
+85
°C
DC ELECTRICAL CHARACTERISTICS
VDD = 3.0 to 3.6 V; GND = 0 V; Tamb = –40 to +85 °C; unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
MIN.
TYP.
MAX.
UNIT
Supplies
VCC
DC supply voltage
3.0
3.3
3.6
V
ICCH
Quiescent supply current,
both channels HIGH
VCC = 3.6 V;
SDAn = SCLn = VCC
—
7
10
mA
ICCL
Quiescent supply current,
both channels LOW
VCC = 3.6 V;
one SDA and one SCL = GND,
other SDA and SCL open
—
6.8
10
mA
ICCLc
Quiescent supply current in contention
VCC = 3.6 V;
SDAn = SCLn = GND
—
7
10
mA
Input SCL; input/output SDA
VIH
High-level input voltage
0.7 VCC
—
5.5
V
VIL
Low-level input voltage (Note 1)
–0.5
—
0.3 VCC
V
VILc
Low-level input voltage contention
(Note 1)
–0.5
—
0.4
V
VIK
Input clamp voltage
II = –18 mA
—
—
–1.2
V
II
Input leakage current
VI = 3.6 V
—
—
±1
µA
IIL
Input current LOW, SDA, SCL
VI = 0.2 V, SDA, SCL
µA
Low level output
IOL = 0 or 6 mA
Low level input voltage below
output low level voltage
IOH
CI
VOL
VOL–VILc
—
—
5
0.47
.52
0.6
V
Guaranteed by design
—
—
70
mV
Output high level leakage current
VO = 3.6 V
—
—
10
µA
Input capacitance
VI = 3 V or 0 V
—
6
10
pF
V
Enable 1–4
VIL
LOW level input voltage
–0.5
—
0.8
VIH
HIGH level input voltage
2.0
—
5.5
V
—
10
30
µA
–1
—
1
µA
—
6
7
pF
IIL
Input current LOW, EN1–EN4
ILI
Input leakage current
CI
Input capacitance
VI = 0.2 V, EN1–EN4
VI = 3.0 V or 0 V
NOTE:
1. VIL specification is for enable input and the first low level seen by the SDAx/SCLx lines. VILc is for the second and subsequent low levels
seen by the SDAx/SCLx lines.
2002 May 13
6
Philips Semiconductors
Product data
5-channel I2C hub
PCA9516
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
LIMITS
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
tPHL
Propagation delay
Waveform 1
57
115
170
ns
tPLH
Propagation delay
Waveform 1
33
55
78
ns
tTHL
Transition time
Waveform 1
67
ns
tTLH
Transition time
Waveform 1; Note 1
135
ns
tSET
Enable to Start condition
100
ns
tHOLD
Enable after Stop condition
100
ns
NOTE:
1. The tTLH transition time is guaranteed with loads of 1.35 kΩ pull-up resistance and 7 pF load capacitance, plus an additional 50 pF load
capacitance. Different load resistance and capacitance will alter the RC time constant, thereby changing the propagation delay and
transition times.
AC WAVEFORMS
TEST CIRCUIT
VCC
3.3 V
INPUT
1.5 V
1.5 V
VIN
0.1 V
tPHL
D.U.T.
3.3 V
80%
RT
80%
1.5 V
20%
RL
VOUT
PULSE
GENERATOR
tPLH
OUTPUT
VCC
CL
1.5 V
20%
VOL
tTHL
tTLH
Test Circuit for Open Drain Outputs
DEFINITIONS
SW00646
RL = Load resistor; 1.35 kΩ
Waveform 1.
CL = Load capacitance includes jig and probe capacitance;
7 pF
RT = Termination resistance should be equal to ZOUT of
pulse generators.
SW00792
2002 May 13
7
Philips Semiconductors
Product data
5-channel I2C hub
PCA9516
SO16: plastic small outline package; 16 leads; body width 3.9 mm
2002 May 13
8
SOT109-1
Philips Semiconductors
Product data
5-channel I2C hub
PCA9516
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
2002 May 13
9
SOT403-1
Philips Semiconductors
Product data
5-channel I2C hub
PCA9516
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent
to use the components in the I2C system provided the system conforms to the
I2C specifications defined by Philips. This specification can be ordered using the
code 9398 393 40011.
Data sheet status
Data sheet status [1]
Product
status [2]
Definitions
Objective data
Development
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be
published at a later date. Philips Semiconductors reserves the right to change the specification
without notice, in order to improve the design and supply the best possible product.
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply.
Changes will be communicated according to the Customer Product/Process Change Notification
(CPCN) procedure SNW-SQ-650A.
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
 Koninklijke Philips Electronics N.V. 2002
All rights reserved. Printed in U.S.A.
Contact information
For additional information please visit
http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
Date of release: 05-02
For sales offices addresses send e-mail to:
[email protected].
Document order number:
2002 May 13
10
9397 750 09815