PHILIPS PXAH40KFBE

INTEGRATED CIRCUITS
XA-H4
Single-chip 16-bit microcontroller
Preliminary specification
IC28 Data Handbook
1999 Sep 24
Philips Semiconductors
Preliminary specification
Single-chip 16-bit microcontroller
XA-H4
DESCRIPTION
The XA-H3 feature set is a subset of the XA-H4 (see Table 1). The
XA-H3/H4 devices are members of the Philips XA (eXtended
Architecture) family of high performance 16-bit microcontrollers.
The powerful 16-bit XA CPU core and rich feature set make the
XA-H3 and XA-H4 devices ideal for high-performance real-time
applications such as industrial control and networking. By supporting
of up to 32 MB of external memory, these devices provide a low-cost
solution to embedded applications of any complexity. Features like
DMA, memory controller and four advanced USARTs help solve I/O
intensive tasks with a minimum of CPU load.
The XA-H3 and XA-H4 are designed to significantly minimize the
need for external components.
FEATURES
• Large Memory Support
• De-multiplexed Address/Data Bus
• Six Programmable Chip Selects
• Dynamic Bus Timing – each of 6 chip selects has individual
programmable bus timing.
• 32 Programmable General Purpose I/O Pins
• Four USARTs with 230.4 kbps capability
• Eight DMA Channels
– Support for Unified Memory – allows easy user modification of
all code
– External ISP Flash support for easy code download
• Dynamic Bus Sizing – each of 6 Chip Selects can be programmed
for 8-bit or 16-bit bus.
ADDITIONAL XA-H4 FEATURES (NOT AVAILABLE ON XA-H3)
• Complete DRAM controller supports up to four banks of 8 MB each
• Memory controller supports 16 MB in Unified Mode
• Memory controller supports 32 MB in Harvard Mode
• Serial ports are USARTs
– Four Match Characters are supported on each USART in
Async Mode
– Hardware Autobaud on all four USARTs in Async Mode
– USARTs are improved 85C30 style
– Synchronous capability up to 1 Mbps, and include
HDLC/SDLC support
1999 Sep 24
2
Philips Semiconductors
Preliminary specification
Single-chip 16-bit microcontroller
XA-H4
Table 1. XA-H3 and XA-H4 features comparison
XA-H3
XA-H4
Maximum External Memory
(Harvard Memory Mode)
Feature
6 MB
32 MB
(16 MB Code, 16 MB Data)
Maximum External Memory
(Unified Memory Mode)
6 MB
16 MB
Memory Controller supports both Harvard and Unified architectures
Yes
Yes
De-multiplexed Address/Data Bus
Yes
Yes
DRAM Controller
No
Yes
8
8
Dynamic Bus Sizing
Yes
Yes
Dynamic Bus Timing
Yes
Yes
Programmable Chip Selects
6
6
General Purpose IO Pins
33
33
Potential Interrupt Pins
16
16
DMA Channels
Interrupts (programmable priority)
7 Standard SW
7 Standard SW
4 High Priority SW
4 High Priority SW
9 Hardware Event
9 Hardware Event
Yes
Yes
Two Counter/Timers plus Watchdog
Baud Rate
Generators1
4
4
4 UARTs
4 USARTs
asynch to 230.4 kbps (no sync)
asynch to 230.4 kbps
sync to 1 Mbps
Match Characters
No
4 async chars per USART
Hardware Autobaud
No
up to 230.4 kbps
Serial Ports
Maximum Serial Data Rates
NOTE:
1. Can be used as additional counters if not needed as BRGs.
ORDERING INFORMATION
ROMless Only
H4 = PXAH40KFBE
Temperature range °C and Package
Freq (MHz)
Package Drawing Number
–40 to +85°C, 100-Pin Low Profile Quad Flat Package (LQFP)
30
SOT407-1
NOTE
K=30 MHz, F = (–40 to +85), BE = LQFP
1999 Sep 24
3
Philips Semiconductors
Preliminary specification
Single-chip 16-bit microcontroller
XA-H4
CD1_Int2
VSS
76
Int0
79
VDD
P2.0_RxD3
80
77
P2.1_TxD3
81
78
P2.3_ComClk_TRClk3
P2.2_RTClk3
82
P2.4_CD3
84
83
P2.5_CTS3
85
P0.1_RTS0
91
P2.7_Sync3_BRG3
P0.2_CTS0
92
P2.6_RTS3
P0.3_CD0
93
86
P0.4_TRClk0
94
VSS
P0.5_RTClk0
95
87
TxD0
96
88
RxD0
97
89
GPOut
98
P0.0_Sync0_BRG0
P0.6
99
VDD
P0.7
100
DRAM CAS bits
NOTE: Address lines output during
various DRAM CAS cycles are shown
in parenthesis. See DRAM Controller
chapter in User Manual for details.
90
PIN CONFIGURATION
VSS
1
75
P1.7_BRG2_Sync2
VDD
2
74
P1.6_RTS2
A0
3
73
P1.5_CTS2
A1
4
72
P1.4_CD2
A2
5
71
P1.3_TRClk2
A3
6
70
P1.2_RTClk2
A4
7
69
P1.1_TxD2
A5
8
68
P1.0_RxD2
A6
9
67
P3.7_Int1_TRClk1
A7 (A21_22)
10
66
P3.6_TxD1
A8 (A19_A20)
11
65
P3.5_RxD1
A9 (A0_A18)
12
64
P3.4_CTS1
A10 (A1)
13
63
P3.3_Timer1_BRG1_Sync1
A11 (A2)
14
62
VDD
A12 (A3)
15
61
XTALOUT
A13 (A4)
16
60
XTALIN
A14 (A5)
17
59
VSS
A15 (A6_A22)
18
58
P3.2_Timer0_ResetOut
VSS
19
57
P3.1_CS5_RAS5_RTS1
VDD
20
56
P3.0_CS4_RAS4_RTClk1
A16 (A7_A20_A21)
21
55
Reset_In
A17 (A8_A18_A19)
22
54
BLE_CASL
A18
23
53
BHE_CASH
A19
24
52
WAIT_Size16
D0
25
51
OE
MOLD MARK
XA-H4
Top View 100 Pin LQFP
Base Part Number PXAH4
Current Part = PXAH40KFBE
K = 30 MHz, F = –40 to +85°C, BE = LQFP pkg
LQFP Package = SOT407-1
50
WE
CS0 49
CS1_RAS1 48
CS2_RAS2 47
ClkOut 45
CS3_RAS3 46
VSS 44
VDD 43
D15 42
D14 41
D13 40
D12 39
D11 38
D10 37
D9 36
D8 35
D7 34
D6 33
D5 32
D4 31
D3 30
VDD 29
VSS 28
D2 27
D1 26
MOLD MARK
SU01269
1999 Sep 24
4
Philips Semiconductors
Preliminary specification
Single-chip 16-bit microcontroller
XA-H4
LOGIC SYMBOL XA-H4
VDD
VSS
Int0
MISC.
UART1
Int2
CD1
CS4, RAS4
CS5, RAS5
ResetOut, Timer0
Timer1
RTClk1
RTS1
Int1
BRG1, Sync1
CTS1
RxD1
TxD1
TRClk1
XTAL1
PORT3
XTAL2
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
CS3, RAS3
CS2, RAS2
CS1, RAS1
CS0
UART3
RxD3
TxD3
RTClk3
ComClk, TRClk3
CD3
CTS3
RTS3
BRG3, Sync3
PORT2
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
A19 – A0 (DRAM A22 – A0)
D15 – D0
XA-H4
UART2
RxD2
TxD2
RTClk2
TRClk2
CD2
CTS2
RTS2
BRG2, Sync2
PORT1
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
ClkOut
CASH, BHE
CASL, BLE
OE
WE
UART0
PORT0
TxD0
RxD0
BRG0, Sync0
RTS0
CTS0
CD0
TRClk0
RTClk0
Wait, Size16
0.0
0.1
0.2
0.3
0.4
0.5
ResetIn
0.6
0.7
GPOut
SU01270
1999 Sep 24
5
Philips Semiconductors
Preliminary specification
Single-chip 16-bit microcontroller
XA-H4
XA-H4 BLOCK DIAGRAM
XA-H4 CPU Core
256 Bytes Data
SRAM
Data
MMR Bus
SFR Bus
DMA R0
Match Chars
USART 0
DMA T0
Port 0
Autobaud
Port 1
DMA R1
Match Chars
USART 1
DMA T1
Autobaud
Port 2
DMA R2
Match Chars
USART 2
Port 3
DMA T2
Autobaud
Timer 0
DMA R3
Match Chars
USART 3
DMA T3
Autobaud
Timer 1
Watchdog
Timer
DRAM
Controller
Memory Bus Controller
6 Chip Selects
Dynamic Bus Sizing
Dynamic Bus Timing
External
System Bus
SU01271
1999 Sep 24
6
Philips Semiconductors
Preliminary specification
Single-chip 16-bit microcontroller
XA-H4
XA-H4 MEMORY MAPS
FFFFFFh
Code and Data
Intermixed
Throughout
16 MB Space
000000h
Unified Memory
(also known as von Neuman architecture)
FFFFFFh
FFFFFFh
Code in
Dedicated
16 MB Space
Data in
Dedicated
16 MB Space
000000h
000000h
Harvard Architecture
SU01272
1999 Sep 24
7
Philips Semiconductors
Preliminary specification
Single-chip 16-bit microcontroller
XA-H4
PIN DESCRIPTIONS
Lqfp
Pin No.
Type
1, 19, 28,
44, 59,
76, 88
I
2, 20, 29,
43, 62,
77, 89
I
ResetIn
55
I
Reset: A low on this pin resets the microcontroller, causing I/O ports and peripherals to take on
their default states, and the processor to begin execution at the address contained in the reset
vector.
WAIT/
Size16
52
I
Wait/Size16: During Reset, this input determines bus size for boot device (“1” = 16-bit boot
device; “0” = 8-bit.) During normal operation this is the Wait input (“1” = Wait; “0” = Proceed.)
XTALIn
60
I
Crystal 1: Input to the inverting amplifier used in the oscillator circuit and input to the internal
clock generator circuits.
XTALOut
61
I
Crystal 2: Output from the oscillator amplifier.
Chip Select 0: This output provides the active low chip select to the boot device (usually ROM or
Flash.) It cannot be connected to DRAM. From reset, it is enabled and mapped to an address
range based at 000000h. It can be remapped by software to a higher base in the address map
(see the “Memory Interface” chapter in the XA-H4 User Manual.)
Mnemonic
VSS
VDD
Name and Function
See
Note
Ground: 0 V reference.
Power Supply: This is the power supply voltage for normal, idle, and power down operation.
CS0
49
O
CS1_RAS1
48
O
Chip Select 1 or RAS1: Chip Selects and RAS 1 through 5 come out of reset disabled. They can
be programmed to function as normal chip selects, or as RAS strobes to DRAM. CS1 can be
“swapped” with CS0 (see the SWAP operation and control bit in the “Memory Controller” chapter
of the XA-H4 User Manual.) CS1 is usually mapped to be based at 000000h after the swap, but is
capable of being based anywhere in the 16 MB space.
CS2_RAS2
47
O
Chip Select 2 or RAS2: Active low Chip Selects CS1 through CS5 come out of reset disabled.
They can be programmed to function as normal chip selects, or as RAS strobes to DRAM. CS2
through CS5 are not used with the “SWAP” operation (see the “Memory Controller” chapter in the
XA-H4 User Manual.) They are mappable to any region of the 16 MB address space.
CS3_RAS3
46
O
CS3 or RAS3: See Chip Select 2 for description.
See Pins 56, 57 for 2 additional Chip Selects
WE
50
O
Write Enable: Goes active low during all bus write cycles only.
OE
51
O
Output Enable: Goes active low during all bus read cycles only.
BLE_CASL
54
O
Byte Low Enable or CAS_Low_Byte: Goes active low during all bus cycles that access D7 – D0,
read or write, Generic or DRAM. Functions as CAS during DRAM cycles.
BHE_CASH
53
O
Byte High Enable or CAS_High_Byte: Goes active low during all bus cycles that access data
bus lines D15 – D8, read or write, Generic or DRAM. Functions as CAS during DRAM cycles.
ClkOut
45
O
Clock Output: This pin outputs a buffered version of the internal CPU clock. The clock output
may be used in conjunction with the external bus to synchronize WAIT state generators, etc. The
clock output may be disabled by software.
WARNING: The capacitive loading on this output must not exceed 40 pf.
A19 – A0
24 – 21,
18 – 3
O
Address[19:0]: These address lines output A19 – A0 during (SRAM, etc.) bus cycles.
D15 – D0
42 – 30,
27 – 25
I/O
Data[15:0]: Bi-directional data bus, D15 – D0.
P0.0
90
I/O
P0.0_Sync0_BRG0: Port 0 Bit 0, or USART0 Sync input or output, or USART0 BRG output, or
USART0 TxClk output.
1
P0.1
91
I/O
P0.1_RTS0: Port 0 Bit 1, or USART0 RTS (Request To Send) output.
1
P0.2
92
I/O
P0.2_CTS0: Port 0 Bit 2, or USART0 CTS (Clear To Send) input.
1
P0.3
93
I/O
P0.3_CD0: Port 0 Bit 3, or USART0 Carrier Detect input.
P0.4
94
I/O
P0.4_TRClk0: Port 0 Bit 4, or USART0 TR clock input.
1, 2
P0.5
95
I/O
P0.5_RTClk0: Port 0 Bit 5, or USART0 RT clock input.
1, 2
P0.6
99
I/O
P0.6: Port 0 Bit 6
1
P0.7
100
I/O
P0.7: Port 0 Bit 7
1
1999 Sep 24
DRAMS (H4 only) are connected only to pins 22, 21, 18 – 10 (pins A17 to A7; see user manual
“MIF Chapter” for connecting various DRAM sizes); the appropriate address values are
multiplexed onto these 11 pins for RAS and CAS during DRAM bus cycles.
8
1
Philips Semiconductors
Preliminary specification
Single-chip 16-bit microcontroller
Mnemonic
Lqfp
Pin No.
Type
XA-H4
Name and Function
See
Note
TxD0
96
O
TxD0: Transmit data for USART0.
RxD0
97
I
RxD0: Receive data for USART0.
GPOut
98
O
GPOut – General Purpose Output Bar: Similar to GPIO, but Push/Pull and inverted output only.
WARNING: This output is inverted. The polarity of the pin is the opposite of the bit that drives it
(GPOut[7])
P1.0
68
I/O
P1.0_RxD2: Port 1 Bit 0, or USART2 RxD input
P1.1
69
I/O
P1.1_TxD2: Port 1 Bit 1, or USART2 TxD output
P1.2
70
I/O
P1.2_RTClk2: Port 1 Bit 2, or USART2 RT Clock input
2
P1.3
71
I/O
P1.3_TRClk2: Port 1 Bit 3, or USART2 TR Clock input
2
P1.4
72
I/O
P1.4_CD2: Port 1 Bit 4, or USART2 Carrier Detect input
P1.5
73
I/O
P1.5_CTS2: Port 1 Bit 5, or USART2 Clear To Send input
P1.6
74
I/O
P1.6_RTS2: Port 1 Bit 6, or USART2 Request To Send output
P1.7
75
I/O
P1.7_BRG2_Sync2: Port 1 Bit 7, or USART2 Sync input or output, or BRG output, or TxClk
output (see USART clk diagrams in the user manual.)
P2.0
80
I/O
P2.0_RxD3: Port 2 Bit 0, or USART3 Rx Data input
P2.1
81
I/O
P2.1_TxD3: Port 2 Bit 1, or USART3 Tx Data output
P2.2
82
I/O
P2.2_RTClk3: Port 2 Bit 2, or USART3 RT Clock input
2
P2.3
83
I/O
P2.3_ComClk_TRClk3: Port 2 Bit 3, or USART3 TR Clock input
2
P2.4
84
I/O
P2.4_CD3: Port 2 Bit 4, or USART3 Carrier Detect input
P2.5
85
I/O
P2.5_CTS3: Port 2 Bit 5, or USART3 Clear To Send input
P2.6
86
I/O
P2.6_RTS3: Port 2 Bit 6, or USART3 Request To Send output
P2.7
87
I/O
P2.7_Sync3_BRG3: Port 2 Bit 7, or USART3 Sync input or output, or BRG output, or TxClk
output (see USART clock diagrams in the user manual.)
P3.0
56
I/O
P3.0_CS4_RAS4_RTClk1: Port 3 Bit 0, or CS4 or RAS 4 output, or USART1 RT Clock input
2
Active low chip selects CS1 through CS5 come out of reset disabled. They can be programmed to
function as normal chip selects, or as RAS strobes to DRAM. CS2 through CS5 are not used with
the “SWAP” operation (see the “Memory Controller” chapter in the XA-H4 User Manual.) They are
mappable to any region of the 16 MB address space.
P3.1_CS5_RTS1: Port 3 Bit 1, or CS5 output, or USART1 Request To Send output
P3.1
P3.2
57
58
I/O
I/O
Active low chip selects CS1 through CS5 come out of reset disabled. They can be programmed to
function as normal chip selects, or as RAS strobes to DRAM. CS2 through CS5 are not used with
the “SWAP” operation (see the “Memory Controller” chapter in the XA-H4 User Manual.) They are
mappable to any region of the 16 MB address space.
P3.2_Timer0_ResetOut: Port 3 Bit 2, or Timer0 input or output, or ResetOut output.
ResetOut: If the ResetOut function is selected, this pin outputs a low whenever the XA-H4
processor is reset by an internal source (Watchdog Reset or the RESET instruction.)
WARNING: Unlike the other 31 GPIO pins, during power up reset, this pin can output a strongly
driven low pulse. The duration of this low pulse ranges from 0 ns to 258 system clocks, starting at
the time that VCC is valid. The state of the ResetIn pin does not affect this pulse.
When used as GPIO, this pin can be driven low by software without resetting the XA-H4.
P3.3
63
I/O
P3.3_Timer1_BRG1_Sync1: Port 3 Bit 3, or Timer1 input or output, or USART1 BRG output, or
USART1 Sync input or output.
P3.4
64
I/O
P3.4_CTS1: Port 3 Bit 4, or USART1 Clear To Send input
P3.5
65
I/O
P3.5_RxD1: Port 3 Bit 5, or USART1 Receive Data input
P3.6
66
I/O
P3.6_TxD1: Port 3 Bit 6, or USART1 Transmit Data output
P3.7
67
I/O
P3.7_Int1_TRClk1: Port 3 Bit 7, or External Interrupt 1 input, or USART1 TR Clock input
CD1_Int2
78
I/O
CD1_Int2: USART1 Carrier Detect, or External Interrupt 2
Int0
79
I/O
External Interrupt 0
2
NOTES:
1. See XA-H4 User Guide, “Pins Chapter,” for how to program selection of pin functions.
2. RTClk input is usually used for Rx Clock if an external clock is needed, but can be used for either Rx or Tx or both. TRClk is usually used for
Tx Clock, but can be used for Rx or Tx or both.
1999 Sep 24
9
Philips Semiconductors
Preliminary specification
Single-chip 16-bit microcontroller
XA-H4
CONTROL REGISTER OVERVIEW
There are two types of control registers in the XA-H4, these are SFRs
(Special Function Registers), and MMRs (Memory Mapped Registers.)
The SFR registers, with the exception of MRBL, MRBH, MICFG, BCR,
BRTH, BRTL, and RSTSRC are the standard XA core registers. See
WARNINGs about BCR, BRTH, and BRTL in Table 2.
on-chip peripherals, and can be accessed by any addressing mode
that can be used for off-chip data accesses. The MMRs are
implemented in a relocatable block. See the “Memory Controller”
chapter in the XA-H4 User Manual for details on how to relocate the
MMRs by writing a new base address into the MRBL and MRBH
(MMR Base Low and High) registers.
SFRs are accessed by “direct addressing” only (see IC25 XA User
Manual for direct addressing.) The MMRs are specific to the XA-H4
Table 2. Special Function Registers (SFR)
Name
BCR
Description
Bus Configuration Reg
SFR
Address
Bit Functions and Addresses
MSB
LSB
Reset
Value
46Ah
WARNING – Never write to the BCR register in the XA-H4 – it is initialized to 07h,
the only legal value. This is not the same as for some other XA derivatives.
07h
WARNING – Immediately after reset, always write BTRH = 51h, followed by
writing BTRL = 40h in that order
order. Follow these two writes with five NOPS.
NOPS This is
not the same as for some other XA derivatives.
FFh
RESERVED – see
Warning
BTRH
Bus Timing Reg High
469h
BTRL
Bus Timing Reg Low
468h
MRBL#
MMR Base Address Low
496h
MA15
MA14
MA13
MA12
–
–
–
MRBE
MRBH#
MMR Base Address High
497h
MA23
MA22
MA21
MA20
MA19
MA18
MA17
MA16
xx
MICFG#
ClkOut Tri-St Enable
1 = Enabled
499h
–
–
–
–
–
–
–
CLKOE
01h
CS
Code Segment
443h
00h
DS
Data Segment
441h
00h
ES
Extra Segment
442h
00h
33F
33E
33D
33C
33B
33A
339
338
EHSWR3
EHSWR2
EHSWR1
EHSWR0
–
EAuto
ESC23
ESC01
EFh
x0h
IEH*
Interrupt Enable High
427h
337
336
335
334
333
332
331
330
IEL*
Interrupt Enable Low
426h
EA
EDMAH
EDMAL
EX2
ET1
EX1
ET0
EX0
IPA0
Interrupt Priority A0
4A0h
–
PT0
–
PX0
00h
IPA1
Interrupt Priority A1
4A1h
–
PT1
–
PX1
00h
IPA2
Interrupt Priority A2
4A2h
–
PDMAL
–
PX2
00h
IPA3
Interrupt Priority A3
4A3h
IPA4
Interrupt Priority A4
4A4h
–
IPA5
Interrupt Priority A5
4A5h
IPA6
Interrupt Priority A6
4A6h
IPA7
Interrupt Priority A7
4A7h
P0*
Port 0
430h
P1*
P2*
P3*
1999 Sep 24
Port 1
Port 2
Port 3
Reserved
00h
00h
–
PDMAH
00h
PSC23
–
PSC01
00h
–
–
–
PAutoB
00h
–
PHSWR1
–
PHSWR0
00h
–
PHSWR3
–
PHSWR2
00h
387
386
385
384
383
382
381
380
38F
38E
38D
38C
38B
38A
389
388
397
396
395
394
393
392
391
390
39F
39E
39D
39C
39B
39A
399
398
FFh
431h
FFh
432h
FFh
433h
FFh
10
Philips Semiconductors
Preliminary specification
Single-chip 16-bit microcontroller
Name
Description
SFR
Address
XA-H4
Bit Functions and Addresses
MSB
LSB
Reset
Value
P0CFGA
Port 0 Configuration A
470h
5
P1CFGA
Port 1 Configuration A
471h
5
P2CFGA
Port 2 Configuration A
472h
5
P3CFGA
Port 3 Configuration A
473h
5
P0CFGB
Port 0 Configuration B
4F0h
5
P1CFGB
Port 1 Configuration B
4F1h
5
P2CFGB
Port 2 Configuration B
4F2h
5
P3CFGB
Port 3 Configuration B
4F3h
5
PCON*
PSWH*
PSWL*
Power Control Reg
Program Status Word High
Program Status Word Low
404h
401h
400h
227
226
225
224
223
222
221
220
–
–
–
–
–
–
PD
IDL
20F
20E
20D
20C
20B
20A
209
208
SM
TM
RS1
RS0
IM3
IM2
IM1
IM0
207
206
205
204
203
202
201
200
C
AC
–
–
–
V
N
Z
217
216
215
214
213
212
211
210
00h
2
2
PSW51*
80C51 Compatible PSW
402h
C
AC
F0
RS1
RS0
V
F1
P
3
RSTSRC
Reset Source Reg
463h
ROEN
–
–
–
–
R_WD
R_CMD
R_EXT
7
RTH0
Timer 0 Reload High
455h
00h
RTH1
Timer 1 Reload High
457h
00h
RTL0
Timer 0 Reload Low
454h
00h
RTL1
Timer 1 Reload Low
456h
00h
SCR
System Configuration Reg
440h
–
–
–
–
PT1
PT0
CM
PZ
21F
21E
21D
21C
21B
21A
219
218
00h
SSEL*
Segment Selection Reg
403h
ESWEN
R6SEG
R5SEG
R4SEG
R3SEG
R2SEG
R1SEG
R0SEG
00h
SWE
Software Interrupt Enable
47Ah
–
SWE7
SWE6
SWE5
SWE4
SWE3
SWE2
SWE1
00h
SWR*
42Ah
357
356
355
354
353
352
351
350
–
SWR7
SWR6
SWR5
SWR4
SWR3
SWR2
SWR1
287
286
285
284
283
282
281
280
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
00h
TCON*
Timer 0/1 Control
410h
TH0
Timer 0 High
451h
00h
TH1
Timer 1 High
453h
00h
TL0
Timer 0 Low
450h
00h
TL1
Timer 1 Low
452h
TMOD
Timer 0/1 Mode
45Ch
1999 Sep 24
00h
00h
GATE
C/T
M1
11
M0
GATE
C/T
M1
M0
00h
Philips Semiconductors
Preliminary specification
Single-chip 16-bit microcontroller
Name
Description
SFR
Address
XA-H4
Bit Functions and Addresses
MSB
LSB
Reset
Value
28F
28E
28D
28C
28B
28A
289
288
TSTAT*
Timer 0/1 Extended Status
411h
–
–
–
–
–
T1OE
–
T0OE
2FF
2FE
2FD
2FC
2FB
2FA
2F9
2F8
WDCON*
Watchdog Control
41Fh
PRE2
PRE1
PRE0
–
–
WDRUN
WDTOF
–
WDL
Watchdog Timer Reload
45Fh
00h
WFEED1
Watchdog Feed 1
45Dh
x
WFEED2
Watchdog Feed 2
45Eh
x
00h
6
NOTES:
* SFRs marked with an asterisk (*) are bit addressable.
# SFRs marked with a pound sign (#) are additional SFR registers specific to the XA-H3 and XA-H4.
1. The XA-H4 implements an 8-bit SFR bus, as stated in Chapter 8 of the IC25 Data Handbook XA User Guide. All SFR accesses must be
8-bit operations. Attempts to write 16 bits to an SFR will actually write only the lower 8 bits. 16-bit SFR reads will return undefined data in
the upper byte.
2. SFR is loaded from the reset vector.
3. F1, F0, and P reset to “0”. All other bits are loaded from the reset vector.
4. Unimplemented bits in SFRs are “X” (unknown) at all times. “1”s should not be written to these bits since they may be used for other
purposes in future XA derivatives. The reset value shown for these bits is “0”.
5. Port configurations default to quasi-bidirectional when the XA begins execution after reset. Thus all PnCFGA registers will contain FFh and
PnCFGB register will contain 00h. See warning in XA-H4 User Manual about P3.2_Timer0_ResetOut pin during first 258 clocks after power up.
Basically, during this period, this pin may output a strongly-driven low pulse. If the pulse does occur, it will terminate in a transition to high at a
time no later than the 259th system clock after valid VCC power up.
6. The WDCON reset value is E6 for a Watchdog reset; E4 for all other reset causes.
7. The RSTSRC register reflects the cause of the last XA reset. One bit will be set to “1”, the others will be “0”. RSTSRC[7] enables the ResetOut
function; “1” = Enabled, “0” = Disabled. See XA-H4 User Manual for details; RSTSRC[7] differs in function from most other XA derivatives.
8. The XA guards writes to certain bits (typically interrupt flags) that may be written by a peripheral function. This prevents loss of an interrupt or
other status if a bit was written directly by a peripheral action between the read and write of an instruction that performs a read-modify-write
operation. XA-H4 SFR bits that are guarded in this manner are: TF1, TF0, IE1, and IE0 (in TCON), and WDTOF (in WDCON).
1999 Sep 24
12
Philips Semiconductors
Preliminary specification
Single-chip 16-bit microcontroller
XA-H4
Table 3. Memory Mapped Registers (MMR)
MMR Name
Read/Write
or Read Only
Size
Address
Offset
Description
Reset
Value
USART0 Registers
USART0 Write Register 0
R/W
8
800h
Command register
00h
USART0 Write Register 1
R/W
8
802h
Tx/Rx Interrupt & data transfer mode
xx
USART0 Write Register 2
R/W
8
804h
Extended Features Control
xx
USART0 Write Register 3
R/W
8
806h
Receive Parameter and Control
00h
USART0 Write Register 4
R/W
8
808h
Tx/Rx miscellaneous parameters & mode
00h
USART0 Write Register 5
R/W
8
80Ah
Tx parameter and control
00h
USART0 Write Register 6 (XA-H4 only)
R/W
8
80Ch
HDLC/SDLC address field or asynch Match Character 0
00h
USART0 Write Register 7
R/W
8
80Eh
HDLC/SDLC flag or Match Character 1
xx
USART0 Write Register 8
R/W
8
810h
Transmit Data Buffer
xx
USART0 Write Register 9
R/W
8
812h
Master Interrupt control
xx
USART0 Write Register 10
R/W
8
814h
Miscellaneous Tx/Rx control register
00h
USART0 Write Register 11
R/W
8
816h
Clock Mode Control
xx
USART0 Write Register 12
R/W
8
818h
Lower Byte of Baud rate time constant
00h
USART0 Write Register 13
R/W
8
81Ah
Upper Byte of Baud rate time constant
00h
USART0 Write Register 14
R/W
8
81Ch
Miscellaneous Control bits
xx
USART0 Write Register 15
R/W
8
81Eh
External/Status interrupt control
f8h
USART0 Write Register 16
R/W
8
828h
Match Character 2 (WR16)
00h
USART0 Write Register 17
R/W
8
82Ah
Match Character 3 (WR17)
00h
USART0 Read Register 0
RO
8
820h
Tx/Rx buffer and external status
USART0 Read Register 1
RO
8
822h
Receive condition status/residue code
Reserved – do not write
USART0 Read Register 3
824h
8
USART0 Read Register 6
RO
8
82Ch
SDLC byte count low register
USART0 Read Register 7
RO
8
82Eh
SDLC byte count high and FIFO status
USART0 Read Register 8
RO
8
830h
Receive Buffer
see WR16 and 17
828–82Ah
Reserved
USART0 Read Register 10
826h
–
RO
Interrupt Pending Bits
see WR16 and 17 above
832h
RO
8
Reserved
834h
Loop/clock status
836-83Eh
–
USART1 Registers
USART1 Write Register 0
R/W
8
840h
Command register
00h
USART1 Write Register 1
R/W
8
842h
Tx/Rx Interrupt & data transfer mode
xx
USART1 Write Register 2
R/W
8
844h
Extended Features Control
xx
USART1 Write Register 3
R/W
8
846h
Receive Parameter and Control
00h
USART1 Write Register 4
R/W
8
848h
Tx/Rx miscellaneous parameters & mode
00h
USART1 Write Register 5
R/W
8
84Ah
Tx parameter and control
00h
USART1 Write Register 6
R/W
8
84Ch
HDLC/SDLC address field or Match Character 0
00h
USART1 Write Register 7
R/W
8
84Eh
HDLC/SDLC flag or async Match Character 1
xx
USART1 Write Register 8
R/W
8
850h
Transmit Data Buffer
xx
USART1 Write Register 9
R/W
8
852h
Master Interrupt control
xx
USART1 Write Register 10
R/W
8
854h
Miscellaneous Tx/Rx control register
00h
USART1 Write Register 11
R/W
8
856h
Clock Mode Control
xx
USART1 Write Register 12
R/W
8
858h
Lower Byte of Baud rate time constant
00h
USART1 Write Register 13
R/W
8
85Ah
Upper Byte of Baud rate time constant
00h
1999 Sep 24
13
Philips Semiconductors
Preliminary specification
Single-chip 16-bit microcontroller
XA-H4
Read/Write
or Read Only
Size
Address
Offset
USART1 Write Register 14
R/W
8
85Ch
Miscellaneous Control bits
xx
USART1 Write Register 15
R/W
8
85Eh
External/Status interrupt control
f8h
USART1 Write Register 16
R/W
8
868h
Match Character 2 (WR16)
00h
USART1 Write Register 17
R/W
8
86Ah
Match Character 3 (WR17)
00h
USART1 Read Register 0
RO
8
860h
Tx/Rx buffer and external status
USART1 Read Register 1
RO
8
862h
Receive condition status/residue code
RO
8
866
8
86Ch
see WR16 and 17 above
MMR Name
Reserved
USART1 Read Register 3
Description
864h
see WR16 and WR17
Interrupt Pending Bits
USART1 Read Register 6
RO
8
86Eh
SDLC byte count low register
USART1 Read Register 7
RO
8
86Eh
SDLC byte count high and FIFO status
USART1 Read Register 8
RO
8
870h
Receive Buffer
RO
8
Reserved
USART1 Read Register 10
Reset
Value
872h
Reserved
874h
Loop/clock status
876-87Eh
USART2 Registers
USART2 Write Register 0
R/W
8
880h
Command register
00h
USART2 Write Register 1
R/W
8
882h
Tx/Rx Interrupt & data transfer mode
xx
USART2 Write Register 2
R/W
8
884h
Extended Features Control
xx
USART2 Write Register 3
R/W
8
886h
Receive Parameter and Control
00h
USART2 Write Register 4
R/W
8
888h
Tx/Rx miscellaneous parameters & mode
00h
USART2 Write Register 5
R/W
8
88Ah
Tx parameter and control
00h
USART2 Write Register 6
R/W
8
88Ch
HDLC/SDLC address field or Match Character 0
00h
USART2 Write Register 7
R/W
8
88Eh
HDLC/SDLC flag or Match Character 1
xx
USART2 Write Register 8
R/W
8
890h
Transmit Data Buffer
xx
USART2 Write Register 9
R/W
8
892h
Master Interrupt control
xx
USART2 Write Register 10
R/W
8
894h
Miscellaneous Tx/Rx control register
00h
USART2 Write Register 11
R/W
8
896h
Clock Mode Control
xx
USART2 Write Register 12
R/W
8
898h
Lower Byte of Baud rate time constant
00h
USART2 Write Register 13
R/W
8
89Ah
Upper Byte of Baud rate time constant
00h
USART2 Write Register 14
R/W
8
89Ch
Miscellaneous Control bits
xx
USART2 Write Register 15
R/W
8
89Eh
External/Status interrupt control
f8h
USART2 Write Register 16
R/W
8
8A8h
Match Character 2 (WR16)
00h
USART2 Write Register 17
R/W
8
8AAh
Match Character 3 (WR17)
00h
USART2 Read Register 0
RO
8
8A0h
Tx/Rx buffer and external status
USART2 Read Register 1
RO
8
8A2h
Receive condition status
Reserved
USART2 Read Register 3
8A4h
RO
see WR16 and WR17
8
8A6h
Interrupt Pending Bits
8
8ACh
see WR16 and 17 above
USART2 Read Register 6
RO
8
8AEh
SDLC byte count low register
USART2 Read Register 7
RO
8
8AEh
SDLC byte count high and FIFO status
USART2 Read Register 8
RO
8
8B0h
Receive Buffer
Reserved
USART2 Read Register 10
Reserved
1999 Sep 24
8B2h
RO
8
8B4h
8B6-8BEh
14
Loop/clock status
Philips Semiconductors
Preliminary specification
Single-chip 16-bit microcontroller
MMR Name
Read/Write
or Read Only
XA-H4
Size
Address
Offset
Description
Reset
Value
USART3 Registers
USART3 Write Register 0
R/W
8
8C0h
Command register
00h
USART3 Write Register 1
R/W
8
8C2h
Tx/Rx Interrupt & data transfer mode
xx
USART3 Write Register 2
R/W
8
8C4h
Extended Features Control
xx
USART3 Write Register 3
R/W
8
8C6h
Receive Parameter and Control
00h
USART3 Write Register 4
R/W
8
8C8h
Tx/Rx miscellaneous parameters & mode
00h
USART3 Write Register 5
R/W
8
8CAh
Tx parameter and control
00h
USART3 Write Register 6
R/W
8
8CCh
HDLC/SDLC address field or Match Character 0
00h
USART3 Write Register 7
R/W
8
8CEh
HDLC/SDLC flag or Match Character 1
xx
USART3 Write Register 8
R/W
8
8D0h
Transmit Data Buffer
xx
USART3 Write Register 9
R/W
8
8D2h
Master Interrupt control
xx
USART3 Write Register 10
R/W
8
8D4h
Miscellaneous Tx/Rx control register
00h
USART3 Write Register 11
R/W
8
8D6h
Clock Mode Control
xx
USART3 Write Register 12
R/W
8
8D8h
Lower Byte of Baud rate time constant
00h
USART3 Write Register 13
R/W
8
8DAh
Upper Byte of Baud rate time constant
00h
USART3 Write Register 14
R/W
8
8DCh
Miscellaneous Control bits
xx
USART3 Write Register 15
R/W
8
8DEh
External/Status interrupt control
f8h
USART3 Write Register 16
R/W
8
8E8h
Match Character 2 (WR16)
00h
USART3 Write Register 17
R/W
8
8EAh
Match Character 3 (WR17)
00h
USART3 Read Register 0
RO
8
8E0h
Tx/Rx buffer and external status
USART3 Read Register 1
RO
8
8E2h
Receive condition status/residue code
Reserved
8E4h
USART3 Read Register 3
RO
8
8E6h
Interrupt Pending Bits
USART3 Read Register 6
RO
8
8ECh
SDLC byte count low register
USART3 Read Register 7
RO
8
8EEh
SDLC byte count high and FIFO status
USART3 Read Register 8
RO
8
8F0h
Receive Buffer
RO
8
Reserved
USART3 Read Register 10
8F2h
Reserved
8F4h
–
Loop/clock status
8F6-8FEh
Rx DMA Registers
DMA Control Register Ch.0 Rx
R/W
8
100h
Control Register
00h
FIFO Control & Status Reg Ch.0 Rx
R/W
8
101h
Control & Status Register
00h
Segment Register Ch.0 Rx
R/W
8
102h
Points to 64 k data segment
00h
00h
Buffer Base Register Ch.0 Rx
R/W
8
104h
Wrap Reload Value for A15 – A8, A7 – A0 reloaded
to zero by hardware
Buffer Bound Register Ch.0 Rx
R/W
16
106h
Upper Bound (plus 1) on A15 – A0
0000h
Address Pointer Reg Ch.0 Rx
R/W
16
108h
Current Address pointer A15 – A0
0000h
Corresponds to A15 – A0 Byte Count, generates
interrupt if enabled and byte count exceeded.
0000h
10Ch = Byte 0 = older,
00h
10Dh = Byte 1 = younger
00h
10Eh = Byte 2 = older,
00h
10Fh = Byte 3 = younger
00h
Byte Count Register Ch.0 Rx
R/W
16
10Ah
Data FIFO Register Ch.0 Lo Rx
R/W
16
10Ch
Data FIFO Register Ch.0 Hi Rx
R/W
16
10Eh
DMA Control Register Ch.1 Rx
R/W
8
110h
Control Register
00h
FIFO Control & Status Register Ch.1 Rx
R/W
8
111h
Control & Status Register
00h
Segment Register Ch. 1 Rx
R/W
8
112h
Points to 64 k data segment
00h
1999 Sep 24
15
Philips Semiconductors
Preliminary specification
Single-chip 16-bit microcontroller
XA-H4
Read/Write
or Read Only
Size
Address
Offset
Buffer Base Register Ch. 1 Rx
R/W
8
114h
Wrap Reload Value for A15 – A8, A7 – A0 reloaded
to zero by hardware
00h
Buffer Bound Register Ch.1 Rx
R/W
16
116h
Upper Bound (plus 1) on A15 – A0
0000h
Address Pointer Reg Ch.1 Rx
R/W
16
118h
Current Address pointer A15 – A0
0000h
Corresponds to A15 – A0 Byte Count, generates
interrupt if enabled and byte count exceeded.
0000h
11Ch = Byte 0 = older,
00h
11Dh = Byte 1 = younger
00h
11Eh = Byte 2 = older,
00h
11Fh = Byte 3 = younger
00h
MMR Name
Byte Count Register Ch.1 Rx
R/W
16
11Ah
Data FIFO Register Ch.1 Lo Rx
R/W
16
11Ch
Description
Reset
Value
Data FIFO Register Ch.1 Hi Rx
R/W
16
11Eh
DMA Control Register Ch.2 Rx
R/W
8
120h
Control Register
00h
FIFO Control & Status Register Ch.2 Rx
R/W
8
121h
Control & Status Register
00h
Segment Register Ch. 2 Rx
R/W
8
122h
Points to 64 k data segment
00h
00h
Buffer Base Register Ch. 2 Rx
R/W
8
124h
Wrap Reload Value for A15 – A8, A7 – A0 reloaded to
zero by hardware
Buffer Bound Register Ch.2 Rx
R/W
16
126h
Upper Bound (plus 1) on A15 – A0
0000h
Address Pointer Reg Ch.2 Rx
R/W
16
128h
Current Address pointer A15 – A0
0000h
Corresponds to A15 – A0 Byte Count, generates
interrupt if enabled and byte count exceeded.
0000h
12Ch = Byte 0 = older,
00h
12Dh = Byte 1 = younger
00h
12Eh = Byte 2 = older,
00h
Byte Count Register Ch.2 Rx
R/W
16
12Ah
Data FIFO Register Ch.2 Lo Rx
R/W
16
12Ch
Data FIFO Register Ch.2 Hi Rx
R/W
16
12Eh
12Fh = Byte 3 = younger
00h
DMA Control Register Ch.3 Rx
R/W
8
130h
Control Register
00h
FIFO Control & Status Register Ch.3 Rx
R/W
8
131h
Control & Status Register
00h
Segment Register Ch. 3 Rx
R/W
8
132h
Points to 64 k data segment
00h
Buffer Base Register Ch. 3 Rx
R/W
8
134h
Wrap Reload Value for A15 – A8, A7 – A0 reloaded to
zero by hardware
00h
Buffer Bound Register Ch.3 Rx
R/W
16
136h
Upper Bound (plus 1) on A15 – A0
0000h
Address Pointer Reg Ch.3 Rx
R/W
16
138h
Current Address pointer A15 – A0
0000h
Corresponds to A15 – A0 Byte Count, generates
interrupt if enabled and byte count exceeded.
0000h
13Ch = Byte 0 = older,
00h
13Dh = Byte 1 = younger
00h
13Eh = Byte 2 = older,
00h
13Fh = Byte 3 = younger
00h
Byte Count Register Ch.3 Rx
R/W
16
13Ah
Data FIFO Register Ch.3 Lo Rx
R/W
16
13Ch
Data FIFO Register Ch.3 Hi Rx
R/W
16
13Eh
DMA Control Register Ch.0 Tx
R/W
8
140h
Control Register
00h
FIFO Control & Status Register Ch.0 Tx
R/W
8
141h
Control & Status Register
00h
Segment Register Ch. 0 Tx
R/W
8
142h
Points to 64 k data segment
00h
00h
Tx DMA Registers
Buffer Base Register Ch. 0 Tx
R/W
8
144h
Wrap Reload Value for A15 – A8, A7 – A0 reloaded
to zero by hardware
Buffer Bound Register Ch.0 Tx
R/W
16
146h
Upper Bound (plus 1) on A15 – A0
0000h
Address Pointer Reg Ch.0 Tx
R/W
16
148h
Current Address pointer A15 – A0
0000h
Corresponds to A15 – A0 Byte Count, generates
interrupt if enabled and byte count exceeded.
0000h
Byte Count Register Ch.0 Tx
R/W
16
14Ah
Data FIFO Register Ch.0 Tx
R/W
16
14Ch
1999 Sep 24
16
14C = Byte0 = older
14D = Byte 1 = younger
0000h
Philips Semiconductors
Preliminary specification
Single-chip 16-bit microcontroller
XA-H4
Read/Write
or Read Only
Size
Address
Offset
Data FIFO Register Ch.0 Tx
R/W
16
14Eh
DMA Control Register Ch.1 Tx
R/W
8
150h
Control Register
00h
FIFO Control & Status Register Ch.1 Tx
R/W
8
151h
Control & Status Register
00h
Segment Register Ch.1 Tx
R/W
8
152h
Points to 64 k data segment
00h
00h
MMR Name
Description
14E = Byte2 = older
14F = Byte3 = younger
Reset
Value
0000h
Buffer Base Register Ch.1 Tx
R/W
8
154h
Wrap Reload Value for A15 – A8, A7 – A0 reloaded
to zero by hardware
Buffer Bound Register Ch.1 Tx
R/W
16
156h
Upper Bound (plus 1) on A15 – A0
0000h
Address Pointer Reg Ch.1 Tx
R/W
16
158h
Current Address pointer A15 – A0
0000h
0000h
Byte Count Register Ch.1 Tx
R/W
16
15Ah
Corresponds to A15 – A0 Byte Count, generates
interrupt if enabled and byte count exceeded.
Data FIFO Register Ch.1 Lo Tx
R/W
16
15Ch
Byte0 & 1
0000h
Data FIFO Register Ch.1 Hi Tx
R/W
16
15Eh
Byte2 & 3
0000h
DMA Control Register Ch.2 Tx
R/W
8
160h
Control Register
00h
FIFO Control & Status Register Ch.2 Tx
R/W
8
161h
Control & Status Register
00h
Segment Register Ch.2 Tx
R/W
8
162h
Points to 64 k data segment
00h
00h
Buffer Base Register Ch.2 Tx
R/W
8
164h
Wrap Reload Value for A15 – A8, A7 – A0 reloaded
to zero by hardware
Buffer Bound Register Ch.2 Tx
R/W
16
166h
Upper Bound (plus 1) on A15 – A0
0000h
Address Pointer Reg Ch.2 Tx
R/W
16
168h
Current Address pointer A15 – A0
0000h
Byte Count Register Ch.2 Tx
R/W
16
16Ah
Corresponds to A15 – A0 Byte Count, generates
interrupt if enabled and byte count exceeded.
0000h
Data FIFO Register Ch.2 Lo Tx
R/W
16
16Ch
Byte0 & 1
0000h
Data FIFO Register Ch.2 Hi Tx
R/W
16
16Eh
Byte2 & 3
0000h
DMA Control Register Ch.3 Tx
R/W
8
170h
Control Register
00h
FIFO Control & Status Register Ch.3 Tx
R/W
8
171h
Control & Status Register
00h
Segment Register Ch. 3 Tx
R/W
8
172h
Points to 64 k data segment
00h
Buffer Base Register Ch. 3 Tx
R/W
8
174h
Buffer Bound Register Ch.3 Tx
R/W
16
176h
Upper Bound (plus 1) on A15 – A0
0000h
Address Pointer Reg Ch.3 Tx
R/W
16
178h
Current Address pointer A15 – A0
0000h
0000h
Wrap Reload Value for A15 – A8,
A7 – A0 reloaded to zero by hardware
00h
Byte Count Register Ch.3 Tx
R/W
16
17Ah
Corresponds to A15 – A0 Byte Count, generates
interrupt if enabled and byte count exceeded.
Data FIFO Register Ch.3 Lo Tx
R/W
16
17Ch
Byte0 & 1
0000h
Data FIFO Register Ch.3 Hi Tx
R/W
16
17Eh
Byte2 & 3
0000h
RESERVED for future DMA
–
R/W
180-1FEh
Miscellaneous DMA Registers
Rx Character Time Out Register Ch.0
R/W
8
200h
0 value disables counter interrupt
00h
Rx Character Time Out Register Ch.1
R/W
8
202h
Same as above, for Rx1
00h
Rx Character Time Out Register Ch.2
R/W
8
204h
Same as above, for Rx2
00h
Rx Character Time Out Register Ch.3
R/W
8
206h
Same as above, for Rx3
00h
Global DMA Interrupt Register
R/W
16
210h
DMA Interrupt Flags
0000h
GPOut
R/W
8
260h
BDAEE (H4 Only)
R/W
8
270h
Autobaud echo enable (H4 Only)
00h
BDCS (H4 Only)
R/W
8
272h
Autobaud Control and Status (H4 Only)
00h
GPOut[7] drives pin 98 (GPOut) through an inverter.
GPOut[6-0] are unused, and must be written with
zeroes.
8xh
Autobaud Registers (H4 Only)
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Philips Semiconductors
Preliminary specification
Single-chip 16-bit microcontroller
MMR Name
Read/Write
or Read Only
XA-H4
Size
Address
Offset
Reset
Value
Description
Memory Interface (MIF) Registers
B0CFG
R/W
8
280h
MIF Bank 0 Config
0Fh
B0AM
R/W
8
281h
MIF Bank 0 Base Address
00h
B0TMG
R/W
8
282h
MIF Bank 0 Timing Params
B1CFG
R/W
8
284h
MIF Bank 1 Config
B1AM
R/W
8
285h
MIF Bank 1 Base Address
B1TMG
R/W
8
286h
MIF Bank 1 Timing Params
B2CFG
R/W
8
288h
MIF Bank 2 Config
B2AM
R/W
8
289h
MIF Bank 2 Base Address
B2TMG
R/W
8
28Ah
MIF Bank 2 Timing Params
B3CFG
R/W
8
28Ch
MIF Bank 3 Config
B3AM
R/W
8
28Dh
MIF Bank 3 Base Address
B3TMG
R/W
8
28Eh
MIF Bank 3 Timing Params
B4CFG
R/W
8
290h
MIF Bank 4 Config
B4AM
R/W
8
291h
MIF Bank 4 Base Address
B4TMG
R/W
8
292h
MIF Bank 4 Timing Params
B5CFG
R/W
8
294h
MIF Bank 5 Config
B5AM
R/W
8
295h
MIF Bank 5 Base Address
B5TMG
R/W
8
296h
MIF Bank 5 Timing Params
MBCL
R/W
8
2BEh
MIF Memory Bank Configuration Lock Register
RFSH
R/W
8
2BFh
MIF Refresh Control
Miscellaneous Registers
Hi-Pri Soft Ints & Pin Mux Control Reg.
R/W
16
2D0h
Control bits for Hi-Priority Soft Ints, and Pin Mux
0000h
XInt2
R/W
8
2D2h
External Interrupt 2 Control
00h
FUNCTIONAL DESCRIPTION
The XA-H4 functions are described in the following sections.
Because all blocks are thoroughly documented in either the IC25 XA
Data Handbook, or the XA-H4 User Manual, only brief descriptions
are given in this datasheet in conjunction with references to the
appropriate document.
XA CPU
BIU
XA CPU
The CPU is a 30 MHz implementation of the standard XA CPU core.
See the XA Data Handbook (IC25) for details. The CPU core is
identical to the G3 core. See the caveat in the next paragraph about
the Bus Interface Unit.
Internal CPU Bus
External
Memory
and I/O Bus
Bus Interface Unit (BIU)
MIF and DRAM
Controller
DMA
Channels
x8
This is the internal Bus, not the bus at the pins. This internal bus
connects the CPU to the MIF (Memory and DRAM Controller.)
SU01273
WARNING: Immediately after reset, always write BTRH = 51h,
followed by BTRL = 40h, in that order. Once written, do not change
the values in these registers. Follow these two writes with five
NOPS. Never write to the BCR register. It comes out of reset
initialized to 07h, which is the only value that will work.
Figure 1. XA CPU core BIU (Bus Interface Unit)
Timers 0 and 1
Timers 0 and 1 are the standard XA-G3 Timer 0 and 1. Each has an
associated I/O pin and interrupt. See the XA-G3 data sheet in the IC25
XA Data Handbook for details. Many XA derivatives include a standard
XA Timer 2 and standard UARTs. These blocks have been removed in
order to provide other functions on the XA-H4. There is no Timer 2 and
the UARTs have been replaced with full function USARTs.
1999 Sep 24
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Philips Semiconductors
Preliminary specification
Single-chip 16-bit microcontroller
XA-H4
Watchdog Timer
ResetOut
This timer is a standard XA-G3 Watchdog Timer. See the G3
datasheet in IC25. Also, if you intend to use the Watchdog Timer to
assert the ResetOut pin, see “ResetOut” in the XA-H4 User Manual.
The Watchdog Timer is enabled at reset, and must be periodically
fed to prevent timeout. If the watchdog times out, it will generate an
internal reset; if ResetOut is enabled, the internal reset will generate
a ResetOut pulse (active low pulse on ResetOut pin.)
The P3.2_Timer0_ResetOut pin provides an external indication (if the
ResetOut function is enabled in the RSRSRC register) via an active
low output when an internal reset occurs (internal reset is Reset
instruction or Watchdog time out.) If the ResetOut function is enabled,
the ResetOut pin will be driven low when a Watchdog reset occurs or
the Reset instruction is executed. This signal may be used to inform
other devices in the system that the XA-H4 has been internally reset.
The ResetIn signal does NOT get passed on to ResetOut. When
activated, the duration of the ResetOut pulse is 256 system clocks.
Reset
On the XA-H4 there are two pins associated with reset. The ResetIn
pin provides an external reset into the XA-H4. The port pin
P3.2_Timer0_ResetOut output can be configured as ResetOut.
WARNING: At power on time, from the time that power coming up is
valid, the P3.2_Timer0_ResetOut pin may be driven low for any
period from zero nanoseconds up to 258 system clocks. This is true
independently of whether ResetIn is active or not.
Because ResetOut does not reflect ResetIn, the ResetOut pin can
be tied directly back into the ResetIn pin without other PC board
logic. This configuration will make all resets (internal or external)
appear to the XA as external resets. See the XA-H4 User Manual for
a full discussion of the reset functions.
Reset Source Register
The Reset Source Identification Register (RSTSRC) indicates the
cause of the most recent XA reset. The cause may have been an
externally applied reset signal, execution of the RESET instruction, or
a Watchdog reset. Figure 2 shows the fields in the RSTSRC register.
If the ResetOut function is tied back into the ResetIn pin, then all
resets will be external resets, and will thus appear as external resets
in the reset source register. RSTSRC[7] enables the ResetOut
function; 1 = Enabled, 0 = Disabled. See XA-H4 User Manual for
details; RSTSRC[7] differs in function from most other XA derivatives.
ResetIn
The ResetIn function is the standard XA-G3 ResetIn function. The
ResetIn signal does NOT get passed on to ResetOut. See the
XA-H4 User Manual for details on reset.
RSTSRC
Reg Type and Address = SFR 463h
Not Bit Addressable
Reset Value = see below
MSB
ROEN
LSB
—
—
—
—
R_WD
R_CMD
R_EXT
BIT
SYMBOL
FUNCTION
RSTSRC.7
ROEN
ResetOut function enable bit – see XA-H3 User Manual for details
RSTSRC.6
–
Reserved for future use. Should not be set to 1 by user programs.
RSTSRC.5
–
Reserved for future use. Should not be set to 1 by user programs.
RSTSRC.4
–
Reserved for future use. Should not be set to 1 by user programs.
RSTSRC.3
–
Reserved for future use. Should not be set to 1 by user programs.
RSTSRC.2
R_WD
Indicates that the last reset was caused by a watchdog timer overflow (see WARNING.)
RSTSRC.1
R_CMD
Indicates that the last reset was caused by execution of the RESET instruction (see WARNING.)
RSTSRC.0
R_EXT
Indicates that the last reset was caused by the external ResetIn input.
WARNING:
If ResetOut function is tied back into ResetIn pin, RSTSRC will always show external reset ONLY, because external reset always takes
precedence over internal reset.
SU01237
Figure 2. RSTSRC reset source register
The XA-H4 has a highly programmable memory bus interface with a
complete complete onboard DRAM controller. Most DRAMs (up to
8 MB per RAS pin), SRAMs, Flash, ROMs, and peripheral chips can
be connected to this interface with zero glue chips. The bus interface
provides 6 mappable chip select outputs, five of which can be
programmed to function as RAS strobes to DRAM. CAS generation,
proper address multiplexing for a wide range of DRAM sizes, and
refresh are all generated onboard. The bus timing for each individual
DRAM CONTROLLER AND MEMORY / I/O BUS
INTERFACE (MIF)
In the memory or system bus interface terminology, generic bus cycles
are synonymous with SRAM bus cycles, because these cycles are
designed to service SRAMs, Flash, EEPROM, peripheral chips, etc.
Chip select output pins function as either CS or RAS (DRAMS and
thus RAS on X-4H only) depending on whether the memory bank has
been programmed as generic or DRAM.
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Philips Semiconductors
Preliminary specification
Single-chip 16-bit microcontroller
XA-H4
Each memory bank and associated chip select programmed for
“generic” (SRAM, Flash, ROM, peripheral chips, etc.) is capable of
supporting a 1 MB address space.
memory bank or peripheral can be programmed to accommodate
slow or fast devices.
Each memory bank and its associated RAS (chip select in DRAM
mode) output, can be programmed to access up to an 8 MB
mappable address space in either EDO or FPM DRAM modes (up
to a total of 32 MB of DRAM. WARNING: Future XA-H4 derivatives
may not support separate code and data spaces.)
The Memory Interface can be programmed to support both Intel
style and 68000 bus style SRAMs and peripherals.
XA-H4
CS5 or RAS5 (or P3.1, RTS1)
Memory Interface
CS4 or RAS4 (or P3.0, RTClk1)
CS3 or RAS3
DRAM Controller
SRAM Controller
Dynamic Bus Sizing
Progammable Bus Timing
CS2 or RAS2
CS1 or RAS1
CS0
A19–A0
(on DRAM cycle, A22 – A0
are Time-Multiplexed for RAS/CAS)
D15–D0
ClkOut
BHE or CASH
BLE or CASL
OE
WE
WAIT, SIZE16
SU01274
Figure 3. Memory bus interface signal pins
Bus Interface Pins
Chip Select Pins
For the following discussion, see Figure 3.
There are six chip select pins (CS5 – CS0) mapped to six sets of bank
control registers. The following attributes are individually programmable
for each bank and associated chip select (or RAS, if DRAM): bank
on/off, address range, external device access time, detailed bus strobe
sequence, DRAM cycle or generic bus cycle, DRAM size if DRAM,
and bus width. Pin CS0 is always generic in order to service the boot
device, thus CS0 cannot be connected to DRAM.
WARNING: On the external bus, ALL XA-H4 reads are 16-bit Reads. If the CPU instruction only specifies 8-bits, then the CPU uses the appropriate
byte, and discards the extra byte. Thus “8-Bit Reads” and “16-Bit Reads” appear to be identical on the bus. On an 8-bit bus, this will appear
as two consecutive 8-bit reads even though the CPU instruction specified a byte read.
Some 8-bit I/O devices (especially FIFOs) cannot operate correctly with 2 bytes being read for a 1 Byte Read. The most common (and least
expensive) solution is to operate these 8-bit devices on a 16-bit bus, and access them in software on all odd byte (or all even byte) boundaries.
An added benefit of this technique is that byte Reads are faster than on an 8-bit bus, because only 1 word is fetched (a single Read) instead of
2 consecutive bytes.
1999 Sep 24
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Philips Semiconductors
Preliminary specification
Single-chip 16-bit microcontroller
XA-H4
Clock Output
ClkOut to be output enabled at reset, but it may be turned off
(tri-state disabled) by software via the MICFG MMR.
WARNING: The capacitive loading on this output must not
exceed 40 pf.
The ClkOut pin allows easier external bus interfacing in some
situations. This output reflects the XTALIn clock input to the XA
(referred to internally as CClk or System Clock), but is delayed to
match the external bus outputs and strobes. The default is for
CS0
CS
A16–A0
XA-H4
D7–D0
OE
128 k x 8 ROM
A16–A0
D7–D0
CS1
RAS
CASL
CASH
OE
A17–A9
D15–D0
CS2
256 k x 16 DRAM
(HM514260DI)
WE
A8–A0
D15–D0
RAS
CASL
CASH
OE
OE
1 M x 16 DRAM
(MT4C1M16C3)
WE
A17–A8
A19–A0
D15–D0
A9–A0
D15–D0
D15–D0
CS3
RAS
BLE
CASL
BHE
CASH
WE
32 k x 16 SRAM
WE
A15–A1
D15–D0
A15–A1
D15–D0
NOTE:
The 16-bit wide RAM does not need the A0 pin from the processor. During byte writes to the RAM, the A0 value will cause
either BLE or BHE pin to go active from the XA-H3, but not to both. For all Word Writes, Word Reads, Code Fetches, and
Byte Reads, both BLE and BHE will go active.During DRAM cycles only, the appropriate CAS Address will be multiplexed
onto pins A17 – A7 after the assertion of RAS and prior to the assertion of BHE (CASH) and BLE (CASL.) See AC timing
diagrams and the XA-H4 User Manual for complete details.
Figure 4. Typical system bus configuration
1999 Sep 24
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SU01275
Philips Semiconductors
Preliminary specification
Single-chip 16-bit microcontroller
XA-H4
Table 4. Memory interface control registers
Register Name
Reg
Type
Description
MRBH
“MMR Base Address” High
SFR
8 bits
This SFR is used to relocate the MMRs. It contains address bits a23 – a16 of the base
address for the 4 kB Memory Mapped Register space. See the XA-H4 User Manual for
using this SFR to relocate the MMRs.
MRBL
“MMR Base Address” Low
SFR
8 bits
Contains address bits a15 – a12 of the base address for the 4 kB Memory Mapped
Register space.
MICFG
MIF Configuration
MMR
8 bits
Contains the ClkOut Enable bit.
MBCL
Memory Bank Configuration
Lock
MMR
8 bits
Contains the bits for locking and unlocking the BiCFG Registers.
BiCFG
Bank i Configuration
MMR
8 bits
Contains the size, type, bus width, and enable bits for Memory Bank i.
BiAM
Bank i Base Address/DRAM
Address Multiplexer Control
MMR
8 bits
Contains the base address bits and DRAM address multiplex control bits for
Memory Bank i.
BiTMG
Bank i Timing
MMR
8 bits
Contains the timing control bits for Memory Bank i.
RFSH
Refresh Timing
MMR
8 bits
Contains the refresh time constant and DRAM Refresh Timer enable bit.
EIGHT CHANNEL DMA CONTROLLER
The XA-H3/H4 has eight DMA channels; one Rx DMA channel
dedicated to each USART Receive (Rx) channel, and one Tx DMA
channel dedicated to each USART Transmit (Tx) channel. All DMA
channels are optimized to support memory efficient circular data
buffers in external memory. All DMA channels can also support
traditional linear data buffers.
Transmit DMA Channel Modes
The four Tx channels have four DMA modes specifically designed
for various applications of the attached USARTs. These modes are
summarized in Table 5. Full details for all DMA functions can be
found in the DMA chapter of the XA-H4 User Manual.
Table 5. Tx DMA modes summary
Mode
Byte Count Source
Maskable Interrupt
Description
Non-SDLC/HDLC
Tx Chaining
Header in memory
On stop
DMA channel picks up header from memory at the
end of transmission. If the byte count in the header
is greater than zero, then DMA transmits the number
of bytes specified in the byte count. If byte count
equals 0, then a maskable interrupt is generated.
This process repeats until the byte count in the data
header is zero. See XA-H4 User Manual for details.
SDLC/HDLC
Tx Chaining
Header in memory
End of packet (not end
of fragment)
Same as above, except DMA header distinguishes
between fragment of packet and full pack. See
XA-H4 User Manual for details.
Stop on TC
Processor loads Byte Count Register (for
each fragment)
Byte count completed
(Tx DMA stops)
Processor loads byte count into DMA. DMA sends
that number of bytes, generates maskable interrupt,
and stops.
Periodic Interrupt
Porcessor loads Byte Count Register
(only once)
When Byte Counter
reaches zero and is
reloaded by DMA
hardware from the byte
count register.
DMA runs until commanded to stop by processor.
Every time byte counter rolls over, a new
maskable interrupt is generated.
1999 Sep 24
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Philips Semiconductors
Preliminary specification
Single-chip 16-bit microcontroller
XA-H4
Receive DMA Channel Modes
The Rx DMA channels have four DMA modes specifically designed
for various applications of the attached USARTs. These modes are
summarized in Table 6. For full details on implementation and use,
see the XA-H4 User Manual.
Table 6. Rx DMA modes summary
Mode
Byte Count Source
SDLC/HDLC
Rx Chaining
DMA stores byte count in header in
memory with data packet.
At end of received packet
Maskable Interrupt
When a complete or aborted SDLC/HDLC packet has
been received, the packet byte count and status
information are stored in memory with the packet. A
maskable interrupt is generated.
Periodic
Interrupt
Loaded by processor into DMA,
used only to determine the number
of bytes between interrupts.
Processor can infer the byte count
from the DMA address pointer.
When Byte Counter reaches
zero and is reloaded by
DMA hardware from the byte
count register.
The DMA channel runs until commanded to stop by the
processor. It generates a maskable interrupt once per n
bytes, where n is the number written once into the byte
count register by the processor, thus an interrupt is
generated once every n received bytes.
Asynchronous
Character
Time Out
Byte Count can be calculated by
software from the DMA address
pointer.
If no character is received
within a specified time out
period, then interrupt.
Processor specifies time out period between incoming
characters. If no character is received within that time,
a maskable interrupt is generated.
Asynchronous
Character
Match
Byte Count can be calculated by
software from the DMA address
pointer.
When matched character is
stored in memory.
There are four match registers, each incoming character
is received within that time, a maskable interrupt is
generated. When a matched character is stored in
memory by DMA, a maskable interrupt is generated.
Data FIFO 3
Data FIFO 2
Data FIFO 1
Data FIFO 0
Description
DMA Control
Segment
Buffer Base
Buffer Bound
Address Pointer
Rx Channel
Byte Count
FIFO Control
Rx Time Out
Data FIFO 3
Data FIFO 2
Data FIFO 1
Data FIFO 0
DMA Control
Segment
Tx Channel
Buffer Base
Buffer Bound
Address Pointer
Byte Count
FIFO Control
SU01240
Figure 5. Rx and Tx DMA Registers
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Philips Semiconductors
Preliminary specification
Single-chip 16-bit microcontroller
XA-H4
DMA Registers
• Synchronous character-oriented protocol features (XA-H4 only):
In addition to the 16-bit Global DMA Interrupt Register (which is shared
by all eight DMA channels), each DMA channel has seven control
registers and a four-byte Data FIFO. The four Rx DMA channels have
one additional register, the Rx Character Time Out Register. All DMA
registers can be read and written in Memory Mapped Register (MMR)
space. These registers are summarized below.
– Automatic CRC generation and checking
– External Sync option
• Data encoding/decoding options:
– FM0 (Biphase Space)
• Global DMA Interrupt Register (not shown in figure): All DMA
– FM1 (Biphase Mark)
interrupt flags are in this register .
– NRZ
• DMA Control Register: Contains the master mode select and
– NRZI
interrupt enable bits for the channel.
• Programmable Baud Rate Generator
• Auto Echo and Local Loopback modes
• Segment Register: Holds A23–A16 (the current segment) of the
24-bit data buffer address.
• Buffer Base Register: Holds a pointer (A15–A8) to the lowest byte
Autobaud Detectors
in the memory buffer.
Each USART has its own Autobaud detector, capable of baud rate
detection up to 921.6 kbaud. The detectors can be programmed to
automatically echo the industry standard autobaud sequences. They
can be programmed to update the necessary control registers in the
USARTs and turn on the receiver, which in turn will automatically
initiate DMA into memory of received data. Thus, once the baud rate
is determined, reception begins without intervention from the
processor. When the baud rate is detected, a maskable interrupt is
sent to the processor. See the “Autobaud” chapter in the XA-H4
User Manual for details.
• Buffer Bound Register: Points to the first out-of-bounds address
above a circular buffer.
• Address Pointer Register: Points to a single byte or word in the
data buffer in memory. The 24-bit DMA address is formed by
concatenating the contents of the Segment Register [A23–A16]
with the contents of the Address Pointer Register [A15–A0].
• Byte Count Register: Holds the initial number of bytes to be
transferred. In Tx Chaining mode, this register is not used
because the byte count is brought into the byte counter from
buffer headers in memory.
I/O Port Output Configuration
Port input/output configurations are the same as standard XA ports:
open drain, quasi-bidirectional, push-pull, and off (off means tri-state
Hi-Z, and allows the pin to be used as an input. WARNING: At
power on time, from the time that power coming up is valid, the
P3.2_Timer0_ResetOut pin may be driven low for any period from
zero nanoseconds up to 258 system clocks. This is true
independently of whether ResetIn is active or not.
• FIFO Control & Status Register: Holds the queuing order and
full/empty status for the Data FIFO Registers.
• Data FIFO Registers: A four-byte data FIFO buffer internal to the
DMA channel.
• Rx Char Time Out Register (RxCTOR, Rx DMA channels only):
Holds the initial value for an 8-bit character timeout countdown
timer which can generate an interrupt.
Power Reduction Modes
The XA-H4 supports Idle and Power Down modes of power
reduction. The idle mode leaves most peripherals running in order to
allow them to activate the processor when an interrupt is generated.
The power down mode stops the oscillator in order to absolutely
minimize power. The processor can be made to exit power down
mode via a reset or one of the external interrupt inputs (INT0 or
INT1). This will occur if the interrupt is enabled and its priority is
higher than that defined by IM3 through IM0. In power down mode,
the power supply voltage may be reduced to the RAM keep-alive
voltage VRAM. This retains the RAM, register, and SFR contents at
the point where power down mode was entered. WARNING: VDD
must be raised to within the operating range before power down
mode is exited.
Four USARTS
• Asynchronous features:
– Asynchronous transfers up to 921.6 kbps
– Can monitor input stream for up to four match characters per
receiver (H4 only)
– 5, 6, 7, or 8 data bits per character
– 1, 1.5, or 2 Stop bits per character
– Even or Odd parity generate and check
– Parity, Rx Overrun, and Framing Error detection
– Break detection
Interrupts
– Supports hardware Autobaud detection and response up to
921.6 kbps.
In the XA architecture, all exceptions, including Reset, are handled in
the same general exception structure. The highest priority exception
is, of course, Reset, and is non-maskable. All exceptions are vectored
through the Exception Vector Table in low memory. Coming out of
Reset, these vectors must be stored in non-volatile memory based at
location 000000. Later in the boot sequence, DRAM or SRAM can be
mapped into this address space if desired. There is a feature in the
XA-H4 Memory Controller called “Bank Swap” that supports replacing
the ROM vector table and other low memory with RAM. See the
XA-H4 User Manual for details.
• SDLC/HDLC features:
– Automatic Flag and Abort Character generation and recognition
– Automatic CRC generation and checking (can be disabled for
“pass-thru”)
– Automatic zero-bit insertion and stripping
– Automatic partial byte residue code generation
– 14-bit Packet byte count stored in memory with received packet
by DMA
1999 Sep 24
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Philips Semiconductors
Preliminary specification
Single-chip 16-bit microcontroller
XA-H4
See the IC25 XA Data Handbook for a full explanation of the
exception structure, including event interrupts, of the XA CPU.
Because the High Priority Software Interrupts are not implemented
on all XA derivitives, they are explained in the XA-H4 User Manual.
The XA-H4 has a standard XA CPU Interrupt Controller,
implemented with 15 Maskable Event Interrupts. Event Interrupts
are defined as maskable interrupts usually generated by hardware
events. However, in the XA-H4, 4 of the 15 Event Interrupts are
generated by software writing directly to the interrupt flag bit. These
4 interrupts are referred to as “High Priority Software Interrupts.”
XA Core
Interrupt Controller
DMAH
DMA
Interrupts
DMAL
CTS0
CD0
CTS1
USART0/
USART1
CD1_INT2
INT2
CTS2
CD2
CTS3
Interrupt
Enable/
Disable Bits
USART2/
USART3
Master
Enable
“EA”
Interrupt
To XA CPU
CD3
INT0
INT1
Autobaud
3–0
Timer 0
Timer 1
High Priority
Software Ints
HSWR 3–0
4
SU01276
Figure 6. XA-H4 Interrupt Structure Overview
1999 Sep 24
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Philips Semiconductors
Preliminary specification
Single-chip 16-bit microcontroller
XA-H4
Table 7. USART0 Interrupts (Interrupt structure is the same, except for bit locations, for all 4 USARTs)
Potential
USART0
Interrupt
Individual Enable Bit
Source Bit
Group Enable Bit(S)
Group Flag Bit
Master Enable Bit
MMR Hex Offset
MMR Hex Offset
MMR Hex Offset
MMR Hex Offset
MMR Hex Offset
WR1[4:3]
802[4:3]
Even Channel Rx IP
RR3[5]
826[5]
USART0/1 Master
Interrupt Enable
WR9[3]
812[3]
Rx Character Available
–
SDLC EOF
(XA-H4 Only)
CRC/Framing Error
Rx Overrun
RR0[0]
820[0]
–
RR1[7]
822[7]
–
RR1[6]
822[6]
–
RR1[5]
822[5]
Parity Error
WR1[2]
802[2]
RR1[4]
822[4]
Tx Buffer Empty
See WR1[1]
RR0[2]
820[2]
Tx Interrupt Enable
WR1[1]
802[1]
Even Channel Tx IP
RR3[4]
826[4]
Break/Abort
Break/
Abort IE
WR15[7]
81E[7]
RR0[7]
820[7]
Master External/Status
Interrupt Enable
WR1[0]
802[0]
Even Channel
External/Status IP
RR3[3]
826[3]
Tx Underrun/EOM
Tx Underrun/EOM IE
WR15[6]
81E[6]
RR0[6]
820[6]
CTS
CTS IE
WR15[5]
81E[5]
RR0[5]
820[5]
SYNC/HUNT
(XA-H4 Only)
SYNC/
HUNT IE
WR15[4]
81E[4]
RR0[4]
822[4]
DCD
DCD IE
WR15[3]
81E[3]
RR0[3]
820[3]
Zero Count
Zero Count IE
WR15[1]
81E[1]
RR0[1]
820[1]
EXCEPTION/TRAPS PRECEDENCE
Description
Vector Address
Arbitration Ranking
Reset (h/w, watchdog, s/w)
0000–0003
0 (High)
Break Point
0004–0007
1
Trace
0008–000B
1
Stack Overflow
000C–000F
1
Divide by 0
0010–0013
1
User RETI
0014–0017
1
TRAP 0–15 (software)
0040–007F
1
1999 Sep 24
26
Philips Semiconductors
Preliminary specification
Single-chip 16-bit microcontroller
XA-H4
EVENT INTERRUPTS
Description Event
Interrupt Source
Flag Bit
Interrupt Vector
Address
Enable Bit (SFR)
Priority Register Bit
Field (SFR)
Arb. Rank
High Priority
Software Interrupt 3
HSWR3
MMR 2D0[15]
00BF–00BC
EHSWR3
427[7]
33F
PHSWR3
4A7[6:4]
17
High Priority
Software Interrupt 2
HSWR2
MMR 2D0[14]
00BB–00B8
EHSWR2
427[6]
33E
PHSWR2
4A7[2:0]
16
High Priority
Software Interrupt 1
HSWR1
MMR 2D0[13]
00B7–00B4
EHSWR1
427[5]
33D
PHSWR1
4A6[6:4]
15
High Priority
Software Interrupt 0
HSWR0
MMR 2D0[12]
00B3–00B0
EHSWR0
427[4]
33C
PHSWR0
4A6[2:0]
14
USART “USART2/3”
Interrupt
multiple OR from
USART2 & USART3
00A7–00A4
ESC23
427[1]
339
PSC23
4A4[6:4]
11
USART “USART0/1”
Interrupt
multiple OR from
USART0 & USART1
00A3–00A0
ESC01
427[0]
338
PSC01
4A4[2:0]
10
DMA “DMAH”
Interrupt
multiple OR from
DMA
009B–0098
EDMAH
426[6]
336
PDMAH
4A3[2:0]
8
DMA “DMAL”
Interrupt
multiple OR from
DMA
0097–0094
EDMAL
426[5]
335
PDMAL
4A2[6:4]
7
External Interrupt 2
(INT2)
IE2
MMR 2D2[0]
0093–0090
EX2
426[4]
334
PX2
4A2[2:0]
6
Timer 1
TF1
SFR 410[7]
287
008F–008C
ET1
426[3]
333
PT1
4A1[6:4]
5
External Interrupt 1
(INT1)
IE1
SFR 410[3]
283
008B–0088
EX1
426[2]
332
PX1
4A1[2:0]
4
Timer 0
TF0
SFR 410[5]
285
0087–0084
ET0
426[1]
331
PT0
4A0[6:4]
3
External Interrupt 0
(INT0)
IE0
SFR 410[1]
0083–0080
EX0
426[0]
330
PX0
4A0[2:0]
2
SOFTWARE INTERRUPTS
Description
Flag Bit
Vector Address
Enable Bit
Interrupt Priority
Software Interrupt 1
SWR1
0100–0103
SWE1
(fixed at 1)
Software Interrupt 2
SWR2
0104–0107
SWE2
(fixed at 2)
Software Interrupt 3
SWR3
0108–010B
SWE3
(fixed at 3)
Software Interrupt 4
SWR4
010C–010F
SWE4
(fixed at 4)
Software Interrupt 5
SWR5
0110–0113
SWE5
(fixed at 5)
Software Interrupt 6
SWR6
0114–0117
SWE6
(fixed at 6)
Software Interrupt 7
SWR7
0118–011B
SWE7
(fixed at 7)
1999 Sep 24
27
Philips Semiconductors
Preliminary specification
Single-chip 16-bit microcontroller
XA-H4
ABSOLUTE MAXIMUM RATINGS
Rating
Unit
Operating temperature under bias
Parameter
–55 to +125
°C
Storage temperature range
–65 to +150
°C
Voltage on any other pin to VSS
–0.5 to VDD+0.5 V
v
Maximum IOL per I/O pin
15
mA
Power dissipation (based on package heat transfer, not device power consumption)
1.5
W
PRELIMINARY DC ELECTRICAL CHARACTERISTICS
VDD = 5.0 V +/– 10% or 3.3 V +/– 10% unless otherwise specified; Tamb = –40°C to +85°C for industrial, unless otherwise specified.
Symbol
IDD
IID
IPDI
VRAM
Parameter
Power supply current, operating
Power supply current, Idle mode
Power supply current, Power Down mode1
Test Conditions
Limits
Min
Max
5.0 V, 30 MHz
64
80
mA
3.3 V, 30 MHz
55
70
mA
5.0 V, 30 MHz
50
70
mA
3.3 V, 30 MHz
44
60
mA
500
µA
5.0 V, 3.0 V
RAM keep-alive voltage
1.5
VIL
Input low voltage
–0.5
VIH
Input high voltage, except Xtal1, RST
2.2
VIH1
Input high voltage to Xtal1, RST
VOL
Output low voltage all ports8
VOH1
VOH2
CIO
Output high voltage, all ports
Output high voltage, all ports
Unit
Typ
For both 3.0 & 5.0 V
V
0.22 VDD
V
V
0.7 VDD
V
IOL = 3.2 mA, VDD = 4.5 V
0.5
V
IOL = 1.0 mA, VDD = 3.0 V
0.4
V
IOH = –100 µA, VDD = 4.5 V
2.4
V
IOH = –30 µA, VDD = 3.0 V
2.0
V
IOH = 3.2 mA, VDD = 4.5 V
2.4
V
IOH = 1.0 mA, VDD = 3.0 V
2.2
Input/Output pin capacitance
V
15
pF
IIL
Logical 0 input current, all ports7
VIN = 0.45 V
–50
µA
ILI
Input leakage current, all ports6
VIN = VIL or VIH
±10
µA
ITL
Logical 1 to 0 transition current, all ports5
At VDD = 5.5 V
–650
µA
At VDD = 3.6 V
–250
µA
NOTE:
1. VDD must be raised to within the operating range before power down mode is exited.
2. Ports in quasi-bidirectional mode with weak pullup.
3. Ports in PUSH-PULL mode, both pullup and pulldown assumed to be the same strength.
4. In all output modes.
5. Port pins source a transition current when used in quasi-bidirectional mode and externally driven from 1 to 0. This current is highest when
VIN is approximately 2 V.
6. Measured with port in high impedance mode.
7. Measured with port in quasi-bidirectional mode.
8. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
15 mA (NOTE: This is +85°C specification for VDD = 5 V)
Maximum IOL per port pin:
Maximum IOL per 8-bit port:
26 mA
71 mA
Maximum total IOL for all outputs:
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
test conditions.
1999 Sep 24
28
Philips Semiconductors
Preliminary specification
Single-chip 16-bit microcontroller
XA-H4
PRELIMINARY AC ELECTRICAL CHARACTERISTICS (5.0 V +/–10%)
VDD = 5.0 V +/– 10%; Tamb = –40°C to +85°C (industrial)
Symbol
Fig re
Figure
Limits
Parameter
Min
Max
Unit
All Cycles
FC
System Clock Frequency
0
30
MHz
tC
23
System Clock Period = 1/FC
33.33
–
ns
tCHCX
23
XTALIN High Time
tC* 0.5
–
ns
tCLCX
23
XTALIN Low Time
tC* 0.4
–
ns
tCLCH
23
XTALIN Rise Time
–
5
ns
tCHCL
23
XTALIN Fall Time
–
5
ns
tAVSL
All
Address Valid to Strobe low
tC – 21
–
ns
9
tCHAH
All
Address hold after ClkOut rising edge
1
–
ns
tCHAV
All
Delay from ClkOut rising edge to address valid
–
25
ns
tCHSH
All
Delay from ClkOut rising edge to Strobe
High9
1
21
ns
tCHSL
All
Delay from ClkOut rising edge to Strobe Low9
1
19
ns
tCODH
24
ClkOut Duty Cycle High (into 40 pF max.)
tCHCX–7
tCHCX+3
ns
tCPWH
11, 12, 17, 18, 19, 20
CAS Pulse Width High
tC – 12
–
ns
tCPWL
11, 19
CAS Pulse Width Low
tC – 10
–
ns
tRP
22
(n * tC) – 168
–
ns
tC – 12
–
ns
All DRAM Cycles
RAS precharge time, thus minimum RAS high time8
Generic Data Read Only
tAHDR
7, 14
Address hold (A19 – A1 only, not A0) after CS, BLE, BHE rise at
end of Generic Data Read Cycle (not code fetch)
Data Read and Instruction Fetch Cycles
tDIS
7, 8, 10, 11, 12, 14, 15,
17, 18, 19
Data In Valid setup to ClkOut rising edge
25
–
ns
tDIH
7, 8, 10, 14, 15, 17, 18
Data In Valid hold after ClkOut rising edge 2
0
–
ns
tOHDE
8, 10, 11, 14, 18
tC – 14
–
ns
–
25
ns
OE high to XA Data Bus Driver Enable
Write Cycles
tCHDV
9, 13
Clock High to Data Valid
tDVSL
16, 20
Data Valid prior to Strobe Low
tC – 23
–
ns
tSHAH
9, 16
Minimum Address Hold Time after strobe goes inactive
tC – 25
–
ns
tSHDH
9, 16
Data hold after strobes (CS and BHE/BLE) high
tC – 25
–
ns
tC – 15
–
ns
Refresh
tCLRL
21
CAS low to RAS low
tWS
25
WAIT setup (stable high or low) to ClkOut rising edge
20
–
ns
tWH
25
WAIT hold (stable high or low) after ClkOut rising edge
0
–
ns
Wait Input
NOTE:
1. See notes after the 3.3 V AC Timing Table
1999 Sep 24
29
Philips Semiconductors
Preliminary specification
Single-chip 16-bit microcontroller
XA-H4
AC ELECTRICAL CHARACTERISTICS (3.3 V +/–10%)
VDD = 3.3 V +/– 10%; Tamb = –40°C to +85°C (industrial)
Symbol
Fig re
Figure
Limits
Parameter
Min
Max
Unit
All Cycles
FC
System Clock (internally called CClk) Frequency
0
30
MHz
tC
23
System Clock Period = 1/FC
33.33
–
ns
tCHCX
23
XTALIN High Time
tC* 0.5
–
ns
tCLCX
23
XTALIN Low Time
tC* 0.4
–
ns
tCLCH
23
XTALIN Rise Time
–
5
ns
tCHCL
23
XTALIN Fall Time
–
5
ns
tAVSL
All
Address Valid to Strobe low
tC – 21
–
ns
9
tCHAH
All
Address hold after ClkOut rising edge
1
–
ns
tCHAV
All
Delay from ClkOut rising edge to address valid
–
30
ns
tCHSH
All
Delay from ClkOut rising edge to Strobe High
9
1
28
ns
tCHSL
All
Delay from ClkOut rising edge to Strobe Low 9
1
25
ns
tCODH
24
ClkOut Duty Cycle High (into 40 pF max.)
tCHCX–7
tCHCX+3
ns
tCPWH
11, 12, 17, 18, 19, 20
CAS Pulse Width High
tC – 12
–
ns
tCPWL
11, 19
CAS Pulse Width Low
tC – 10
–
ns
tRP
22
(n * tC) – 168
–
ns
tC – 12
–
ns
All DRAM Cycles
RAS precharge time, thus minimum RAS high time8
Data Read Only
tAHDR
7, 14
Address hold (A19 – A1 only, not A0) after CS, BLE, BHE rise at
end of Data Read Cycle (not code fetch)
Data Read and Instruction Fetch Cycles
tDIS
7, 8, 10, 11, 12, 14, 15,
17, 18, 19
Data In Valid setup to ClkOut rising edge
32
–
ns
tDIH
7, 8, 10, 14, 15, 17, 18
Data In Valid hold after ClkOut rising edge 2
0
–
ns
tOHDE
8, 10, 11, 14, 18
tC – 19
–
ns
–
30
ns
OE high to XA Data Bus Driver Enable
Write Cycles
tCHDV
9, 13
Clock High to Data Valid
tDVSL
16, 20
Data Valid prior to Strobe Low
tC – 23
–
ns
tSHAH
9, 16
Minimum Address Hold Time after strobe goes inactive
tC – 25
–
ns
tSHDH
9, 16
Data hold after strobes (CS and BHE/BLE) high
tC – 25
–
ns
tC – 15
–
ns
Refresh
tCLRL
21
CAS low to RAS low
Wait Input
tWS
25
WAIT setup (stable high or low) prior to ClkOut rising edge
25
–
ns
tWH
25
WAIT hold (stable high or low) after ClkOut rising edge
0
–
ns
NOTE:
1. On a 16-bit bus, if only one byte is being written, then only one of BLE_CASL or BHE_CASH will go active. On an 8-bit bus, BLE_CASL
goes active for all (odd or even address) accesses. BHE_CASH will not go active during any accesses on an 8-bit bus.
2. The bus timing is designed to make meeting hold time very straightforward without glue logic. On all generic reads and fetches, in order to
meet hold time, the slave should hold data valid on the bus until the earliest of CS, BHE/BLE, OE, goes high (inactive), or until the address
changes. On all FPM DRAM reads and fetches, hold data valid on the bus until a new CAS is asserted, or until OE goes high (inactive).
3. To avoid 3-State fights during read cycles and fetch cycles, do not drive data bus until OE goes active.
4. To meet hold time, EDO DRAM drives data onto the bus until OE rises, or until a new falling edge of CAS.
5. WARNING: ClkOut is specified at 40 pF max. More than 40 pf on ClkOut may significantly degrade the ClkOut waveform. Load
capacitance for all outputs (except ClkOut) = 80 pF.
6. Not all combinations of bus timing configuration values result in valid bus cycles. Please refer to the XA-H4 User Manual for details.
7. When code is being fetched on the external bus, a burst mode fetch is used. This burst can be from 2 to 16 bytes long. On a 16-bit bus,
A3 – A1 are incremented for each new word of the burst. On an 8-bit bus, A3 – A0 are incremented for each new byte of the burst code fetch.
1999 Sep 24
30
Philips Semiconductors
Preliminary specification
Single-chip 16-bit microcontroller
XA-H4
8. tRP is specified as the minimum high time (thus inactive) on each of the 5 individual CS_RAS[5:1] pins when such pin is programmed in the
memory controller to service DRAM. The number of CClks (system clocks) in tRP is programmable, and is represented by n in the tRP
equation in the AC tables. Regardless of what value is programmed into the control register, n will never be less than 2 clocks. Thus, at
30 Mhz system clock, the minimum value for RAS precharge is tRP=((2 * tC) – 16= ((2 * 33.33) – 16) = 50.6 ns. As the system clock
frequency FC, is slowed down, tC (system clock period) of course becomes greater, and thus tRP becomes greater.
9. The MIN value for this parameter is guaranteed by design and is not tested in production to the specified limit. In those cases where a
maximum value is specified in the table for this parameter, it is tested.
TIMING DIAGRAMS
All references to numbered Notes are to the notes following the AC Electrical Characteristics tables
ClkOut
A0
tCHAV
tCHAH
A19–A1
tCHSL
CS
tAHDR
(Does Not Include A0)
tAVSL
tCHSH
BHE/BLE
OE
Note 3
tDIH (Note 2)
tDIS
D15–D0
Note:
On Generic Data Reads, A0 can terminate a full clock period before A19–A1, and therefore
should not be used on some peripheral devices.
SU01277
Figure 7. Generic (SRAM, ROM, Flash, I/O Devices, etc.) Read on 16-Bit Bus
1999 Sep 24
31
Philips Semiconductors
Preliminary specification
Single-chip 16-bit microcontroller
XA-H4
ClkOut
tCHAV
A[19:0]
tCHAV
Address
tCHAV
Address + 2
Address + 4
tCHSL
tCHSH
tAVSL
CS
BHE/BLE
tOHDE
Note 3
OE
tDIH
Note 2
tDIS
D[15:0]
Note:
tDIH
Note 2
tDIS
tDIS
tDIH
(Note 2)
Driven
by XA
Driven by XA
The processor can prefetch from one to eight words.
SU01131
Figure 8. Generic (SRAM, ROM, Flash, etc.) Burst Code Fetch on 16-Bit Bus
ClkOut
tCHSH
tCHAV
A
tCHSL
CS
tAVSL
tSHAH
Note 1
BHE/BLE
WE
tSHDH
tCHDV
D
SU01278
Figure 9. Generic (SRAM, I/O Devices, etc.) Write
1999 Sep 24
32
Philips Semiconductors
Preliminary specification
Single-chip 16-bit microcontroller
XA-H4
ClkOut
tCHAH
A
RAS ADDRESS
tCHAV
CAS ADDRESS
tCHAV
tCHSL
tCHSH
tAVSL
RAS (CS)
tCHSL
CAS (BHE/BLE)
tAVSL
tCHSH
OE
tOHDE
tDIS
tDIH
Note 2
D
VALID DATA
SU01279
Figure 10. DRAM Single Read Cycle
ClkOut
tCHAH
tCHAH
RAS ADDRESS
A
tCHAV
tCHAV
CAS ADDRESS
tCHAV
tCHSL
tCHAH
CAS ADDRESS +2
tCHSH
tCHSH
tAVSL
RAS (CS)
tCHSL
tCPWH
tAVSL
CAS (BHE/BLE)
OE
tCPWL
tOHDE
Note 3
tDIS
D[15:0]
Driven by XA
Driven by Slave Device
Note 4
Word (from CAS Addr)
tDIS
Note 4
Word (from CAS Addr +2)
4 Byte Fetch (1 Word = 2 Bytes) is shown on 16-bit bus, burst can be 2 to 16 bytes (1 to 8 words).
SU01280
Figure 11. DRAM EDO Burst Code Fetch on 16-Bit Bus
1999 Sep 24
33
Philips Semiconductors
Preliminary specification
Single-chip 16-bit microcontroller
XA-H4
ClkOut
tCHAV
tCHSL
tCHAV
RAS ADDRESS
A
tCHAV
tCHAV
CAS ADDRESS
CAS ADDRESS +2
tCHAH
tCHSL
tCHAH
tCHAH
tAVSL
RAS
tCHSH
tCHSH
tAVSL
CASL, CASH
tCPWH
tCHSL
OE
tDIS
D[15:0]
Note 2
Note 2
tDIS
INSTRUCTION
Note:
INSTRUCTION
The processor can fetch from one to eight Words (1 Word = 2 bytes)
SU01281
Figure 12. DRAM FPM (Fast Page Mode) Burst Code Fetch
ClkOut
tCHAV
tCHAH
tCHSL
RAS ADDRESS
A
tCHAH
CAS ADDRESS
tCHSH
tCHSL
tAVSL
RAS (CS)
tAVSL
CAS (BHE/BLE)
Note 1
tCHSH
WE
tCHDV
D
Valid Data
Note.
OE is inactive during all writes.
SU01282
Figure 13. DRAM Write (on 16-Bit Bus, also 8-Bit Write on 8-Bit Bus)
1999 Sep 24
34
Philips Semiconductors
Preliminary specification
Single-chip 16-bit microcontroller
XA-H4
ClkOut
A19 – A1
A0
tAHDR
tCHAV
tCHSL
tCHSH
CS
tAVSL
BLE
Note 3
OE
tOHDE
tDIS
D7 – D0
Note 2
tDIH
tDIS
Driven by XA
Note 2
Driven by XA
On all cycles on 8-bit bus, BHE remains high (inactive)
Note:
On the external bus, ALL XA-H4 reads are 16-bit reads. If the CPU instruction only specifies 8-bits, then the CPU uses the appropriate byte, and discards the
extra byte. Thus, “8-Bit Reads” and “16-Bit Reads” appear to be identical on the bus. On an 8-bit bus, this will appear as two consecutive 8-bit reads even
though the CPU will only use one of the two bytes.
WARNING: Some 8-bit I/O devices (especially FIFOS) cannot operate correctly with 2 bytes being read for a one byte read. The most common (and least expensive)
solution is to operate these 8-bit devices on a 16-bit bus, and access them in software on all odd byte (or all even byte) boundaries. An added benefit of this technique is that byte reads are faster than on an 8-bit bus, because only 1 word is fetched (a single read) instead of 2 consecutive bytes.
SU01283
Figure 14. Generic (SRAM, Flash, I/O Device, etc.) Read (16-Bit or 8-Bit) on 8-Bit Bus
Clkout
tCHAV
tCHAV
Even Address
tCHAV
Address + 1
tCHAV
Address + 2
Address + 3
tCHAV
OE, BLE, CS
tCHSH
Note 3
tDIS
tDIH
tDIH
tDIS
Note 2
D[7:0]
Note:
LS Byte
tDIS
Note 2
MS Byte
tDIH
tDIS
Note 2
LS Byte
tDIH
Note 2
MS Byte
BHE remains high (inactive) for all accesses on an 8-bit bus. A burst code fetch can be
from 1 to 8 words (1 word = 2 bytes), a 2 word fetch is shown here.
SU01245
Figure 15. Burst Code Fetch on 8-Bit Bus, Generic Memory
1999 Sep 24
35
Philips Semiconductors
Preliminary specification
Single-chip 16-bit microcontroller
XA-H4
Clkout
tCHAV
tCHSL
tCHSH
A19 – A1
tSHAH
A0
tSHAH
tCHSL
CS
tAVSL
tAVSL
BLE, WE
tSHDH
tDVSL
D7 – D0
Note. OE is inactive during all writes.
SU01246
Figure 16. Generic 16-Bit Write on 8-Bit Bus
ClkOut
tCHAV
CAS ADDRESS
A
tCHAV
tCHAV
CAS ADDRESS EVEN
CAS ADDRESS ODD
tCHAH
tCHSL
RAS
tCHSL
tCHAV
tCHAH
tCHAH
tCHSH
tAVSL
tCHSH
tAVSL
CASL
(CASH stays high)
tCPWH
tCHSL
OE
tDIS
tDIH
Note 2
LS Byte
D[7:0]
tDIS
Note 2
MS Byte
SU01284
Figure 17. 16-Bit Read on 8-Bit Bus, DRAM (both FPM and EDO)
1999 Sep 24
36
Philips Semiconductors
Preliminary specification
Single-chip 16-bit microcontroller
1
2
3
4
5
6
XA-H4
7
8
9
10
11
12
13
14
15
ClkOut
tCHAH
tCHAV
RAS
ADDR
A
CAS ADDR
Even
CAS ADDR
ODD
CAS ADDR
Even
CAS ADDR
ODD
tCHSH
tCHSL
RAS
tAVSL
tCHSL
tCHSH
tAVSL
CASL
tCPWH
tCHSH
OE
tOHDE
tDIS
D[7:0]
tDIH
Note 2
Note 2
LS Byte
tDIH
LS Byte
MS Byte
MS Byte
4-Byte Fetch is shown on 8-bit bus, burst can be 2 to 16 bytes.
Data bus is sampled on the rising edge of clock 6, and every three clocks thereafter (clocks 6, 9, 12, and 15 in this example).
SU01285
Figure 18. DRAM FPM (Fast Page Mode) Burst Code Fetch on 8-Bit Bus
1
2
3
4
5
6
7
8
9
10
11
12
ClkOut
tCHAH
tCHAV
A
RAS ADDRESS
CAS ADDR
EVEN
CAS ADDR
ODD
CAS ADDR
EVEN
CAS ADDR
ODD
tCHSL
tCHSH
tCHSH
RAS
tAVSL
tCHSL
tCPWL
CASL
tCPWH
tAVSL
tCHSH
OE
Note 3
tOHDE
tDIS
Note 4
LS Byte
D[7:0]
Note.
MS Byte
Note 4
LS Byte
MS Byte
4-Byte Fetch is shown on 8-bit bus, burst can be 2 to 16 bytes.
To meet Hold Time, EDO DRAM drives Data until OE rises, or until a new falling edge of CAS.
Data bus is sampled on the rising edge of clock 6, and every three clocks thereafter (clocks 6, 8, 10, and 12 in this example).
SU01286
Figure 19. EDO DRAM Burst Code Fetch on 8-Bit Bus
1999 Sep 24
37
Philips Semiconductors
Preliminary specification
Single-chip 16-bit microcontroller
XA-H4
ClkOut
tCHAV
A
tCHAV
tCHSL
RAS ADDRESS
tCHAH
tCHSL
RAS (CS)
tCHAV
tCHAV
CAS ADDRESS EVEN
CAS ADDRESS ODD
tCHAH
tCHAH
tAVSL
tCHSH
tCHSH
tAVSL
CASL
tCPWH
tCHSL
WE
tDVSL
tDVSL
D[7:0]
LS Byte
MS Byte
SU01287
Figure 20. DRAM 16-Bit Write on 8-Bit Bus (FPM or EDO DRAMs)
ClkOut
tCHSL
RAS
tCLRL
tCHSH
CASH, CASL
RAS and CAS terminate together. The active low portion of RAS can be programmed to last from 3 to 6 clock cycles.
The high portion of RAS after Refresh can be programmed to last from 2 to 4 clock cycles. See Chapter 3 of the XA-H4 User Manual.
SU01288
Figure 21. REFRESH
tRP
RAS
NOTE:
tRP minimum is specified for each of the 5 individual RAS pins (CS_RAS[5:1])
It is the minimum high time (thus RAS inactive) between two DRAM bus cycles on the same RAS pin.
Figure 22. RAS Precharge Time
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SU01289
Philips Semiconductors
Preliminary specification
Single-chip 16-bit microcontroller
XA-H4
VDD – 0.5
0.7 VDD
XTALIN
0.45 V
0.2 VDD – 0.1
tCHCX
tCHCL
tCLCX
tCLCH
tC
SU01146
Figure 23. External Clock Input Drive
tCODH
ClkOut
WARNING: ClkOut is specified into 40 pF max, do not overload.
SU01147
Figure 24. ClkOut Duty Cycle
ClkOut
tWS
tWH
WAIT
tWS – Setup time of WAIT to rising edge of ClkOut.
tWH – Hold time of WAIT after ClkOut High.
SU01148
Figure 25. External WAIT Pin Timing
1999 Sep 24
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Philips Semiconductors
Preliminary specification
Single-chip 16-bit microcontroller
XA-H4
LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm
1999 Sep 24
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SOT407-1
Philips Semiconductors
Preliminary specification
Single-chip 16-bit microcontroller
XA-H4
NOTES
1999 Sep 24
41
Philips Semiconductors
Preliminary specification
Single-chip 16-bit microcontroller
XA-H4
Data sheet status
Data sheet
status
Product
status
Definition [1]
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
 Copyright Philips Electronics North America Corporation 1999
All rights reserved. Printed in U.S.A.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 09-99
Document order number:
1999 Sep 24
42
9397 750 06432